Merge "fix(cpus): check minor revision before applying runtime errata" into integration

fix(cpus): check minor revision before applying runtime errata

Patch db9ee83432 removed cpu_rev checking for runtime errata
within cpu functions with the argument that if we're in the cpu file,
we'v

fix(cpus): check minor revision before applying runtime errata

Patch db9ee83432 removed cpu_rev checking for runtime errata
within cpu functions with the argument that if we're in the cpu file,
we've already check the MIDR and matched against the CPU. However, that
also removes the revision check which being in the cpu file does not
guarantee. Reintroduce the MIDR checking so that the revision check
happens and errata can be skipped if they don't apply.

Change-Id: I46b2ba8b524a073e02b4b5de641ae97795bc176b
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(cpus): remove errata setting PF_MODE to conservative" into integration

fix(cpus): remove errata setting PF_MODE to conservative

The erratum titled “Disabling of data prefetcher with outstanding
prefetch TLB miss might cause a deadlock” should not be handled within
TF-A

fix(cpus): remove errata setting PF_MODE to conservative

The erratum titled “Disabling of data prefetcher with outstanding
prefetch TLB miss might cause a deadlock” should not be handled within
TF-A. The current workaround attempts to follow option 2 but
misapplies it. Specifically, it statically sets PF_MODE to
conservative, which is not the recommended approach. According to the
erratum documentation, PF_MODE should be configured in conservative
mode only when we disable data prefetcher however this is not done
in TF-A and thus the workaround is not needed in TF-A.

The static setting of PF_MODE in TF-A does not correctly address the
erratum and may introduce unnecessary performance degradation on
platforms that adopt it without fully understanding its implications.

To prevent incorrect or unintended use, the current implementation of
this erratum workaround should be removed from TF-A and not adopted by
platforms.

List of Impacted CPU's with Errata Numbers and reference to SDEN -

Cortex-A78 - 2132060 - https://developer.arm.com/documentation/SDEN1401784/latest
Cortex-A78C - 2132064 - https://developer.arm.com/documentation/SDEN-2004089/latest
Cortex-A710 - 2058056 - https://developer.arm.com/documentation/SDEN-1775101/latest
Cortex-X2 - 2058056 - https://developer.arm.com/documentation/SDEN-1775100/latest
Cortex-X3 - 2070301 - https://developer.arm.com/documentation/SDEN2055130/latest
Neoverse-N2 - 2138953 - https://developer.arm.com/documentation/SDEN-1982442/latest
Neoverse-V1 - 2108267 - https://developer.arm.com/documentation/SDEN-1401781/latest
Neoverse-V2 - 2331132 - https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: Icf4048508ae070b2df073cc46c63be058b2779df
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "ar/cvereorder" into integration

* changes:
chore(cpus): rearrange the errata and cve order in Neoverse-N2
chore(cpus): rearrange cve in order in Cortex-X1
chore(cpus)

Merge changes from topic "ar/cvereorder" into integration

* changes:
chore(cpus): rearrange the errata and cve order in Neoverse-N2
chore(cpus): rearrange cve in order in Cortex-X1
chore(cpus): fix cve order in Neoverse-V1
chore(cpus): fix cve order in Cortex-X2
chore(cpus): fix cve order in Cortex-A78C
chore(cpus): fix cve order in Cortex-A78_AE
chore(cpus): fix cve order in Cortex-A78
chore(cpus): fix cve order in Cortex-A77

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chore(cpus): fix cve order in Neoverse-V1

This patch rearranges CVE-2024-5660 apply order in Neoverse-V1.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ice0b1c6efa913f885

chore(cpus): fix cve order in Neoverse-V1

This patch rearranges CVE-2024-5660 apply order in Neoverse-V1.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ice0b1c6efa913f88522fb33182b9cdc0e7723988

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Merge changes from topic "bk/errata_speed" into integration

* changes:
refactor(cpus): declare runtime errata correctly
perf(cpus): make reset errata do fewer branches
perf(cpus): inline the i

Merge changes from topic "bk/errata_speed" into integration

* changes:
refactor(cpus): declare runtime errata correctly
perf(cpus): make reset errata do fewer branches
perf(cpus): inline the init_cpu_data_ptr function
perf(cpus): inline the reset function
perf(cpus): inline the cpu_get_rev_var call
perf(cpus): inline cpu_rev_var checks
refactor(cpus): register DSU errata with the errata framework's wrappers
refactor(cpus): convert checker functions to standard helpers
refactor(cpus): convert the Cortex-A65 to use the errata framework
fix(cpus): declare reset errata correctly

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perf(cpus): make reset errata do fewer branches

Errata application is painful for performance. For a start, it's done
when the core has just come out of reset, which means branch predictors
and cach

perf(cpus): make reset errata do fewer branches

Errata application is painful for performance. For a start, it's done
when the core has just come out of reset, which means branch predictors
and caches will be empty so a branch to a workaround function must be
fetched from memory and that round trip is very slow. Then it also runs
with the I-cache off, which means that the loop to iterate over the
workarounds must also be fetched from memory on each iteration.

We can remove both branches. First, we can simply apply every erratum
directly instead of defining a workaround function and jumping to it.
Currently, no errata that need to be applied at both reset and runtime,
with the same workaround function, exist. If the need arose in future,
this should be achievable with a reset + runtime wrapper combo.

Then, we can construct a function that applies each erratum linearly
instead of looping over the list. If this function is part of the reset
function, then the only "far" branches at reset will be for the checker
functions. Importantly, this mitigates the slowdown even when an erratum
is disabled.

The result is ~50% speedup on N1SDP and ~20% on AArch64 Juno on wakeup
from PSCI calls that end in powerdown. This is roughly back to the
baseline of v2.9, before the errata framework regressed on performance
(or a little better). It is important to note that there are other
slowdowns since then that remain unknown.

Change-Id: Ie4d5288a331b11fd648e5c4a0b652b74160b07b9
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(cpus): declare reset errata correctly

The errata in this patch are declared as runtime, but are never called
explicitly. This means that they are never called! Convert them to reset
errata so th

fix(cpus): declare reset errata correctly

The errata in this patch are declared as runtime, but are never called
explicitly. This means that they are never called! Convert them to reset
errata so that they are called at reset. Their SDENs entries have been
checked and confirm that this is how they should be implemented.

Also, drop the the MIDR check on the a57 erratum as it's not needed -
the erratum is already called from a cpu-specific function.

Change-Id: I22c3043ab454ce94b3c122c856e5804bc2ebb18b
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "sm/fix_erratum" into integration

* changes:
fix(cpus): workaround for CVE-2024-5660 for Cortex-X925
fix(cpus): workaround for CVE-2024-5660 for Cortex-X2
fix(cpus): w

Merge changes from topic "sm/fix_erratum" into integration

* changes:
fix(cpus): workaround for CVE-2024-5660 for Cortex-X925
fix(cpus): workaround for CVE-2024-5660 for Cortex-X2
fix(cpus): workaround for CVE-2024-5660 for Cortex-A77
fix(cpus): workaround for CVE-2024-5660 for Neoverse-V1
fix(cpus): workaround for CVE-2024-5660 for Cortex-A78_AE
fix(cpus): workaround for CVE-2024-5660 for Cortex-A78C
fix(cpus): workaround for CVE-2024-5660 for Cortex-A78
fix(cpus): workaround for CVE-2024-5660 for Cortex-X1
fix(cpus): workaround for CVE-2024-5660 for Neoverse-N2
fix(cpus): workaround for CVE-2024-5660 for Cortex-A710
fix(cpus): workaround for CVE-2024-5660 for Neoverse-V2
fix(cpus): workaround for CVE-2024-5660 for Cortex-X3
fix(cpus): workaround for CVE-2024-5660 for Neoverse-V3
fix(cpus): workaround for CVE-2024-5660 for Cortex-X4

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fix(cpus): workaround for CVE-2024-5660 for Neoverse-V1

Implements mitigation for CVE-2024-5660 that affects Neoverse-V1
revisions r0p0, r1p0, r1p1, r1p2.
The workaround is to disable the hardware p

fix(cpus): workaround for CVE-2024-5660 for Neoverse-V1

Implements mitigation for CVE-2024-5660 that affects Neoverse-V1
revisions r0p0, r1p0, r1p1, r1p2.
The workaround is to disable the hardware page aggregation at
EL3 by setting CPUECTLR_EL1[46] = 1'b1.

Public Documentation:
https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-5660

Change-Id: Ia59452ea38c66b291790956d7f2880bfcd56d45f
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge "chore(cpus): optimise runtime errata applications" into integration

chore(cpus): optimise runtime errata applications

The errata framework has a helper to invoke workarounds, complete with a
cpu rev_var check. We can use that directly instead of the
apply_cpu_pwr_dw

chore(cpus): optimise runtime errata applications

The errata framework has a helper to invoke workarounds, complete with a
cpu rev_var check. We can use that directly instead of the
apply_cpu_pwr_dwn_errata to save on some code, as well as an extra
branch. It's also more readable.

Also, apply_erratum invocation in cpu files don't need to check the
rev_var as that was already done by the cpu_ops dispatcher for us to end
up in the file.

Finally, X2 erratum 2768515 only applies in the powerdown sequence, i.e.
at runtime. It doesn't achieve anything at reset, so we can label it
accordingly.

Change-Id: I02f9dd7d0619feb54c870938ea186be5e3a6ca7b
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "clean-up-errata-compatibility" into integration

* changes:
refactor(cpus): remove cpu specific errata funcs
refactor(cpus): directly invoke errata reporter

refactor(cpus): remove cpu specific errata funcs

Errata printing is done directly via generic_errata_report.
This commit removes the unused \_cpu\()_errata_report
functions for all cores, and remove

refactor(cpus): remove cpu specific errata funcs

Errata printing is done directly via generic_errata_report.
This commit removes the unused \_cpu\()_errata_report
functions for all cores, and removes errata_func from cpu_ops.

Change-Id: I04fefbde5f0ff63b1f1cd17c864557a14070d68c
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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Merge changes from topic "sm/errata" into integration

* changes:
fix(cpus): workaround for Cortex-A78C erratum 2743232
fix(cpus): workaround for Neoverse V1 erratum 2348377
fix(cpus): workarou

Merge changes from topic "sm/errata" into integration

* changes:
fix(cpus): workaround for Cortex-A78C erratum 2743232
fix(cpus): workaround for Neoverse V1 erratum 2348377
fix(cpus): workaround for Cortex-X3 erratum 2779509

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fix(cpus): workaround for Neoverse V1 erratum 2348377

Neoverse V1 erratum 2348377 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL

fix(cpus): workaround for Neoverse V1 erratum 2348377

Neoverse V1 erratum 2348377 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL1[61] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401781/latest

Change-Id: Ica402494f78811c85e56a262e1f60b09915168fe
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge changes from topic "sm/err_errata" into integration

* changes:
fix(cpus): fix the rev-var of Neoverse-V1
fix(errata-abi): update the Neoverse-N2 errata ABI struct
fix(errata-abi): update

Merge changes from topic "sm/err_errata" into integration

* changes:
fix(cpus): fix the rev-var of Neoverse-V1
fix(errata-abi): update the Neoverse-N2 errata ABI struct
fix(errata-abi): update the neoverse-N1 errata ABI struct
fix(cpus): fix the rev-var of Cortex-X2
fix(errata-abi): update the Cortex-A78C errata ABI struct
fix(cpus): update the rev-var for Cortex-A78AE
fix(errata-abi): update the Cortex-A76 errata ABI struct
fix(cpus): fix the rev-var for Cortex-A710

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fix(cpus): fix the rev-var of Neoverse-V1

Update the revision and variant information in the
errata ABI file, neoverse_v1.S file for erratum ID - 2294912
to match the revision and variant in the lat

fix(cpus): fix the rev-var of Neoverse-V1

Update the revision and variant information in the
errata ABI file, neoverse_v1.S file for erratum ID - 2294912
to match the revision and variant in the latest SDEN.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401781/latest

Change-Id: I38a0f53c3515860ba442b5c0872c8ab051fdda6f
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge changes from topic "ar/errata_refactor" into integration

* changes:
refactor(cpus): convert Neoverse V1 to use CPU helpers
refactor(cpus): convert Neoverse V1 to framework
refactor(cpus)

Merge changes from topic "ar/errata_refactor" into integration

* changes:
refactor(cpus): convert Neoverse V1 to use CPU helpers
refactor(cpus): convert Neoverse V1 to framework
refactor(cpus): reorder Neoverse V1 errata by ascending order

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refactor(cpus): convert Neoverse V1 to use CPU helpers

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Idb4b47982278cda93a7c0f0a49dfceb75b8d88e4

refactor(cpus): convert Neoverse V1 to framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report w

refactor(cpus): convert Neoverse V1 to framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive

It is important to note that the errata workaround sequences remain
unchanged and preserve their git blame.

Testing was conducted by:

* Building for release with all errata flags enabled and running script
in change 19136 to compare output of objdump for each errata. Only
able to verify the check functions this way, rest had to manually
verified

* Manual comparison of disassembly of converted functions with non-
converted functions

aarch64-none-elf-objdump -D <trusted-firmware-a with conversion>/build/fvp/release/bl31/bl31.elf
vs
aarch64-none-elf-objdump -D <trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf

* Build for release with all errata flags enabled and run default tftf
tests

CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp DEBUG=0 \
CTX_INCLUDE_AARCH32_REGS=0 HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0 \
BL33=./../tf-a-tests/build/fvp/release/tftf.bin \
ERRATA_V1_1618635=1 ERRATA_V1_1774420=1 ERRATA_V1_1791573=1 \
ERRATA_V1_1852267=1 ERRATA_V1_1925756=1 ERRATA_V1_1940577=1 \
ERRATA_V1_1966096=1 ERRATA_V1_2108267=1 ERRATA_V1_2139242=1 \
ERRATA_V1_2216392=1 ERRATA_V1_2294912=1 ERRATA_V1_2372203=1 \
ERRATA_V1_2743093=1 ERRATA_V1_2743233=1 ERRATA_V1_2779461=1 \
WORKAROUND_CVE_2022_23960=1 ERRATA_ABI_SUPPORT=1 all fip

* Build for debug with all errata enabled and step through ArmDS
at reset to ensure all functions are entered.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ic5697b7cd2a508dee9978d89136fbe168f34626c

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refactor(cpus): reorder Neoverse V1 errata by ascending order

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I1c531fe166218804e4fc9ebbdeda2bfebdd69081

Merge "fix(cpus): workaround for Neoverse V1 errata 2743233" into integration

fix(cpus): workaround for Neoverse V1 errata 2743233

Neoverse V1 erratum 2743233 is a Cat B erratum that applies to
all revisions <= r1p2 and is still open.

The workaround sets CPUACTLR5_EL1[56:55]

fix(cpus): workaround for Neoverse V1 errata 2743233

Neoverse V1 erratum 2743233 is a Cat B erratum that applies to
all revisions <= r1p2 and is still open.

The workaround sets CPUACTLR5_EL1[56:55] to 2'b01.

SDEN documentation: https://developer.arm.com/documentation/SDEN1401781/latest

Change-Id: If51a6f4293fa8b5b35c44edd564ebb715ba309a1
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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