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Searched refs:SCLK_GMAC0_RX_TX (Results 1 – 18 of 18) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3568-evb.dts41 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
H A DOK3568-C.dts41 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
H A D.OK3568-C.dtb.pre.tmp
H A Drk3568-spi-nand.dts135 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
H A Drk3568-u-boot.dtsi244 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
H A Drk3568.dtsi1771 clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
1772 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
1774 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
/OK3568_Linux_fs/u-boot/include/dt-bindings/clock/
H A Drk3568-cru.h452 #define SCLK_GMAC0_RX_TX 389 macro
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Drk3568-cru.h452 #define SCLK_GMAC0_RX_TX 389 macro
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3568-nvr-demo-v10.dtsi118 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
H A Drk3568-evb2-lp4x-v10.dtsi132 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>;
H A Drk3568-evb1-ddr4-v10.dtsi213 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
H A Drk3568-evb5-ddr4-v10.dtsi219 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>;
H A Drk3568-toybrick-x0.dtsi265 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
H A Drk3568.dtsi1782 clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
1783 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
1785 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
H A DOK3568-C-common.dtsi622 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>, <&cru CLK_MAC0_OUT>;
H A DOK-x-U40-common.dtsi1182 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>, <&cru CLK_MAC0_OUT>;
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3568.c2801 case SCLK_GMAC0_RX_TX: in rk3568_clk_set_rate()
3199 case SCLK_GMAC0_RX_TX: in rk3568_clk_set_parent()
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-rk3568.c951 MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p, CLK_SET_RATE_PARENT,