1/* 2 * SPDX-License-Identifier: GPL-2.0+ 3 * 4 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 5 */ 6 7/dts-v1/; 8#include "rk3568.dtsi" 9#include "rk3568-u-boot.dtsi" 10#include <dt-bindings/input/input.h> 11 12/ { 13 model = "Rockchip RK3568 Evaluation Board"; 14 compatible = "rockchip,rk3568-evb", "rockchip,rk3568"; 15 16 adc-keys { 17 compatible = "adc-keys"; 18 io-channels = <&saradc 0>; 19 io-channel-names = "buttons"; 20 keyup-threshold-microvolt = <1800000>; 21 u-boot,dm-spl; 22 status = "okay"; 23 24 volumeup-key { 25 u-boot,dm-spl; 26 linux,code = <KEY_VOLUMEUP>; 27 label = "volume up"; 28 press-threshold-microvolt = <9>; 29 }; 30 }; 31}; 32 33&gmac0 { 34 phy-mode = "rgmii"; 35 clock_in_out = "output"; 36 37 snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; 38 snps,reset-active-low; 39 /* Reset time is 20ms, 100ms for rtl8211f */ 40 snps,reset-delays-us = <0 20000 100000>; 41 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 42 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; 43 assigned-clock-rates = <0>, <125000000>; 44 45 pinctrl-names = "default"; 46 pinctrl-0 = <&gmac0_miim 47 &gmac0_tx_bus2 48 &gmac0_rx_bus2 49 &gmac0_rgmii_clk 50 &gmac0_rgmii_bus>; 51 52 tx_delay = <0x3c>; 53 rx_delay = <0x2f>; 54 55 phy-handle = <&rgmii_phy0>; 56 status = "disabled"; 57}; 58 59&gmac1 { 60 phy-mode = "rgmii"; 61 clock_in_out = "output"; 62 63 snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; 64 snps,reset-active-low; 65 /* Reset time is 20ms, 100ms for rtl8211f */ 66 snps,reset-delays-us = <0 20000 100000>; 67 68 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 69 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; 70 assigned-clock-rates = <0>, <125000000>; 71 72 pinctrl-names = "default"; 73 pinctrl-0 = <&gmac1m1_miim 74 &gmac1m1_tx_bus2 75 &gmac1m1_rx_bus2 76 &gmac1m1_rgmii_clk 77 &gmac1m1_rgmii_bus>; 78 79 tx_delay = <0x4f>; 80 rx_delay = <0x26>; 81 82 phy-handle = <&rgmii_phy1>; 83 status = "disabled"; 84}; 85 86&mdio0 { 87 rgmii_phy0: phy@0 { 88 compatible = "ethernet-phy-ieee802.3-c22"; 89 reg = <0x0>; 90 }; 91}; 92 93&mdio1 { 94 rgmii_phy1: phy@0 { 95 compatible = "ethernet-phy-ieee802.3-c22"; 96 reg = <0x0>; 97 }; 98}; 99 100&crypto { 101 status = "okay"; 102}; 103 104&uart2 { 105 status = "okay"; 106}; 107