1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2020 Rockchip Electronics Co., Ltd 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun#include "rk3568.dtsi" 9*4882a593Smuzhiyun#include "rk3568-u-boot.dtsi" 10*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Rockchip RK3568 Evaluation Board"; 14*4882a593Smuzhiyun compatible = "rockchip,rk3568-evb", "rockchip,rk3568"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun adc-keys { 17*4882a593Smuzhiyun compatible = "adc-keys"; 18*4882a593Smuzhiyun io-channels = <&saradc 0>; 19*4882a593Smuzhiyun io-channel-names = "buttons"; 20*4882a593Smuzhiyun keyup-threshold-microvolt = <1800000>; 21*4882a593Smuzhiyun u-boot,dm-spl; 22*4882a593Smuzhiyun status = "okay"; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun volumeup-key { 25*4882a593Smuzhiyun u-boot,dm-spl; 26*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 27*4882a593Smuzhiyun label = "volume up"; 28*4882a593Smuzhiyun press-threshold-microvolt = <9>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun}; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun&gmac0 { 34*4882a593Smuzhiyun phy-mode = "rgmii"; 35*4882a593Smuzhiyun clock_in_out = "output"; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; 38*4882a593Smuzhiyun snps,reset-active-low; 39*4882a593Smuzhiyun /* Reset time is 20ms, 100ms for rtl8211f */ 40*4882a593Smuzhiyun snps,reset-delays-us = <0 20000 100000>; 41*4882a593Smuzhiyun assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 42*4882a593Smuzhiyun assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; 43*4882a593Smuzhiyun assigned-clock-rates = <0>, <125000000>; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun pinctrl-names = "default"; 46*4882a593Smuzhiyun pinctrl-0 = <&gmac0_miim 47*4882a593Smuzhiyun &gmac0_tx_bus2 48*4882a593Smuzhiyun &gmac0_rx_bus2 49*4882a593Smuzhiyun &gmac0_rgmii_clk 50*4882a593Smuzhiyun &gmac0_rgmii_bus>; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun tx_delay = <0x3c>; 53*4882a593Smuzhiyun rx_delay = <0x2f>; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun phy-handle = <&rgmii_phy0>; 56*4882a593Smuzhiyun status = "disabled"; 57*4882a593Smuzhiyun}; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun&gmac1 { 60*4882a593Smuzhiyun phy-mode = "rgmii"; 61*4882a593Smuzhiyun clock_in_out = "output"; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; 64*4882a593Smuzhiyun snps,reset-active-low; 65*4882a593Smuzhiyun /* Reset time is 20ms, 100ms for rtl8211f */ 66*4882a593Smuzhiyun snps,reset-delays-us = <0 20000 100000>; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 69*4882a593Smuzhiyun assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; 70*4882a593Smuzhiyun assigned-clock-rates = <0>, <125000000>; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun pinctrl-names = "default"; 73*4882a593Smuzhiyun pinctrl-0 = <&gmac1m1_miim 74*4882a593Smuzhiyun &gmac1m1_tx_bus2 75*4882a593Smuzhiyun &gmac1m1_rx_bus2 76*4882a593Smuzhiyun &gmac1m1_rgmii_clk 77*4882a593Smuzhiyun &gmac1m1_rgmii_bus>; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun tx_delay = <0x4f>; 80*4882a593Smuzhiyun rx_delay = <0x26>; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun phy-handle = <&rgmii_phy1>; 83*4882a593Smuzhiyun status = "disabled"; 84*4882a593Smuzhiyun}; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun&mdio0 { 87*4882a593Smuzhiyun rgmii_phy0: phy@0 { 88*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 89*4882a593Smuzhiyun reg = <0x0>; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun}; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun&mdio1 { 94*4882a593Smuzhiyun rgmii_phy1: phy@0 { 95*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 96*4882a593Smuzhiyun reg = <0x0>; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun}; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun&crypto { 101*4882a593Smuzhiyun status = "okay"; 102*4882a593Smuzhiyun}; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun&uart2 { 105*4882a593Smuzhiyun status = "okay"; 106*4882a593Smuzhiyun}; 107