1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include "rk3568.dtsi" 12#include "rk3568-evb.dtsi" 13 14/ { 15 model = "Rockchip RK3568 EVB1 DDR4 V10 Board"; 16 compatible = "rockchip,rk3568-evb1-ddr4-v10", "rockchip,rk3568"; 17 18 vcc2v5_sys: vcc2v5-ddr { 19 compatible = "regulator-fixed"; 20 regulator-name = "vcc2v5-sys"; 21 regulator-always-on; 22 regulator-boot-on; 23 regulator-min-microvolt = <2500000>; 24 regulator-max-microvolt = <2500000>; 25 vin-supply = <&vcc3v3_sys>; 26 }; 27 28 vcc3v3_vga: vcc3v3-vga { 29 compatible = "regulator-fixed"; 30 regulator-name = "vcc3v3_vga"; 31 regulator-always-on; 32 regulator-boot-on; 33 gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; 34 enable-active-high; 35 vin-supply = <&vcc3v3_sys>; 36 }; 37 38 pcie30_avdd0v9: pcie30-avdd0v9 { 39 compatible = "regulator-fixed"; 40 regulator-name = "pcie30_avdd0v9"; 41 regulator-always-on; 42 regulator-boot-on; 43 regulator-min-microvolt = <900000>; 44 regulator-max-microvolt = <900000>; 45 vin-supply = <&vcc3v3_sys>; 46 }; 47 48 pcie30_avdd1v8: pcie30-avdd1v8 { 49 compatible = "regulator-fixed"; 50 regulator-name = "pcie30_avdd1v8"; 51 regulator-always-on; 52 regulator-boot-on; 53 regulator-min-microvolt = <1800000>; 54 regulator-max-microvolt = <1800000>; 55 vin-supply = <&vcc3v3_sys>; 56 }; 57 58 vcc3v3_pcie: gpio-regulator { 59 compatible = "regulator-fixed"; 60 regulator-name = "vcc3v3_pcie"; 61 regulator-min-microvolt = <3300000>; 62 regulator-max-microvolt = <3300000>; 63 enable-active-high; 64 gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; 65 startup-delay-us = <5000>; 66 vin-supply = <&dc_12v>; 67 }; 68 69 vcc3v3_bu: vcc3v3-bu { 70 compatible = "regulator-fixed"; 71 regulator-name = "vcc3v3_bu"; 72 regulator-always-on; 73 regulator-boot-on; 74 regulator-min-microvolt = <3300000>; 75 regulator-max-microvolt = <3300000>; 76 vin-supply = <&vcc5v0_sys>; 77 }; 78 79 vcc_camera: vcc-camera-regulator { 80 compatible = "regulator-fixed"; 81 gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; 82 pinctrl-names = "default"; 83 pinctrl-0 = <&camera_pwr>; 84 regulator-name = "vcc_camera"; 85 enable-active-high; 86 regulator-always-on; 87 regulator-boot-on; 88 }; 89}; 90 91&combphy0_us { 92 status = "okay"; 93}; 94 95&combphy1_usq { 96 status = "okay"; 97}; 98 99&combphy2_psq { 100 status = "okay"; 101}; 102 103&csi2_dphy_hw { 104 status = "okay"; 105}; 106 107&csi2_dphy0 { 108 status = "okay"; 109 110 ports { 111 #address-cells = <1>; 112 #size-cells = <0>; 113 port@0 { 114 reg = <0>; 115 #address-cells = <1>; 116 #size-cells = <0>; 117 118 mipi_in_ucam0: endpoint@1 { 119 reg = <1>; 120 remote-endpoint = <&ucam_out0>; 121 data-lanes = <1 2 3 4>; 122 }; 123 mipi_in_ucam1: endpoint@2 { 124 reg = <2>; 125 remote-endpoint = <&gc8034_out>; 126 data-lanes = <1 2 3 4>; 127 }; 128 mipi_in_ucam2: endpoint@3 { 129 reg = <3>; 130 remote-endpoint = <&ov5695_out>; 131 data-lanes = <1 2>; 132 }; 133 }; 134 port@1 { 135 reg = <1>; 136 #address-cells = <1>; 137 #size-cells = <0>; 138 139 csidphy_out: endpoint@0 { 140 reg = <0>; 141 remote-endpoint = <&isp0_in>; 142 }; 143 }; 144 }; 145}; 146 147/* 148 * video_phy0 needs to be enabled 149 * when dsi0 is enabled 150 */ 151&dsi0 { 152 status = "okay"; 153}; 154 155&dsi0_in_vp0 { 156 status = "disabled"; 157}; 158 159&dsi0_in_vp1 { 160 status = "okay"; 161}; 162 163&dsi0_panel { 164 power-supply = <&vcc3v3_lcd0_n>; 165}; 166 167/* 168 * video_phy1 needs to be enabled 169 * when dsi1 is enabled 170 */ 171&dsi1 { 172 status = "disabled"; 173}; 174 175&dsi1_in_vp0 { 176 status = "disabled"; 177}; 178 179&dsi1_in_vp1 { 180 status = "disabled"; 181}; 182 183&dsi1_panel { 184 power-supply = <&vcc3v3_lcd1_n>; 185}; 186 187&edp { 188 hpd-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; 189 status = "okay"; 190}; 191 192&edp_phy { 193 status = "okay"; 194}; 195 196&edp_in_vp0 { 197 status = "okay"; 198}; 199 200&edp_in_vp1 { 201 status = "disabled"; 202}; 203 204&gmac0 { 205 phy-mode = "rgmii"; 206 clock_in_out = "output"; 207 208 snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; 209 snps,reset-active-low; 210 /* Reset time is 20ms, 100ms for rtl8211f */ 211 snps,reset-delays-us = <0 20000 100000>; 212 213 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 214 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; 215 assigned-clock-rates = <0>, <125000000>; 216 217 pinctrl-names = "default"; 218 pinctrl-0 = <&gmac0_miim 219 &gmac0_tx_bus2 220 &gmac0_rx_bus2 221 &gmac0_rgmii_clk 222 &gmac0_rgmii_bus>; 223 224 tx_delay = <0x3c>; 225 rx_delay = <0x2f>; 226 227 phy-handle = <&rgmii_phy0>; 228 status = "okay"; 229}; 230 231&gmac1 { 232 phy-mode = "rgmii"; 233 clock_in_out = "output"; 234 235 snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; 236 snps,reset-active-low; 237 /* Reset time is 20ms, 100ms for rtl8211f */ 238 snps,reset-delays-us = <0 20000 100000>; 239 240 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 241 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; 242 assigned-clock-rates = <0>, <125000000>; 243 244 pinctrl-names = "default"; 245 pinctrl-0 = <&gmac1m1_miim 246 &gmac1m1_tx_bus2 247 &gmac1m1_rx_bus2 248 &gmac1m1_rgmii_clk 249 &gmac1m1_rgmii_bus>; 250 251 tx_delay = <0x4f>; 252 rx_delay = <0x26>; 253 254 phy-handle = <&rgmii_phy1>; 255 status = "okay"; 256}; 257 258/* 259 * power-supply should switche to vcc3v3_lcd1_n 260 * when mipi panel is connected to dsi1. 261 */ 262>1x { 263 power-supply = <&vcc3v3_lcd0_n>; 264}; 265 266&i2c4 { 267 status = "okay"; 268 gc8034: gc8034@37 { 269 compatible = "galaxycore,gc8034"; 270 status = "okay"; 271 reg = <0x37>; 272 clocks = <&cru CLK_CIF_OUT>; 273 clock-names = "xvclk"; 274 pinctrl-names = "default"; 275 pinctrl-0 = <&cif_clk>; 276 reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; 277 pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>; 278 rockchip,grf = <&grf>; 279 rockchip,camera-module-index = <0>; 280 rockchip,camera-module-facing = "back"; 281 rockchip,camera-module-name = "RK-CMK-8M-2-v1"; 282 rockchip,camera-module-lens-name = "CK8401"; 283 port { 284 gc8034_out: endpoint { 285 remote-endpoint = <&mipi_in_ucam1>; 286 data-lanes = <1 2 3 4>; 287 }; 288 }; 289 }; 290 os04a10: os04a10@36 { 291 compatible = "ovti,os04a10"; 292 reg = <0x36>; 293 clocks = <&cru CLK_CIF_OUT>; 294 clock-names = "xvclk"; 295 power-domains = <&power RK3568_PD_VI>; 296 pinctrl-names = "default"; 297 pinctrl-0 = <&cif_clk>; 298 reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; 299 pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; 300 rockchip,camera-module-index = <0>; 301 rockchip,camera-module-facing = "back"; 302 rockchip,camera-module-name = "CMK-OT1607-FV1"; 303 rockchip,camera-module-lens-name = "M12-40IRC-4MP-F16"; 304 port { 305 ucam_out0: endpoint { 306 remote-endpoint = <&mipi_in_ucam0>; 307 data-lanes = <1 2 3 4>; 308 }; 309 }; 310 }; 311 ov5695: ov5695@36 { 312 status = "okay"; 313 compatible = "ovti,ov5695"; 314 reg = <0x36>; 315 clocks = <&cru CLK_CIF_OUT>; 316 clock-names = "xvclk"; 317 power-domains = <&power RK3568_PD_VI>; 318 pinctrl-names = "default"; 319 pinctrl-0 = <&cif_clk>; 320 reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; 321 pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; 322 rockchip,camera-module-index = <0>; 323 rockchip,camera-module-facing = "back"; 324 rockchip,camera-module-name = "TongJu"; 325 rockchip,camera-module-lens-name = "CHT842-MD"; 326 port { 327 ov5695_out: endpoint { 328 remote-endpoint = <&mipi_in_ucam2>; 329 data-lanes = <1 2>; 330 }; 331 }; 332 }; 333}; 334 335&mdio0 { 336 rgmii_phy0: phy@0 { 337 compatible = "ethernet-phy-ieee802.3-c22"; 338 reg = <0x0>; 339 }; 340}; 341 342&mdio1 { 343 rgmii_phy1: phy@0 { 344 compatible = "ethernet-phy-ieee802.3-c22"; 345 reg = <0x0>; 346 }; 347}; 348 349&video_phy0 { 350 status = "okay"; 351}; 352 353&video_phy1 { 354 status = "disabled"; 355}; 356 357&pcie30phy { 358 status = "okay"; 359}; 360 361&pcie3x2 { 362 reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; 363 vpcie3v3-supply = <&vcc3v3_pcie>; 364 status = "okay"; 365}; 366 367&pinctrl { 368 cam { 369 camera_pwr: camera-pwr { 370 rockchip,pins = 371 /* camera power en */ 372 <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 373 }; 374 }; 375 headphone { 376 hp_det: hp-det { 377 rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; 378 }; 379 }; 380 381 wireless-wlan { 382 wifi_host_wake_irq: wifi-host-wake-irq { 383 rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; 384 }; 385 }; 386 387 wireless-bluetooth { 388 uart8_gpios: uart8-gpios { 389 rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 390 }; 391 }; 392}; 393 394&rk809_sound { 395 hp-det-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; 396}; 397 398&rkisp { 399 status = "okay"; 400}; 401 402&rkisp_mmu { 403 status = "okay"; 404}; 405 406&rkisp_vir0 { 407 status = "okay"; 408 409 port { 410 #address-cells = <1>; 411 #size-cells = <0>; 412 413 isp0_in: endpoint@0 { 414 reg = <0>; 415 remote-endpoint = <&csidphy_out>; 416 }; 417 }; 418}; 419 420&route_dsi0 { 421 status = "okay"; 422 connect = <&vp1_out_dsi0>; 423}; 424 425&route_edp { 426 status = "okay"; 427 connect = <&vp0_out_edp>; 428}; 429 430&sata2 { 431 status = "okay"; 432}; 433 434&sdmmc2 { 435 max-frequency = <150000000>; 436 no-sd; 437 no-mmc; 438 bus-width = <4>; 439 disable-wp; 440 cap-sd-highspeed; 441 cap-sdio-irq; 442 keep-power-in-suspend; 443 mmc-pwrseq = <&sdio_pwrseq>; 444 non-removable; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; 447 sd-uhs-sdr104; 448 status = "okay"; 449}; 450 451&spdif_8ch { 452 status = "okay"; 453 pinctrl-names = "default"; 454 pinctrl-0 = <&spdifm1_tx>; 455}; 456 457&uart8 { 458 status = "okay"; 459 pinctrl-names = "default"; 460 pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; 461}; 462 463&vcc3v3_lcd0_n { 464 gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; 465 enable-active-high; 466}; 467 468&vcc3v3_lcd1_n { 469 gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; 470 enable-active-high; 471}; 472 473&wireless_wlan { 474 pinctrl-names = "default"; 475 pinctrl-0 = <&wifi_host_wake_irq>; 476 WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; 477}; 478 479&wireless_bluetooth { 480 compatible = "bluetooth-platdata"; 481 clocks = <&rk809 1>; 482 clock-names = "ext_clock"; 483 //wifi-bt-power-toggle; 484 uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; 485 pinctrl-names = "default", "rts_gpio"; 486 pinctrl-0 = <&uart8m0_rtsn>; 487 pinctrl-1 = <&uart8_gpios>; 488 BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; 489 BT,wake_gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; 490 BT,wake_host_irq = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; 491 status = "okay"; 492}; 493