xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/OK3568-C-common.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/dts-v1/;
2*4882a593Smuzhiyun
3*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
4*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h>
5*4882a593Smuzhiyun#include <dt-bindings/input/rk-input.h>
6*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h>
7*4882a593Smuzhiyun#include <dt-bindings/display/rockchip_vop.h>
8*4882a593Smuzhiyun#include <dt-bindings/display/media-bus-format.h>
9*4882a593Smuzhiyun#include "rk3568.dtsi"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun	model = "Forlinx OK3568-C Board";
15*4882a593Smuzhiyun	compatible = "forlinx,ok3568", "rockchip,rk3568-evb1-ddr4-v10", "rockchip,rk3568";
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun	forlinx_control {
18*4882a593Smuzhiyun		status = "disabled";
19*4882a593Smuzhiyun		video-hdmi = "hdmi";
20*4882a593Smuzhiyun		video-mipi-edp = "mipi";
21*4882a593Smuzhiyun		video-lvds-rgb = "lvds";
22*4882a593Smuzhiyun	};
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun	edp-panel {
25*4882a593Smuzhiyun		compatible = "simple-panel";
26*4882a593Smuzhiyun		prepare-delay-ms = <120>;
27*4882a593Smuzhiyun		enable-delay-ms = <120>;
28*4882a593Smuzhiyun		unprepare-delay-ms = <120>;
29*4882a593Smuzhiyun		disable-delay-ms = <120>;
30*4882a593Smuzhiyun		backlight = <&edp_backlight>;
31*4882a593Smuzhiyun		enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun		port {
34*4882a593Smuzhiyun			panel_in_edp: endpoint {
35*4882a593Smuzhiyun				remote-endpoint = <&edp_out_panel>;
36*4882a593Smuzhiyun			};
37*4882a593Smuzhiyun		};
38*4882a593Smuzhiyun	};
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun	panel {
41*4882a593Smuzhiyun		compatible = "simple-panel";
42*4882a593Smuzhiyun		backlight = <&lvds_backlight>;
43*4882a593Smuzhiyun		power-supply = <&vcc3v3_lcd2_n>;
44*4882a593Smuzhiyun		enable-delay-ms = <20>;
45*4882a593Smuzhiyun		prepare-delay-ms = <20>;
46*4882a593Smuzhiyun		unprepare-delay-ms = <20>;
47*4882a593Smuzhiyun		disable-delay-ms = <20>;
48*4882a593Smuzhiyun		bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
49*4882a593Smuzhiyun		width-mm = <152>;
50*4882a593Smuzhiyun		height-mm = <91>;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun		display-timings {
53*4882a593Smuzhiyun			native-mode = <&timing0>;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun			timing0: timing0 {
56*4882a593Smuzhiyun				clock-frequency = <71000000>;
57*4882a593Smuzhiyun				hactive = <1280>;
58*4882a593Smuzhiyun				vactive = <800>;
59*4882a593Smuzhiyun				hback-porch = <10>;
60*4882a593Smuzhiyun				hfront-porch = <140>;
61*4882a593Smuzhiyun				vback-porch = <1>;
62*4882a593Smuzhiyun				vfront-porch = <2>;
63*4882a593Smuzhiyun				hsync-len = <10>;
64*4882a593Smuzhiyun				vsync-len = <20>;
65*4882a593Smuzhiyun				hsync-active = <0>;
66*4882a593Smuzhiyun				vsync-active = <1>;
67*4882a593Smuzhiyun				de-active = <1>;
68*4882a593Smuzhiyun				pixelclk-active = <0>;
69*4882a593Smuzhiyun			};
70*4882a593Smuzhiyun		};
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun		ports {
73*4882a593Smuzhiyun			#address-cells = <1>;
74*4882a593Smuzhiyun			#size-cells = <0>;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun			port@0 {
77*4882a593Smuzhiyun				reg = <0>;
78*4882a593Smuzhiyun				dual-lvds-even-pixels;
79*4882a593Smuzhiyun				panel_in_lvds: endpoint {
80*4882a593Smuzhiyun					remote-endpoint = <&lvds_out_panel>;
81*4882a593Smuzhiyun				};
82*4882a593Smuzhiyun			};
83*4882a593Smuzhiyun		};
84*4882a593Smuzhiyun	};
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun	rgb-panel {
87*4882a593Smuzhiyun                compatible = "simple-panel";
88*4882a593Smuzhiyun                backlight = <&lvds_backlight>;
89*4882a593Smuzhiyun                power-supply = <&vcc3v3_lcd2_n>;
90*4882a593Smuzhiyun                bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun                display-timings {
93*4882a593Smuzhiyun                        native-mode = <&timing1>;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun                        timing1: timing1 {
96*4882a593Smuzhiyun                               clock-frequency = <51200000>;
97*4882a593Smuzhiyun                               hactive = <1024>;
98*4882a593Smuzhiyun                               vactive = <600>;
99*4882a593Smuzhiyun                               hfront-porch = <160>;
100*4882a593Smuzhiyun                               hback-porch = <320>;
101*4882a593Smuzhiyun                               hsync-len = <1>;
102*4882a593Smuzhiyun                               vback-porch = <35>;
103*4882a593Smuzhiyun                               vfront-porch = <12>;
104*4882a593Smuzhiyun                               vsync-len = <1>;
105*4882a593Smuzhiyun                               hsync-active = <0>;
106*4882a593Smuzhiyun                               vsync-active = <0>;
107*4882a593Smuzhiyun                               de-active = <1>;
108*4882a593Smuzhiyun                               pixelclk-active = <1>;
109*4882a593Smuzhiyun                        };
110*4882a593Smuzhiyun                };
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun                ports {
113*4882a593Smuzhiyun                        #address-cells = <1>;
114*4882a593Smuzhiyun                        #size-cells = <0>;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun                        port@0 {
117*4882a593Smuzhiyun                                reg = <0>;
118*4882a593Smuzhiyun                                panel_in_rgb: endpoint {
119*4882a593Smuzhiyun                                        remote-endpoint = <&rgb_out_panel>;
120*4882a593Smuzhiyun                                };
121*4882a593Smuzhiyun                        };
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun                };
124*4882a593Smuzhiyun        };
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun	adc_keys: adc-keys {
127*4882a593Smuzhiyun		compatible = "adc-keys";
128*4882a593Smuzhiyun		io-channels = <&saradc 0>;
129*4882a593Smuzhiyun		io-channel-names = "buttons";
130*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
131*4882a593Smuzhiyun		poll-interval = <100>;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun		vol-up-key {
134*4882a593Smuzhiyun			label = "volume up";
135*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
136*4882a593Smuzhiyun			press-threshold-microvolt = <1750>;
137*4882a593Smuzhiyun		};
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun		vol-down-key {
140*4882a593Smuzhiyun			label = "volume down";
141*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
142*4882a593Smuzhiyun			press-threshold-microvolt = <297500>;
143*4882a593Smuzhiyun		};
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun		menu-key {
146*4882a593Smuzhiyun			label = "menu";
147*4882a593Smuzhiyun			linux,code = <KEY_MENU>;
148*4882a593Smuzhiyun			press-threshold-microvolt = <980000>;
149*4882a593Smuzhiyun		};
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun		back-key {
152*4882a593Smuzhiyun			label = "back";
153*4882a593Smuzhiyun			linux,code = <KEY_BACK>;
154*4882a593Smuzhiyun			press-threshold-microvolt = <1305500>;
155*4882a593Smuzhiyun		};
156*4882a593Smuzhiyun	};
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun	leds: leds {
159*4882a593Smuzhiyun		compatible = "gpio-leds";
160*4882a593Smuzhiyun		work_led: work {
161*4882a593Smuzhiyun			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
162*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
163*4882a593Smuzhiyun		};
164*4882a593Smuzhiyun	};
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun	hdmi_sound: hdmi-sound {
167*4882a593Smuzhiyun		status = "okay";
168*4882a593Smuzhiyun		compatible = "rockchip,hdmi";
169*4882a593Smuzhiyun		rockchip,mclk-fs = <128>;
170*4882a593Smuzhiyun		rockchip,card-name = "rockchip,hdmi";
171*4882a593Smuzhiyun		rockchip,cpu = <&i2s0_8ch>;
172*4882a593Smuzhiyun		rockchip,codec = <&hdmi>;
173*4882a593Smuzhiyun		rockchip,jack-det;
174*4882a593Smuzhiyun	};
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun	pdmics: dummy-codec {
177*4882a593Smuzhiyun		status = "disabled";
178*4882a593Smuzhiyun		compatible = "rockchip,dummy-codec";
179*4882a593Smuzhiyun		#sound-dai-cells = <0>;
180*4882a593Smuzhiyun	};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun	pdm_mic_array: pdm-mic-array {
183*4882a593Smuzhiyun		status = "disabled";
184*4882a593Smuzhiyun		compatible = "simple-audio-card";
185*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,pdm-mic-array";
186*4882a593Smuzhiyun		simple-audio-card,cpu {
187*4882a593Smuzhiyun			sound-dai = <&pdm>;
188*4882a593Smuzhiyun		};
189*4882a593Smuzhiyun		simple-audio-card,codec {
190*4882a593Smuzhiyun			sound-dai = <&pdmics>;
191*4882a593Smuzhiyun		};
192*4882a593Smuzhiyun	};
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun	audiopwmout_diff: audiopwmout-diff {
195*4882a593Smuzhiyun		status = "disabled";
196*4882a593Smuzhiyun		compatible = "simple-audio-card";
197*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
198*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,audiopwmout-diff";
199*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
200*4882a593Smuzhiyun		simple-audio-card,bitclock-master = <&master>;
201*4882a593Smuzhiyun		simple-audio-card,frame-master = <&master>;
202*4882a593Smuzhiyun		simple-audio-card,cpu {
203*4882a593Smuzhiyun			sound-dai = <&i2s3_2ch>;
204*4882a593Smuzhiyun		};
205*4882a593Smuzhiyun		master: simple-audio-card,codec {
206*4882a593Smuzhiyun			sound-dai = <&dig_acodec>;
207*4882a593Smuzhiyun		};
208*4882a593Smuzhiyun	};
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun	rk809_sound: rk809-sound {
212*4882a593Smuzhiyun		status = "okay";
213*4882a593Smuzhiyun		compatible = "rockchip,multicodecs-card";
214*4882a593Smuzhiyun                rockchip,card-name = "rockchip-rk809";
215*4882a593Smuzhiyun                hp-det-gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
216*4882a593Smuzhiyun                rockchip,format = "i2s";
217*4882a593Smuzhiyun                rockchip,mclk-fs = <256>;
218*4882a593Smuzhiyun                rockchip,cpu = <&i2s1_8ch>;
219*4882a593Smuzhiyun                rockchip,codec = <&rk809_codec>;
220*4882a593Smuzhiyun                pinctrl-names = "default";
221*4882a593Smuzhiyun                pinctrl-0 = <&hp_det>;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun	};
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun	spdif-sound {
226*4882a593Smuzhiyun		status = "disabled";
227*4882a593Smuzhiyun		compatible = "simple-audio-card";
228*4882a593Smuzhiyun		simple-audio-card,name = "ROCKCHIP,SPDIF";
229*4882a593Smuzhiyun		simple-audio-card,cpu {
230*4882a593Smuzhiyun				sound-dai = <&spdif_8ch>;
231*4882a593Smuzhiyun		};
232*4882a593Smuzhiyun		simple-audio-card,codec {
233*4882a593Smuzhiyun				sound-dai = <&spdif_out>;
234*4882a593Smuzhiyun		};
235*4882a593Smuzhiyun	};
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun	spdif_out: spdif-out {
238*4882a593Smuzhiyun			status = "disabled";
239*4882a593Smuzhiyun			compatible = "linux,spdif-dit";
240*4882a593Smuzhiyun			#sound-dai-cells = <0>;
241*4882a593Smuzhiyun	};
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun	vcc12v: vcc-12v {
244*4882a593Smuzhiyun		compatible = "regulator-fixed";
245*4882a593Smuzhiyun		regulator-name = "vcc12v";
246*4882a593Smuzhiyun		regulator-always-on;
247*4882a593Smuzhiyun		regulator-boot-on;
248*4882a593Smuzhiyun		regulator-min-microvolt = <12000000>;
249*4882a593Smuzhiyun		regulator-max-microvolt = <12000000>;
250*4882a593Smuzhiyun	};
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun	vcc5v0_sys: vcc5v0-sys {
253*4882a593Smuzhiyun		compatible = "regulator-fixed";
254*4882a593Smuzhiyun		regulator-name = "vcc5v0_sys";
255*4882a593Smuzhiyun		regulator-always-on;
256*4882a593Smuzhiyun		regulator-boot-on;
257*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
258*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
259*4882a593Smuzhiyun		vin-supply = <&vcc12v>;
260*4882a593Smuzhiyun	};
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun	vcc3v3_sys: vcc3v3-sys {
263*4882a593Smuzhiyun		compatible = "regulator-fixed";
264*4882a593Smuzhiyun		regulator-name = "vcc3v3_sys";
265*4882a593Smuzhiyun		regulator-always-on;
266*4882a593Smuzhiyun		regulator-boot-on;
267*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
268*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
269*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
270*4882a593Smuzhiyun	};
271*4882a593Smuzhiyun	vcc3v3_pcie: vcc3v3-pcie {
272*4882a593Smuzhiyun		compatible = "regulator-gpio";
273*4882a593Smuzhiyun		regulator-name = "vcc3v3_pcie";
274*4882a593Smuzhiyun		regulator-min-microvolt = <100000>;
275*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
276*4882a593Smuzhiyun		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
277*4882a593Smuzhiyun		gpios-states = <0x1>;
278*4882a593Smuzhiyun		states = <100000 0x0
279*4882a593Smuzhiyun				3300000 0x1>;
280*4882a593Smuzhiyun	};
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun	//for main board
283*4882a593Smuzhiyun	vcc3v3: vcc-3v3 {
284*4882a593Smuzhiyun		compatible = "regulator-fixed";
285*4882a593Smuzhiyun		regulator-name = "vcc3v3";
286*4882a593Smuzhiyun		regulator-always-on;
287*4882a593Smuzhiyun		regulator-boot-on;
288*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
289*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
290*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
291*4882a593Smuzhiyun	};
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun	vcc1v8: vcc-1v8 {
294*4882a593Smuzhiyun		compatible = "regulator-fixed";
295*4882a593Smuzhiyun		regulator-name = "vcc1v8";
296*4882a593Smuzhiyun		regulator-always-on;
297*4882a593Smuzhiyun		regulator-boot-on;
298*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
299*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
300*4882a593Smuzhiyun		vin-supply = <&vcc3v3>;
301*4882a593Smuzhiyun	};
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun	vcc1v2: vcc-1v2 {
304*4882a593Smuzhiyun		compatible = "regulator-fixed";
305*4882a593Smuzhiyun		regulator-name = "vcc1v2";
306*4882a593Smuzhiyun		regulator-always-on;
307*4882a593Smuzhiyun		regulator-boot-on;
308*4882a593Smuzhiyun		regulator-min-microvolt = <1200000>;
309*4882a593Smuzhiyun		regulator-max-microvolt = <1200000>;
310*4882a593Smuzhiyun		vin-supply = <&vcc3v3>;
311*4882a593Smuzhiyun	};
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun	vcc2v8: vcc-2v8 {
314*4882a593Smuzhiyun		compatible = "regulator-fixed";
315*4882a593Smuzhiyun		regulator-name = "vcc2v8";
316*4882a593Smuzhiyun		regulator-always-on;
317*4882a593Smuzhiyun		regulator-boot-on;
318*4882a593Smuzhiyun		regulator-min-microvolt = <2800000>;
319*4882a593Smuzhiyun		regulator-max-microvolt = <2800000>;
320*4882a593Smuzhiyun		vin-supply = <&vcc3v3>;
321*4882a593Smuzhiyun	};
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun	vcc3v3_lcd2_n: vcc3v3-lcd2-n {
324*4882a593Smuzhiyun		compatible = "regulator-fixed";
325*4882a593Smuzhiyun		regulator-name = "vcc3v3_lcd2_n";
326*4882a593Smuzhiyun		regulator-boot-on;
327*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
328*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
329*4882a593Smuzhiyun		enable-active-high;
330*4882a593Smuzhiyun		gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
331*4882a593Smuzhiyun		vin-supply = <&vcc3v3_sys>;
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun		regulator-state-mem {
334*4882a593Smuzhiyun			regulator-off-in-suspend;
335*4882a593Smuzhiyun		};
336*4882a593Smuzhiyun	};
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun	sdio_pwrseq: sdio-pwrseq {
339*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
340*4882a593Smuzhiyun		clocks = <&rk809 1>;
341*4882a593Smuzhiyun		clock-names = "ext_clock";
342*4882a593Smuzhiyun		pinctrl-names = "default";
343*4882a593Smuzhiyun		pinctrl-0 = <&wifi_enable_h>;
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun		/*
346*4882a593Smuzhiyun		 * On the module itself this is one of these (depending
347*4882a593Smuzhiyun		 * on the actual card populated):
348*4882a593Smuzhiyun		 * - SDIO_RESET_L_WL_REG_ON
349*4882a593Smuzhiyun		 * - PDN (power down when low)
350*4882a593Smuzhiyun		 */
351*4882a593Smuzhiyun		post-power-on-delay-ms = <200>;
352*4882a593Smuzhiyun		reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
353*4882a593Smuzhiyun	};
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun	vcc2v5_sys: vcc2v5-ddr {
356*4882a593Smuzhiyun		compatible = "regulator-fixed";
357*4882a593Smuzhiyun		regulator-name = "vcc2v5-sys";
358*4882a593Smuzhiyun		regulator-always-on;
359*4882a593Smuzhiyun		regulator-boot-on;
360*4882a593Smuzhiyun		regulator-min-microvolt = <2500000>;
361*4882a593Smuzhiyun		regulator-max-microvolt = <2500000>;
362*4882a593Smuzhiyun		vin-supply = <&vcc3v3_sys>;
363*4882a593Smuzhiyun	};
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun	5g-rst {
366*4882a593Smuzhiyun        compatible = "regulator-fixed";
367*4882a593Smuzhiyun        regulator-name = "5g-rst";
368*4882a593Smuzhiyun        regulator-min-microvolt = <3300000>;
369*4882a593Smuzhiyun        regulator-max-microvolt = <3300000>;
370*4882a593Smuzhiyun        gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>;
371*4882a593Smuzhiyun        enable-active-low;
372*4882a593Smuzhiyun        regulator-boot-on;
373*4882a593Smuzhiyun        regulator-always-on;
374*4882a593Smuzhiyun		pinctrl-names = "default";
375*4882a593Smuzhiyun		pinctrl-0 = <&net_5g_rst_gpio>;
376*4882a593Smuzhiyun        status = "okay";
377*4882a593Smuzhiyun    };
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun    5g-pwr {
380*4882a593Smuzhiyun        compatible = "regulator-fixed";
381*4882a593Smuzhiyun        regulator-name = "5g-pwr";
382*4882a593Smuzhiyun        regulator-min-microvolt = <3300000>;
383*4882a593Smuzhiyun        regulator-max-microvolt = <3300000>;
384*4882a593Smuzhiyun        gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
385*4882a593Smuzhiyun        enable-active-high;
386*4882a593Smuzhiyun        regulator-boot-on;
387*4882a593Smuzhiyun        regulator-always-on;
388*4882a593Smuzhiyun		pinctrl-names = "default";
389*4882a593Smuzhiyun		pinctrl-0 = <&net_5g_pwr_gpio>;
390*4882a593Smuzhiyun        status = "okay";
391*4882a593Smuzhiyun    };
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun	fiq-debugger {
394*4882a593Smuzhiyun		compatible = "rockchip,fiq-debugger";
395*4882a593Smuzhiyun		rockchip,serial-id = <2>;
396*4882a593Smuzhiyun		rockchip,wake-irq = <0>;
397*4882a593Smuzhiyun		/* If enable uart uses irq instead of fiq */
398*4882a593Smuzhiyun		rockchip,irq-mode-enable = <1>;
399*4882a593Smuzhiyun		rockchip,baudrate = <115200>;  /* Only 115200 and 1500000 */
400*4882a593Smuzhiyun		interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>;
401*4882a593Smuzhiyun		pinctrl-names = "default";
402*4882a593Smuzhiyun		pinctrl-0 = <&uart2m0_xfer>;
403*4882a593Smuzhiyun		status = "okay";
404*4882a593Smuzhiyun	};
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun	debug: debug@fd904000 {
407*4882a593Smuzhiyun		compatible = "rockchip,debug";
408*4882a593Smuzhiyun		reg = <0x0 0xfd904000 0x0 0x1000>,
409*4882a593Smuzhiyun			<0x0 0xfd905000 0x0 0x1000>,
410*4882a593Smuzhiyun			<0x0 0xfd906000 0x0 0x1000>,
411*4882a593Smuzhiyun			<0x0 0xfd907000 0x0 0x1000>;
412*4882a593Smuzhiyun	};
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun	cspmu: cspmu@fd90c000 {
415*4882a593Smuzhiyun		compatible = "rockchip,cspmu";
416*4882a593Smuzhiyun		reg = <0x0 0xfd90c000 0x0 0x1000>,
417*4882a593Smuzhiyun			<0x0 0xfd90d000 0x0 0x1000>,
418*4882a593Smuzhiyun			<0x0 0xfd90e000 0x0 0x1000>,
419*4882a593Smuzhiyun			<0x0 0xfd90f000 0x0 0x1000>;
420*4882a593Smuzhiyun	};
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun	test-power {
423*4882a593Smuzhiyun		status = "okay";
424*4882a593Smuzhiyun	};
425*4882a593Smuzhiyun	dsi1_backlight: dsi1-backlight {
426*4882a593Smuzhiyun		compatible = "pwm-backlight";
427*4882a593Smuzhiyun		pwms = <&pwm5 0 20000 0>;
428*4882a593Smuzhiyun		brightness-levels = <
429*4882a593Smuzhiyun			  0  20  20  21  21  22  22  23
430*4882a593Smuzhiyun			 23  24  24  25  25  26  26  27
431*4882a593Smuzhiyun			 27  28  28  29  29  30  30  31
432*4882a593Smuzhiyun			 31  32  32  33  33  34  34  35
433*4882a593Smuzhiyun			 35  36  36  37  37  38  38  39
434*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
435*4882a593Smuzhiyun			 48  49  50  51  52  53  54  55
436*4882a593Smuzhiyun			 56  57  58  59  60  61  62  63
437*4882a593Smuzhiyun			 64  65  66  67  68  69  70  71
438*4882a593Smuzhiyun			 72  73  74  75  76  77  78  79
439*4882a593Smuzhiyun			 80  81  82  83  84  85  86  87
440*4882a593Smuzhiyun			 88  89  90  91  92  93  94  95
441*4882a593Smuzhiyun			 96  97  98  99 100 101 102 103
442*4882a593Smuzhiyun			104 105 106 107 108 109 110 111
443*4882a593Smuzhiyun			112 113 114 115 116 117 118 119
444*4882a593Smuzhiyun			120 121 122 123 124 125 126 127
445*4882a593Smuzhiyun			128 129 130 131 132 133 134 135
446*4882a593Smuzhiyun			136 137 138 139 140 141 142 143
447*4882a593Smuzhiyun			144 145 146 147 148 149 150 151
448*4882a593Smuzhiyun			152 153 154 155 156 157 158 159
449*4882a593Smuzhiyun			160 161 162 163 164 165 166 167
450*4882a593Smuzhiyun			168 169 170 171 172 173 174 175
451*4882a593Smuzhiyun			176 177 178 179 180 181 182 183
452*4882a593Smuzhiyun			184 185 186 187 188 189 190 191
453*4882a593Smuzhiyun			192 193 194 195 196 197 198 199
454*4882a593Smuzhiyun			200 201 202 203 204 205 206 207
455*4882a593Smuzhiyun			208 209 210 211 212 213 214 215
456*4882a593Smuzhiyun			216 217 218 219 220 221 222 223
457*4882a593Smuzhiyun			224 225 226 227 228 229 230 231
458*4882a593Smuzhiyun			232 233 234 235 236 237 238 239
459*4882a593Smuzhiyun			240 241 242 243 244 245 246 247
460*4882a593Smuzhiyun			248 249 250 251 252 253 254 255
461*4882a593Smuzhiyun		>;
462*4882a593Smuzhiyun		default-brightness-level = <200>;
463*4882a593Smuzhiyun		is-forlinx;
464*4882a593Smuzhiyun	};
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun	lvds_backlight: lvds-backlight {
467*4882a593Smuzhiyun		compatible = "pwm-backlight";
468*4882a593Smuzhiyun		pwms = <&pwm14 0 20000 0>;
469*4882a593Smuzhiyun		brightness-levels = <
470*4882a593Smuzhiyun			  0  20  20  21  21  22  22  23
471*4882a593Smuzhiyun			 23  24  24  25  25  26  26  27
472*4882a593Smuzhiyun			 27  28  28  29  29  30  30  31
473*4882a593Smuzhiyun			 31  32  32  33  33  34  34  35
474*4882a593Smuzhiyun			 35  36  36  37  37  38  38  39
475*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
476*4882a593Smuzhiyun			 48  49  50  51  52  53  54  55
477*4882a593Smuzhiyun			 56  57  58  59  60  61  62  63
478*4882a593Smuzhiyun			 64  65  66  67  68  69  70  71
479*4882a593Smuzhiyun			 72  73  74  75  76  77  78  79
480*4882a593Smuzhiyun			 80  81  82  83  84  85  86  87
481*4882a593Smuzhiyun			 88  89  90  91  92  93  94  95
482*4882a593Smuzhiyun			 96  97  98  99 100 101 102 103
483*4882a593Smuzhiyun			104 105 106 107 108 109 110 111
484*4882a593Smuzhiyun			112 113 114 115 116 117 118 119
485*4882a593Smuzhiyun			120 121 122 123 124 125 126 127
486*4882a593Smuzhiyun			128 129 130 131 132 133 134 135
487*4882a593Smuzhiyun			136 137 138 139 140 141 142 143
488*4882a593Smuzhiyun			144 145 146 147 148 149 150 151
489*4882a593Smuzhiyun			152 153 154 155 156 157 158 159
490*4882a593Smuzhiyun			160 161 162 163 164 165 166 167
491*4882a593Smuzhiyun			168 169 170 171 172 173 174 175
492*4882a593Smuzhiyun			176 177 178 179 180 181 182 183
493*4882a593Smuzhiyun			184 185 186 187 188 189 190 191
494*4882a593Smuzhiyun			192 193 194 195 196 197 198 199
495*4882a593Smuzhiyun			200 201 202 203 204 205 206 207
496*4882a593Smuzhiyun			208 209 210 211 212 213 214 215
497*4882a593Smuzhiyun			216 217 218 219 220 221 222 223
498*4882a593Smuzhiyun			224 225 226 227 228 229 230 231
499*4882a593Smuzhiyun			232 233 234 235 236 237 238 239
500*4882a593Smuzhiyun			240 241 242 243 244 245 246 247
501*4882a593Smuzhiyun			248 249 250 251 252 253 254 255
502*4882a593Smuzhiyun		>;
503*4882a593Smuzhiyun		default-brightness-level = <200>;
504*4882a593Smuzhiyun		is-forlinx;
505*4882a593Smuzhiyun	};
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun	edp_backlight: edp-backlight {
508*4882a593Smuzhiyun		compatible = "pwm-backlight";
509*4882a593Smuzhiyun		pwms = <&pwm3 0 20000 0>;
510*4882a593Smuzhiyun		brightness-levels = <
511*4882a593Smuzhiyun			  0  20  20  21  21  22  22  23
512*4882a593Smuzhiyun			 23  24  24  25  25  26  26  27
513*4882a593Smuzhiyun			 27  28  28  29  29  30  30  31
514*4882a593Smuzhiyun			 31  32  32  33  33  34  34  35
515*4882a593Smuzhiyun			 35  36  36  37  37  38  38  39
516*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
517*4882a593Smuzhiyun			 48  49  50  51  52  53  54  55
518*4882a593Smuzhiyun			 56  57  58  59  60  61  62  63
519*4882a593Smuzhiyun			 64  65  66  67  68  69  70  71
520*4882a593Smuzhiyun			 72  73  74  75  76  77  78  79
521*4882a593Smuzhiyun			 80  81  82  83  84  85  86  87
522*4882a593Smuzhiyun			 88  89  90  91  92  93  94  95
523*4882a593Smuzhiyun			 96  97  98  99 100 101 102 103
524*4882a593Smuzhiyun			104 105 106 107 108 109 110 111
525*4882a593Smuzhiyun			112 113 114 115 116 117 118 119
526*4882a593Smuzhiyun			120 121 122 123 124 125 126 127
527*4882a593Smuzhiyun			128 129 130 131 132 133 134 135
528*4882a593Smuzhiyun			136 137 138 139 140 141 142 143
529*4882a593Smuzhiyun			144 145 146 147 148 149 150 151
530*4882a593Smuzhiyun			152 153 154 155 156 157 158 159
531*4882a593Smuzhiyun			160 161 162 163 164 165 166 167
532*4882a593Smuzhiyun			168 169 170 171 172 173 174 175
533*4882a593Smuzhiyun			176 177 178 179 180 181 182 183
534*4882a593Smuzhiyun			184 185 186 187 188 189 190 191
535*4882a593Smuzhiyun			192 193 194 195 196 197 198 199
536*4882a593Smuzhiyun			200 201 202 203 204 205 206 207
537*4882a593Smuzhiyun			208 209 210 211 212 213 214 215
538*4882a593Smuzhiyun			216 217 218 219 220 221 222 223
539*4882a593Smuzhiyun			224 225 226 227 228 229 230 231
540*4882a593Smuzhiyun			232 233 234 235 236 237 238 239
541*4882a593Smuzhiyun			240 241 242 243 244 245 246 247
542*4882a593Smuzhiyun			248 249 250 251 252 253 254 255
543*4882a593Smuzhiyun		>;
544*4882a593Smuzhiyun		default-brightness-level = <200>;
545*4882a593Smuzhiyun	};
546*4882a593Smuzhiyun};
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun&reserved_memory {
549*4882a593Smuzhiyun	ramoops: ramoops@110000 {
550*4882a593Smuzhiyun		compatible = "ramoops";
551*4882a593Smuzhiyun		reg = <0x0 0x110000 0x0 0xf0000>;
552*4882a593Smuzhiyun		record-size = <0x20000>;
553*4882a593Smuzhiyun		console-size = <0x80000>;
554*4882a593Smuzhiyun		ftrace-size = <0x00000>;
555*4882a593Smuzhiyun		pmsg-size = <0x50000>;
556*4882a593Smuzhiyun	};
557*4882a593Smuzhiyun};
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun&rng {
560*4882a593Smuzhiyun	status = "okay";
561*4882a593Smuzhiyun};
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun&rockchip_suspend {
564*4882a593Smuzhiyun	status = "okay";
565*4882a593Smuzhiyun};
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun&combphy0_us {
568*4882a593Smuzhiyun	status = "okay";
569*4882a593Smuzhiyun};
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun&combphy1_usq {
572*4882a593Smuzhiyun	status = "okay";
573*4882a593Smuzhiyun};
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun&combphy2_psq {
576*4882a593Smuzhiyun	status = "okay";
577*4882a593Smuzhiyun};
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun&csi2_dphy_hw {
580*4882a593Smuzhiyun	status = "okay";
581*4882a593Smuzhiyun};
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun&csi2_dphy0 {
584*4882a593Smuzhiyun	status = "okay";
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun	ports {
587*4882a593Smuzhiyun		#address-cells = <1>;
588*4882a593Smuzhiyun		#size-cells = <0>;
589*4882a593Smuzhiyun		port@0 {
590*4882a593Smuzhiyun			reg = <0>;
591*4882a593Smuzhiyun			#address-cells = <1>;
592*4882a593Smuzhiyun			#size-cells = <0>;
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun			mipi_in_ov13850: endpoint@1 {
595*4882a593Smuzhiyun				reg = <1>;
596*4882a593Smuzhiyun				remote-endpoint = <&ov13850_out>;
597*4882a593Smuzhiyun				data-lanes = <1 2>;
598*4882a593Smuzhiyun			};
599*4882a593Smuzhiyun		};
600*4882a593Smuzhiyun		port@1 {
601*4882a593Smuzhiyun			reg = <1>;
602*4882a593Smuzhiyun			#address-cells = <1>;
603*4882a593Smuzhiyun			#size-cells = <0>;
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun			csidphy_out: endpoint@0 {
606*4882a593Smuzhiyun				reg = <0>;
607*4882a593Smuzhiyun				remote-endpoint = <&isp0_in>;
608*4882a593Smuzhiyun			};
609*4882a593Smuzhiyun		};
610*4882a593Smuzhiyun	};
611*4882a593Smuzhiyun};
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun&gmac0 {
614*4882a593Smuzhiyun	phy-mode = "rgmii-rxid";
615*4882a593Smuzhiyun	clock_in_out = "output";
616*4882a593Smuzhiyun
617*4882a593Smuzhiyun	snps,reset-gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
618*4882a593Smuzhiyun	snps,reset-active-low;
619*4882a593Smuzhiyun	/* Reset time is 20ms, 100ms for rtl8211f */
620*4882a593Smuzhiyun	snps,reset-delays-us = <0 20000 100000>;
621*4882a593Smuzhiyun
622*4882a593Smuzhiyun	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>, <&cru CLK_MAC0_OUT>;
623*4882a593Smuzhiyun	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
624*4882a593Smuzhiyun	assigned-clock-rates = <0>, <125000000>, <25000000>;
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun	pinctrl-names = "default";
627*4882a593Smuzhiyun	pinctrl-0 = <&gmac0_miim
628*4882a593Smuzhiyun		     &gmac0_tx_bus2
629*4882a593Smuzhiyun		     &gmac0_rx_bus2
630*4882a593Smuzhiyun		     &gmac0_rgmii_clk
631*4882a593Smuzhiyun		     &gmac0_rgmii_bus
632*4882a593Smuzhiyun			 &eth0_pins>;
633*4882a593Smuzhiyun
634*4882a593Smuzhiyun	tx_delay = <0x36>;
635*4882a593Smuzhiyun/*	rx_delay = <0x00>;  */
636*4882a593Smuzhiyun
637*4882a593Smuzhiyun	phy-handle = <&rgmii_phy0>;
638*4882a593Smuzhiyun	status = "okay";
639*4882a593Smuzhiyun};
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun&gmac1 {
642*4882a593Smuzhiyun	phy-mode = "rgmii-rxid";
643*4882a593Smuzhiyun	clock_in_out = "output";
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun	snps,reset-gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
646*4882a593Smuzhiyun	snps,reset-active-low;
647*4882a593Smuzhiyun	/* Reset time is 20ms, 100ms for rtl8211f */
648*4882a593Smuzhiyun	snps,reset-delays-us = <0 20000 100000>;
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>, <&cru CLK_MAC1_OUT>;
651*4882a593Smuzhiyun	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
652*4882a593Smuzhiyun	assigned-clock-rates = <0>, <125000000>, <25000000>;
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun	pinctrl-names = "default";
655*4882a593Smuzhiyun	pinctrl-0 = <&gmac1m1_miim
656*4882a593Smuzhiyun		     &gmac1m1_tx_bus2
657*4882a593Smuzhiyun		     &gmac1m1_rx_bus2
658*4882a593Smuzhiyun		     &gmac1m1_rgmii_clk
659*4882a593Smuzhiyun		     &gmac1m1_rgmii_bus
660*4882a593Smuzhiyun			 &eth1m1_pins>;
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun	tx_delay = <0x47>;
663*4882a593Smuzhiyun/*	rx_delay = <0x00>; */
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun	phy-handle = <&rgmii_phy1>;
666*4882a593Smuzhiyun	status = "okay";
667*4882a593Smuzhiyun};
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun&mdio0 {
670*4882a593Smuzhiyun	rgmii_phy0: phy@0 {
671*4882a593Smuzhiyun		compatible = "ethernet-phy-ieee802.3-c22";
672*4882a593Smuzhiyun		reg = <0x0>;
673*4882a593Smuzhiyun		clocks = <&cru CLK_MAC0_OUT>;
674*4882a593Smuzhiyun	};
675*4882a593Smuzhiyun};
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun&mdio1 {
678*4882a593Smuzhiyun	rgmii_phy1: phy@0 {
679*4882a593Smuzhiyun		compatible = "ethernet-phy-ieee802.3-c22";
680*4882a593Smuzhiyun		reg = <0x0>;
681*4882a593Smuzhiyun		clocks = <&cru CLK_MAC1_OUT>;
682*4882a593Smuzhiyun	};
683*4882a593Smuzhiyun};
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun&video_phy0 {
686*4882a593Smuzhiyun	status = "okay";
687*4882a593Smuzhiyun};
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun&video_phy1 {
690*4882a593Smuzhiyun	status = "okay";
691*4882a593Smuzhiyun};
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun&pcie30phy {
694*4882a593Smuzhiyun	status = "okay";
695*4882a593Smuzhiyun};
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun&pcie3x2 {
698*4882a593Smuzhiyun	reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
699*4882a593Smuzhiyun/*	enable-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; */
700*4882a593Smuzhiyun	vpcie3v3-supply = <&vcc3v3_pcie>;
701*4882a593Smuzhiyun	status = "okay";
702*4882a593Smuzhiyun};
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun&pcie2x1 {
705*4882a593Smuzhiyun	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
706*4882a593Smuzhiyun	status = "okay";
707*4882a593Smuzhiyun};
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun&pinctrl {
710*4882a593Smuzhiyun 	touch {
711*4882a593Smuzhiyun 		touch_gpio: touch-gpio {
712*4882a593Smuzhiyun 			rockchip,pins =
713*4882a593Smuzhiyun				<1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
714*4882a593Smuzhiyun				<1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
715*4882a593Smuzhiyun		};
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun		rgb_touch_gpio: rgb-touch-gpio {
718*4882a593Smuzhiyun			rockchip,pins =
719*4882a593Smuzhiyun				<4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>,
720*4882a593Smuzhiyun				<4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
721*4882a593Smuzhiyun		};
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun		ft5x06_int: ft5x06-int {
724*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
725*4882a593Smuzhiyun							<0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
726*4882a593Smuzhiyun 		};
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun		dsi_gt911_int: dsi-gt911-int {
729*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
730*4882a593Smuzhiyun							<0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
731*4882a593Smuzhiyun 		};
732*4882a593Smuzhiyun 	};
733*4882a593Smuzhiyun
734*4882a593Smuzhiyun	cam {
735*4882a593Smuzhiyun		camera_pwr: camera-pwr {
736*4882a593Smuzhiyun			rockchip,pins =
737*4882a593Smuzhiyun				/* camera power en */
738*4882a593Smuzhiyun				<0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
739*4882a593Smuzhiyun		};
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun		ov13850_default_pin: ov13850-default-pin {
742*4882a593Smuzhiyun			rockchip,pins =
743*4882a593Smuzhiyun				<4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>,
744*4882a593Smuzhiyun				<0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
745*4882a593Smuzhiyun		};
746*4882a593Smuzhiyun		ov13850_sleep_pin: ov13850-sleep-pin {
747*4882a593Smuzhiyun			rockchip,pins =
748*4882a593Smuzhiyun				<4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>,
749*4882a593Smuzhiyun				<0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
750*4882a593Smuzhiyun		};
751*4882a593Smuzhiyun	};
752*4882a593Smuzhiyun	headphone {
753*4882a593Smuzhiyun		hp_det: hp-det {
754*4882a593Smuzhiyun			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
755*4882a593Smuzhiyun		};
756*4882a593Smuzhiyun	};
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun	pmic {
759*4882a593Smuzhiyun		pmic_int: pmic_int {
760*4882a593Smuzhiyun			rockchip,pins =
761*4882a593Smuzhiyun				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
762*4882a593Smuzhiyun		};
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun		soc_slppin_gpio: soc_slppin_gpio {
765*4882a593Smuzhiyun			rockchip,pins =
766*4882a593Smuzhiyun				<0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>;
767*4882a593Smuzhiyun		};
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun		soc_slppin_slp: soc_slppin_slp {
770*4882a593Smuzhiyun			rockchip,pins =
771*4882a593Smuzhiyun				<0 RK_PA2 1 &pcfg_pull_up>;
772*4882a593Smuzhiyun		};
773*4882a593Smuzhiyun
774*4882a593Smuzhiyun		soc_slppin_rst: soc_slppin_rst {
775*4882a593Smuzhiyun			rockchip,pins =
776*4882a593Smuzhiyun				<0 RK_PA2 2 &pcfg_pull_none>;
777*4882a593Smuzhiyun		};
778*4882a593Smuzhiyun	};
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun	sdio-pwrseq {
781*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
782*4882a593Smuzhiyun			rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
783*4882a593Smuzhiyun		};
784*4882a593Smuzhiyun	};
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun	5g {
787*4882a593Smuzhiyun		net_5g_rst_gpio: net_5g_rst_gpio {
788*4882a593Smuzhiyun			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
789*4882a593Smuzhiyun		};
790*4882a593Smuzhiyun
791*4882a593Smuzhiyun		net_5g_pwr_gpio: net_5g_pwr_gpio {
792*4882a593Smuzhiyun			rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
793*4882a593Smuzhiyun		};
794*4882a593Smuzhiyun	};
795*4882a593Smuzhiyun};
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun&rkisp {
798*4882a593Smuzhiyun	status = "okay";
799*4882a593Smuzhiyun};
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun&rkisp_mmu {
802*4882a593Smuzhiyun	status = "okay";
803*4882a593Smuzhiyun};
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun&rkisp_vir0 {
806*4882a593Smuzhiyun	status = "okay";
807*4882a593Smuzhiyun
808*4882a593Smuzhiyun	port {
809*4882a593Smuzhiyun		#address-cells = <1>;
810*4882a593Smuzhiyun		#size-cells = <0>;
811*4882a593Smuzhiyun
812*4882a593Smuzhiyun		isp0_in: endpoint@0 {
813*4882a593Smuzhiyun			reg = <0>;
814*4882a593Smuzhiyun			remote-endpoint = <&csidphy_out>;
815*4882a593Smuzhiyun		};
816*4882a593Smuzhiyun	};
817*4882a593Smuzhiyun};
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun&sdmmc2 {
820*4882a593Smuzhiyun	max-frequency = <150000000>;
821*4882a593Smuzhiyun	supports-sdio;
822*4882a593Smuzhiyun	bus-width = <4>;
823*4882a593Smuzhiyun	disable-wp;
824*4882a593Smuzhiyun	cap-sd-highspeed;
825*4882a593Smuzhiyun	cap-sdio-irq;
826*4882a593Smuzhiyun	keep-power-in-suspend;
827*4882a593Smuzhiyun	mmc-pwrseq = <&sdio_pwrseq>;
828*4882a593Smuzhiyun	non-removable;
829*4882a593Smuzhiyun	pinctrl-names = "default";
830*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
831*4882a593Smuzhiyun	sd-uhs-sdr104;
832*4882a593Smuzhiyun	status = "okay";
833*4882a593Smuzhiyun};
834*4882a593Smuzhiyun
835*4882a593Smuzhiyun&uart8 {
836*4882a593Smuzhiyun	status = "okay";
837*4882a593Smuzhiyun	pinctrl-names = "default";
838*4882a593Smuzhiyun	pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>;
839*4882a593Smuzhiyun};
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun&bus_npu {
842*4882a593Smuzhiyun	bus-supply = <&vdd_logic>;
843*4882a593Smuzhiyun	pvtm-supply = <&vdd_cpu>;
844*4882a593Smuzhiyun	status = "okay";
845*4882a593Smuzhiyun};
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun&can0 {
848*4882a593Smuzhiyun	assigned-clocks = <&cru CLK_CAN0>;
849*4882a593Smuzhiyun	assigned-clock-rates = <200000000>;
850*4882a593Smuzhiyun	pinctrl-names = "default";
851*4882a593Smuzhiyun	pinctrl-0 = <&can0m0_pins>;
852*4882a593Smuzhiyun	status = "okay";
853*4882a593Smuzhiyun};
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun&can1 {
856*4882a593Smuzhiyun	assigned-clocks = <&cru CLK_CAN1>;
857*4882a593Smuzhiyun	assigned-clock-rates = <200000000>;
858*4882a593Smuzhiyun	pinctrl-names = "default";
859*4882a593Smuzhiyun	pinctrl-0 = <&can1m1_pins>;
860*4882a593Smuzhiyun	status = "okay";
861*4882a593Smuzhiyun};
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun&can2 {
864*4882a593Smuzhiyun	assigned-clocks = <&cru CLK_CAN2>;
865*4882a593Smuzhiyun	assigned-clock-rates = <150000000>;
866*4882a593Smuzhiyun	pinctrl-names = "default";
867*4882a593Smuzhiyun	pinctrl-0 = <&can2m1_pins>;
868*4882a593Smuzhiyun	status = "disabled";
869*4882a593Smuzhiyun};
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun&cpu0 {
872*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
873*4882a593Smuzhiyun};
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun&dfi {
876*4882a593Smuzhiyun	status = "okay";
877*4882a593Smuzhiyun};
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun&dmc {
880*4882a593Smuzhiyun	center-supply = <&vdd_logic>;
881*4882a593Smuzhiyun	status = "okay";
882*4882a593Smuzhiyun};
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun&gpu {
885*4882a593Smuzhiyun	mali-supply = <&vdd_gpu>;
886*4882a593Smuzhiyun	status = "okay";
887*4882a593Smuzhiyun};
888*4882a593Smuzhiyun
889*4882a593Smuzhiyun&i2c0 {
890*4882a593Smuzhiyun	status = "okay";
891*4882a593Smuzhiyun
892*4882a593Smuzhiyun	vdd_cpu: tcs4525@1c {
893*4882a593Smuzhiyun		compatible = "tcs,tcs452x";
894*4882a593Smuzhiyun		status = "okay";
895*4882a593Smuzhiyun		reg = <0x1c>;
896*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
897*4882a593Smuzhiyun		regulator-compatible = "fan53555-reg";
898*4882a593Smuzhiyun		regulator-name = "vdd_cpu";
899*4882a593Smuzhiyun		regulator-min-microvolt = <712500>;
900*4882a593Smuzhiyun		regulator-max-microvolt = <1390000>;
901*4882a593Smuzhiyun		regulator-init-microvolt = <900000>;
902*4882a593Smuzhiyun		regulator-ramp-delay = <2300>;
903*4882a593Smuzhiyun		fcs,suspend-voltage-selector = <1>;
904*4882a593Smuzhiyun		regulator-boot-on;
905*4882a593Smuzhiyun		regulator-always-on;
906*4882a593Smuzhiyun		regulator-state-mem {
907*4882a593Smuzhiyun			regulator-off-in-suspend;
908*4882a593Smuzhiyun		};
909*4882a593Smuzhiyun	};
910*4882a593Smuzhiyun
911*4882a593Smuzhiyun	rk809: pmic@20 {
912*4882a593Smuzhiyun		compatible = "rockchip,rk809";
913*4882a593Smuzhiyun		reg = <0x20>;
914*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
915*4882a593Smuzhiyun		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
916*4882a593Smuzhiyun
917*4882a593Smuzhiyun		pinctrl-names = "default", "pmic-sleep",
918*4882a593Smuzhiyun				"pmic-power-off", "pmic-reset";
919*4882a593Smuzhiyun		pinctrl-0 = <&pmic_int>;
920*4882a593Smuzhiyun		pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
921*4882a593Smuzhiyun		pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
922*4882a593Smuzhiyun		pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
923*4882a593Smuzhiyun
924*4882a593Smuzhiyun		rockchip,system-power-controller;
925*4882a593Smuzhiyun		wakeup-source;
926*4882a593Smuzhiyun		#clock-cells = <1>;
927*4882a593Smuzhiyun		clock-output-names = "rk808-clkout1", "rk808-clkout2";
928*4882a593Smuzhiyun		//fb-inner-reg-idxs = <2>;
929*4882a593Smuzhiyun		/* 1: rst regs (default in codes), 0: rst the pmic */
930*4882a593Smuzhiyun		pmic-reset-func = <0>;
931*4882a593Smuzhiyun		/* not save the PMIC_POWER_EN register in uboot */
932*4882a593Smuzhiyun		not-save-power-en = <1>;
933*4882a593Smuzhiyun
934*4882a593Smuzhiyun		vcc1-supply = <&vcc3v3_sys>;
935*4882a593Smuzhiyun		vcc2-supply = <&vcc3v3_sys>;
936*4882a593Smuzhiyun		vcc3-supply = <&vcc3v3_sys>;
937*4882a593Smuzhiyun		vcc4-supply = <&vcc3v3_sys>;
938*4882a593Smuzhiyun		vcc5-supply = <&vcc3v3_sys>;
939*4882a593Smuzhiyun		vcc6-supply = <&vcc3v3_sys>;
940*4882a593Smuzhiyun		vcc7-supply = <&vcc3v3_sys>;
941*4882a593Smuzhiyun		vcc8-supply = <&vcc3v3_sys>;
942*4882a593Smuzhiyun		vcc9-supply = <&vcc3v3_sys>;
943*4882a593Smuzhiyun
944*4882a593Smuzhiyun		pwrkey {
945*4882a593Smuzhiyun			status = "okay";
946*4882a593Smuzhiyun		};
947*4882a593Smuzhiyun
948*4882a593Smuzhiyun		pinctrl_rk8xx: pinctrl_rk8xx {
949*4882a593Smuzhiyun			gpio-controller;
950*4882a593Smuzhiyun			#gpio-cells = <2>;
951*4882a593Smuzhiyun
952*4882a593Smuzhiyun			rk817_slppin_null: rk817_slppin_null {
953*4882a593Smuzhiyun				pins = "gpio_slp";
954*4882a593Smuzhiyun				function = "pin_fun0";
955*4882a593Smuzhiyun			};
956*4882a593Smuzhiyun
957*4882a593Smuzhiyun			rk817_slppin_slp: rk817_slppin_slp {
958*4882a593Smuzhiyun				pins = "gpio_slp";
959*4882a593Smuzhiyun				function = "pin_fun1";
960*4882a593Smuzhiyun			};
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
963*4882a593Smuzhiyun				pins = "gpio_slp";
964*4882a593Smuzhiyun				function = "pin_fun2";
965*4882a593Smuzhiyun			};
966*4882a593Smuzhiyun
967*4882a593Smuzhiyun			rk817_slppin_rst: rk817_slppin_rst {
968*4882a593Smuzhiyun				pins = "gpio_slp";
969*4882a593Smuzhiyun				function = "pin_fun3";
970*4882a593Smuzhiyun			};
971*4882a593Smuzhiyun		};
972*4882a593Smuzhiyun
973*4882a593Smuzhiyun		regulators {
974*4882a593Smuzhiyun			vdd_logic: DCDC_REG1 {
975*4882a593Smuzhiyun				regulator-always-on;
976*4882a593Smuzhiyun				regulator-boot-on;
977*4882a593Smuzhiyun				regulator-min-microvolt = <500000>;
978*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
979*4882a593Smuzhiyun				regulator-init-microvolt = <900000>;
980*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
981*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
982*4882a593Smuzhiyun				regulator-name = "vdd_logic";
983*4882a593Smuzhiyun				regulator-state-mem {
984*4882a593Smuzhiyun					regulator-off-in-suspend;
985*4882a593Smuzhiyun				};
986*4882a593Smuzhiyun			};
987*4882a593Smuzhiyun
988*4882a593Smuzhiyun			vdd_gpu: DCDC_REG2 {
989*4882a593Smuzhiyun				regulator-always-on;
990*4882a593Smuzhiyun				regulator-boot-on;
991*4882a593Smuzhiyun				regulator-min-microvolt = <500000>;
992*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
993*4882a593Smuzhiyun				regulator-init-microvolt = <900000>;
994*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
995*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
996*4882a593Smuzhiyun				regulator-name = "vdd_gpu";
997*4882a593Smuzhiyun				regulator-state-mem {
998*4882a593Smuzhiyun					regulator-off-in-suspend;
999*4882a593Smuzhiyun				};
1000*4882a593Smuzhiyun			};
1001*4882a593Smuzhiyun
1002*4882a593Smuzhiyun			vcc_ddr: DCDC_REG3 {
1003*4882a593Smuzhiyun				regulator-always-on;
1004*4882a593Smuzhiyun				regulator-boot-on;
1005*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
1006*4882a593Smuzhiyun				regulator-name = "vcc_ddr";
1007*4882a593Smuzhiyun				regulator-state-mem {
1008*4882a593Smuzhiyun					regulator-on-in-suspend;
1009*4882a593Smuzhiyun				};
1010*4882a593Smuzhiyun			};
1011*4882a593Smuzhiyun
1012*4882a593Smuzhiyun			vdd_npu: DCDC_REG4 {
1013*4882a593Smuzhiyun				regulator-always-on;
1014*4882a593Smuzhiyun				regulator-boot-on;
1015*4882a593Smuzhiyun				regulator-min-microvolt = <500000>;
1016*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
1017*4882a593Smuzhiyun				regulator-init-microvolt = <900000>;
1018*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
1019*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
1020*4882a593Smuzhiyun				regulator-name = "vdd_npu";
1021*4882a593Smuzhiyun				regulator-state-mem {
1022*4882a593Smuzhiyun					regulator-off-in-suspend;
1023*4882a593Smuzhiyun				};
1024*4882a593Smuzhiyun			};
1025*4882a593Smuzhiyun
1026*4882a593Smuzhiyun			vdda0v9_image: LDO_REG1 {
1027*4882a593Smuzhiyun				regulator-boot-on;
1028*4882a593Smuzhiyun				regulator-always-on;
1029*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
1030*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
1031*4882a593Smuzhiyun				regulator-name = "vdda0v9_image";
1032*4882a593Smuzhiyun				regulator-state-mem {
1033*4882a593Smuzhiyun					regulator-off-in-suspend;
1034*4882a593Smuzhiyun				};
1035*4882a593Smuzhiyun			};
1036*4882a593Smuzhiyun
1037*4882a593Smuzhiyun			vdda_0v9: LDO_REG2 {
1038*4882a593Smuzhiyun				regulator-always-on;
1039*4882a593Smuzhiyun				regulator-boot-on;
1040*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
1041*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
1042*4882a593Smuzhiyun				regulator-name = "vdda_0v9";
1043*4882a593Smuzhiyun				regulator-state-mem {
1044*4882a593Smuzhiyun					regulator-off-in-suspend;
1045*4882a593Smuzhiyun				};
1046*4882a593Smuzhiyun			};
1047*4882a593Smuzhiyun
1048*4882a593Smuzhiyun			vdda0v9_pmu: LDO_REG3 {
1049*4882a593Smuzhiyun				regulator-always-on;
1050*4882a593Smuzhiyun				regulator-boot-on;
1051*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
1052*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
1053*4882a593Smuzhiyun				regulator-name = "vdda0v9_pmu";
1054*4882a593Smuzhiyun				regulator-state-mem {
1055*4882a593Smuzhiyun					regulator-on-in-suspend;
1056*4882a593Smuzhiyun					regulator-suspend-microvolt = <900000>;
1057*4882a593Smuzhiyun				};
1058*4882a593Smuzhiyun			};
1059*4882a593Smuzhiyun
1060*4882a593Smuzhiyun			vccio_acodec: LDO_REG4 {
1061*4882a593Smuzhiyun				regulator-always-on;
1062*4882a593Smuzhiyun				regulator-boot-on;
1063*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
1064*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
1065*4882a593Smuzhiyun				regulator-name = "vccio_acodec";
1066*4882a593Smuzhiyun				regulator-state-mem {
1067*4882a593Smuzhiyun					regulator-off-in-suspend;
1068*4882a593Smuzhiyun				};
1069*4882a593Smuzhiyun			};
1070*4882a593Smuzhiyun
1071*4882a593Smuzhiyun			vccio_sd: LDO_REG5 {
1072*4882a593Smuzhiyun				regulator-always-on;
1073*4882a593Smuzhiyun				regulator-boot-on;
1074*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
1075*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
1076*4882a593Smuzhiyun				regulator-name = "vccio_sd";
1077*4882a593Smuzhiyun				regulator-state-mem {
1078*4882a593Smuzhiyun					regulator-off-in-suspend;
1079*4882a593Smuzhiyun				};
1080*4882a593Smuzhiyun			};
1081*4882a593Smuzhiyun
1082*4882a593Smuzhiyun			vcc3v3_pmu: LDO_REG6 {
1083*4882a593Smuzhiyun				regulator-always-on;
1084*4882a593Smuzhiyun				regulator-boot-on;
1085*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
1086*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
1087*4882a593Smuzhiyun				regulator-name = "vcc3v3_pmu";
1088*4882a593Smuzhiyun				regulator-state-mem {
1089*4882a593Smuzhiyun					regulator-on-in-suspend;
1090*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
1091*4882a593Smuzhiyun				};
1092*4882a593Smuzhiyun			};
1093*4882a593Smuzhiyun
1094*4882a593Smuzhiyun			vcca_1v8: LDO_REG7 {
1095*4882a593Smuzhiyun				regulator-always-on;
1096*4882a593Smuzhiyun				regulator-boot-on;
1097*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
1098*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
1099*4882a593Smuzhiyun				regulator-name = "vcca_1v8";
1100*4882a593Smuzhiyun				regulator-state-mem {
1101*4882a593Smuzhiyun					regulator-off-in-suspend;
1102*4882a593Smuzhiyun				};
1103*4882a593Smuzhiyun			};
1104*4882a593Smuzhiyun
1105*4882a593Smuzhiyun			vcca1v8_pmu: LDO_REG8 {
1106*4882a593Smuzhiyun				regulator-always-on;
1107*4882a593Smuzhiyun				regulator-boot-on;
1108*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
1109*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
1110*4882a593Smuzhiyun				regulator-name = "vcca1v8_pmu";
1111*4882a593Smuzhiyun				regulator-state-mem {
1112*4882a593Smuzhiyun					regulator-on-in-suspend;
1113*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
1114*4882a593Smuzhiyun				};
1115*4882a593Smuzhiyun			};
1116*4882a593Smuzhiyun
1117*4882a593Smuzhiyun			vcca1v8_image: LDO_REG9 {
1118*4882a593Smuzhiyun				regulator-always-on;
1119*4882a593Smuzhiyun				regulator-boot-on;
1120*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
1121*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
1122*4882a593Smuzhiyun				regulator-name = "vcca1v8_image";
1123*4882a593Smuzhiyun				regulator-state-mem {
1124*4882a593Smuzhiyun					regulator-off-in-suspend;
1125*4882a593Smuzhiyun				};
1126*4882a593Smuzhiyun			};
1127*4882a593Smuzhiyun
1128*4882a593Smuzhiyun			vcc_1v8: DCDC_REG5 {
1129*4882a593Smuzhiyun				regulator-always-on;
1130*4882a593Smuzhiyun				regulator-boot-on;
1131*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
1132*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
1133*4882a593Smuzhiyun				regulator-name = "vcc_1v8";
1134*4882a593Smuzhiyun				regulator-state-mem {
1135*4882a593Smuzhiyun					regulator-off-in-suspend;
1136*4882a593Smuzhiyun				};
1137*4882a593Smuzhiyun			};
1138*4882a593Smuzhiyun
1139*4882a593Smuzhiyun			vcc_3v3: SWITCH_REG1 {
1140*4882a593Smuzhiyun				regulator-always-on;
1141*4882a593Smuzhiyun				regulator-boot-on;
1142*4882a593Smuzhiyun				regulator-name = "vcc_3v3";
1143*4882a593Smuzhiyun				regulator-state-mem {
1144*4882a593Smuzhiyun					regulator-off-in-suspend;
1145*4882a593Smuzhiyun				};
1146*4882a593Smuzhiyun			};
1147*4882a593Smuzhiyun
1148*4882a593Smuzhiyun			vcc3v3_sd: SWITCH_REG2 {
1149*4882a593Smuzhiyun				regulator-always-on;
1150*4882a593Smuzhiyun				regulator-boot-on;
1151*4882a593Smuzhiyun				regulator-name = "vcc3v3_sd";
1152*4882a593Smuzhiyun				regulator-state-mem {
1153*4882a593Smuzhiyun					regulator-off-in-suspend;
1154*4882a593Smuzhiyun				};
1155*4882a593Smuzhiyun			};
1156*4882a593Smuzhiyun		};
1157*4882a593Smuzhiyun
1158*4882a593Smuzhiyun		rk809_codec: codec {
1159*4882a593Smuzhiyun			#sound-dai-cells = <0>;
1160*4882a593Smuzhiyun			compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
1161*4882a593Smuzhiyun			clocks = <&cru I2S1_MCLKOUT>;
1162*4882a593Smuzhiyun			clock-names = "mclk";
1163*4882a593Smuzhiyun			assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>;
1164*4882a593Smuzhiyun			assigned-clock-rates = <12288000>;
1165*4882a593Smuzhiyun			assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>;
1166*4882a593Smuzhiyun			pinctrl-names = "default";
1167*4882a593Smuzhiyun			pinctrl-0 = <&i2s1m0_mclk>;
1168*4882a593Smuzhiyun			hp-volume = <20>;
1169*4882a593Smuzhiyun			spk-volume = <3>;
1170*4882a593Smuzhiyun			mic-in-differential;
1171*4882a593Smuzhiyun			status = "okay";
1172*4882a593Smuzhiyun		};
1173*4882a593Smuzhiyun	};
1174*4882a593Smuzhiyun};
1175*4882a593Smuzhiyun
1176*4882a593Smuzhiyun&i2c2 {
1177*4882a593Smuzhiyun	status = "okay";
1178*4882a593Smuzhiyun	pinctrl-names = "default";
1179*4882a593Smuzhiyun	pinctrl-0 = <&i2c2m1_xfer>;
1180*4882a593Smuzhiyun
1181*4882a593Smuzhiyun	vm149c_0: vm149c@0c {
1182*4882a593Smuzhiyun		compatible = "silicon touch,vm149c";
1183*4882a593Smuzhiyun		status = "okay";
1184*4882a593Smuzhiyun		reg = <0x0c>;
1185*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
1186*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
1187*4882a593Smuzhiyun	};
1188*4882a593Smuzhiyun
1189*4882a593Smuzhiyun	ov13850: ov13850@10 {
1190*4882a593Smuzhiyun		compatible = "ovti,ov13850";
1191*4882a593Smuzhiyun		status = "okay";
1192*4882a593Smuzhiyun		reg = <0x10>;
1193*4882a593Smuzhiyun		clocks = <&cru CLK_CIF_OUT>;
1194*4882a593Smuzhiyun		clock-names = "xvclk";
1195*4882a593Smuzhiyun		power-domains = <&power RK3568_PD_VI>;
1196*4882a593Smuzhiyun		pinctrl-names = "default";
1197*4882a593Smuzhiyun		pinctrl-0 = <&cif_clk>, <&ov13850_default_pin>;
1198*4882a593Smuzhiyun		pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
1199*4882a593Smuzhiyun		reset-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
1200*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
1201*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
1202*4882a593Smuzhiyun		rockchip,camera-module-name = "ov13850-csi";
1203*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "ov13850-2mp";
1204*4882a593Smuzhiyun		lens-focus = <&vm149c_0>;
1205*4882a593Smuzhiyun
1206*4882a593Smuzhiyun		port {
1207*4882a593Smuzhiyun			ov13850_out: endpoint {
1208*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ov13850>;
1209*4882a593Smuzhiyun				data-lanes = <1 2>;
1210*4882a593Smuzhiyun			};
1211*4882a593Smuzhiyun		};
1212*4882a593Smuzhiyun	};
1213*4882a593Smuzhiyun
1214*4882a593Smuzhiyun	gt9xx_lvds: gt9xx@5d {
1215*4882a593Smuzhiyun		compatible = "goodix,gt928";
1216*4882a593Smuzhiyun		reg = <0x5d>;
1217*4882a593Smuzhiyun		pinctrl-names = "default";
1218*4882a593Smuzhiyun		pinctrl-0 = <&touch_gpio>;
1219*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
1220*4882a593Smuzhiyun		interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>;
1221*4882a593Smuzhiyun		irq-gpio = <&gpio1 RK_PA4 IRQ_TYPE_LEVEL_LOW>;
1222*4882a593Smuzhiyun		reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
1223*4882a593Smuzhiyun		touchscreen-size-x = <1280>;
1224*4882a593Smuzhiyun		touchscreen-size-y = <800>;
1225*4882a593Smuzhiyun		touchscreen-swapped-x-y;
1226*4882a593Smuzhiyun		uniq = "lvds";
1227*4882a593Smuzhiyun		status = "okay";
1228*4882a593Smuzhiyun	};
1229*4882a593Smuzhiyun
1230*4882a593Smuzhiyun	gt9xx_rgb: gt9xx-rgb@5d {
1231*4882a593Smuzhiyun		compatible = "goodix,gt928";
1232*4882a593Smuzhiyun		reg = <0x5d>;
1233*4882a593Smuzhiyun		pinctrl-names = "default";
1234*4882a593Smuzhiyun		pinctrl-0 = <&rgb_touch_gpio>;
1235*4882a593Smuzhiyun		interrupt-parent = <&gpio4>;
1236*4882a593Smuzhiyun		interrupts = <RK_PC6 IRQ_TYPE_EDGE_FALLING>;
1237*4882a593Smuzhiyun		irq-gpio = <&gpio4 RK_PC6 IRQ_TYPE_LEVEL_LOW>;
1238*4882a593Smuzhiyun		reset-gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
1239*4882a593Smuzhiyun		touchscreen-size-x = <800>;
1240*4882a593Smuzhiyun		touchscreen-size-y = <480>;
1241*4882a593Smuzhiyun		touchscreen-inverted-x;
1242*4882a593Smuzhiyun		touchscreen-inverted-y;
1243*4882a593Smuzhiyun		uniq = "rgb";
1244*4882a593Smuzhiyun		status = "disabled";
1245*4882a593Smuzhiyun	};
1246*4882a593Smuzhiyun
1247*4882a593Smuzhiyun	gt9xx_dsi: gt9xx@14 {
1248*4882a593Smuzhiyun		compatible = "goodix,gt928";
1249*4882a593Smuzhiyun		reg = <0x14>;
1250*4882a593Smuzhiyun		pinctrl-names = "default";
1251*4882a593Smuzhiyun		pinctrl-0 = <&dsi_gt911_int>;
1252*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
1253*4882a593Smuzhiyun		interrupts = <RK_PA0 IRQ_TYPE_EDGE_FALLING>;
1254*4882a593Smuzhiyun		irq-gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
1255*4882a593Smuzhiyun		reset-gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
1256*4882a593Smuzhiyun		touchscreen-size-x = <1024>;
1257*4882a593Smuzhiyun		touchscreen-size-y = <600>;
1258*4882a593Smuzhiyun		uniq = "dsi";
1259*4882a593Smuzhiyun		status = "okay";
1260*4882a593Smuzhiyun	};
1261*4882a593Smuzhiyun
1262*4882a593Smuzhiyun	polytouch: edt-ft5x06@38{
1263*4882a593Smuzhiyun		compatible = "edt,edt-ft5406", "edt,edt-ft5x06";
1264*4882a593Smuzhiyun		reg = <0x38>;
1265*4882a593Smuzhiyun		pinctrl-names = "defaults";
1266*4882a593Smuzhiyun		pinctrl-0 = <&ft5x06_int>;
1267*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
1268*4882a593Smuzhiyun		interrupts = <RK_PA0 IRQ_TYPE_EDGE_FALLING>;
1269*4882a593Smuzhiyun		touchscreen-size-x = <1024>;
1270*4882a593Smuzhiyun		touchscreen-size-y = <600>;
1271*4882a593Smuzhiyun		status = "okay";
1272*4882a593Smuzhiyun	};
1273*4882a593Smuzhiyun};
1274*4882a593Smuzhiyun
1275*4882a593Smuzhiyun&i2c3 {
1276*4882a593Smuzhiyun	status = "okay";
1277*4882a593Smuzhiyun
1278*4882a593Smuzhiyun	rx8010: rx8010@32 {
1279*4882a593Smuzhiyun		compatible = "epson,rx8010";
1280*4882a593Smuzhiyun		reg = <0x32>;
1281*4882a593Smuzhiyun	};
1282*4882a593Smuzhiyun
1283*4882a593Smuzhiyun	pcf8563: pcf8563@51 {
1284*4882a593Smuzhiyun		compatible = "nxp,pcf8563";
1285*4882a593Smuzhiyun		reg = <0x51>;
1286*4882a593Smuzhiyun		#clock-cells = <0>;
1287*4882a593Smuzhiyun	};
1288*4882a593Smuzhiyun};
1289*4882a593Smuzhiyun
1290*4882a593Smuzhiyun&i2s0_8ch {
1291*4882a593Smuzhiyun	status = "okay";
1292*4882a593Smuzhiyun};
1293*4882a593Smuzhiyun
1294*4882a593Smuzhiyun&i2s1_8ch {
1295*4882a593Smuzhiyun	status = "okay";
1296*4882a593Smuzhiyun	rockchip,clk-trcm = <1>;
1297*4882a593Smuzhiyun	pinctrl-names = "default";
1298*4882a593Smuzhiyun	pinctrl-0 = <&i2s1m0_sclktx
1299*4882a593Smuzhiyun		     &i2s1m0_lrcktx
1300*4882a593Smuzhiyun		     &i2s1m0_sdi0
1301*4882a593Smuzhiyun		     &i2s1m0_sdo0>;
1302*4882a593Smuzhiyun};
1303*4882a593Smuzhiyun
1304*4882a593Smuzhiyun&iep {
1305*4882a593Smuzhiyun	status = "okay";
1306*4882a593Smuzhiyun};
1307*4882a593Smuzhiyun
1308*4882a593Smuzhiyun&iep_mmu {
1309*4882a593Smuzhiyun	status = "okay";
1310*4882a593Smuzhiyun};
1311*4882a593Smuzhiyun
1312*4882a593Smuzhiyun&jpegd {
1313*4882a593Smuzhiyun	status = "okay";
1314*4882a593Smuzhiyun};
1315*4882a593Smuzhiyun
1316*4882a593Smuzhiyun&jpegd_mmu {
1317*4882a593Smuzhiyun	status = "okay";
1318*4882a593Smuzhiyun};
1319*4882a593Smuzhiyun
1320*4882a593Smuzhiyun&mpp_srv {
1321*4882a593Smuzhiyun	status = "okay";
1322*4882a593Smuzhiyun};
1323*4882a593Smuzhiyun
1324*4882a593Smuzhiyun&nandc0 {
1325*4882a593Smuzhiyun	#address-cells = <1>;
1326*4882a593Smuzhiyun	#size-cells = <0>;
1327*4882a593Smuzhiyun	status = "okay";
1328*4882a593Smuzhiyun
1329*4882a593Smuzhiyun	nand@0 {
1330*4882a593Smuzhiyun		reg = <0>;
1331*4882a593Smuzhiyun		nand-bus-width = <8>;
1332*4882a593Smuzhiyun		nand-ecc-mode = "hw";
1333*4882a593Smuzhiyun		nand-ecc-strength = <16>;
1334*4882a593Smuzhiyun		nand-ecc-step-size = <1024>;
1335*4882a593Smuzhiyun	};
1336*4882a593Smuzhiyun};
1337*4882a593Smuzhiyun
1338*4882a593Smuzhiyun /*
1339*4882a593Smuzhiyun  * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7].
1340*4882a593Smuzhiyun  * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured;
1341*4882a593Smuzhiyun  * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages
1342*4882a593Smuzhiyun  *    must be consistent with the software configuration correspondingly
1343*4882a593Smuzhiyun  *	a/ When the hardware IO level is connected to 1.8V, the software voltage configuration
1344*4882a593Smuzhiyun  *	   should also be configured to 1.8V accordingly;
1345*4882a593Smuzhiyun  *	b/ When the hardware IO level is connected to 3.3V, the software voltage configuration
1346*4882a593Smuzhiyun  *	   should also be configured to 3.3V accordingly;
1347*4882a593Smuzhiyun  * 3/ VCCIO2 voltage control selection (0xFDC20140)
1348*4882a593Smuzhiyun  *	BIT[0]: 0x0: from GPIO_0A7 (default)
1349*4882a593Smuzhiyun  *	BIT[0]: 0x1: from GRF
1350*4882a593Smuzhiyun  *    Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7:
1351*4882a593Smuzhiyun  *	L:VCCIO2 must supply 3.3V
1352*4882a593Smuzhiyun  *	H:VCCIO2 must supply 1.8V
1353*4882a593Smuzhiyun  */
1354*4882a593Smuzhiyun&pmu_io_domains {
1355*4882a593Smuzhiyun	status = "okay";
1356*4882a593Smuzhiyun	pmuio1-supply = <&vcc3v3_pmu>;
1357*4882a593Smuzhiyun	pmuio2-supply = <&vcc3v3_pmu>;
1358*4882a593Smuzhiyun	vccio1-supply = <&vccio_acodec>;
1359*4882a593Smuzhiyun	vccio3-supply = <&vccio_sd>;
1360*4882a593Smuzhiyun	vccio4-supply = <&vcc_1v8>;
1361*4882a593Smuzhiyun	vccio5-supply = <&vcc_3v3>;
1362*4882a593Smuzhiyun	vccio6-supply = <&vcc_1v8>;
1363*4882a593Smuzhiyun	vccio7-supply = <&vcc_3v3>;
1364*4882a593Smuzhiyun};
1365*4882a593Smuzhiyun
1366*4882a593Smuzhiyun&pwm3 {
1367*4882a593Smuzhiyun	status = "okay";
1368*4882a593Smuzhiyun};
1369*4882a593Smuzhiyun
1370*4882a593Smuzhiyun&pwm5 {
1371*4882a593Smuzhiyun	status = "okay";
1372*4882a593Smuzhiyun};
1373*4882a593Smuzhiyun
1374*4882a593Smuzhiyun&pwm14 {
1375*4882a593Smuzhiyun	status = "okay";
1376*4882a593Smuzhiyun};
1377*4882a593Smuzhiyun
1378*4882a593Smuzhiyun&rk_rga {
1379*4882a593Smuzhiyun	status = "okay";
1380*4882a593Smuzhiyun};
1381*4882a593Smuzhiyun
1382*4882a593Smuzhiyun&rkvdec {
1383*4882a593Smuzhiyun	status = "okay";
1384*4882a593Smuzhiyun};
1385*4882a593Smuzhiyun
1386*4882a593Smuzhiyun&rkvdec_mmu {
1387*4882a593Smuzhiyun	status = "okay";
1388*4882a593Smuzhiyun};
1389*4882a593Smuzhiyun
1390*4882a593Smuzhiyun&rkvenc {
1391*4882a593Smuzhiyun	venc-supply = <&vdd_logic>;
1392*4882a593Smuzhiyun	status = "okay";
1393*4882a593Smuzhiyun};
1394*4882a593Smuzhiyun
1395*4882a593Smuzhiyun&rkvenc_mmu {
1396*4882a593Smuzhiyun	status = "okay";
1397*4882a593Smuzhiyun};
1398*4882a593Smuzhiyun
1399*4882a593Smuzhiyun&rknpu {
1400*4882a593Smuzhiyun	rknpu-supply = <&vdd_npu>;
1401*4882a593Smuzhiyun	status = "okay";
1402*4882a593Smuzhiyun};
1403*4882a593Smuzhiyun
1404*4882a593Smuzhiyun&rknpu_mmu {
1405*4882a593Smuzhiyun	status = "okay";
1406*4882a593Smuzhiyun};
1407*4882a593Smuzhiyun
1408*4882a593Smuzhiyun&saradc {
1409*4882a593Smuzhiyun	status = "okay";
1410*4882a593Smuzhiyun	vref-supply = <&vcca_1v8>;
1411*4882a593Smuzhiyun};
1412*4882a593Smuzhiyun
1413*4882a593Smuzhiyun&sdhci {
1414*4882a593Smuzhiyun	bus-width = <8>;
1415*4882a593Smuzhiyun	supports-emmc;
1416*4882a593Smuzhiyun	non-removable;
1417*4882a593Smuzhiyun	max-frequency = <200000000>;
1418*4882a593Smuzhiyun	status = "okay";
1419*4882a593Smuzhiyun};
1420*4882a593Smuzhiyun
1421*4882a593Smuzhiyun&sdmmc0 {
1422*4882a593Smuzhiyun	max-frequency = <150000000>;
1423*4882a593Smuzhiyun	supports-sd;
1424*4882a593Smuzhiyun	bus-width = <4>;
1425*4882a593Smuzhiyun	cap-mmc-highspeed;
1426*4882a593Smuzhiyun	cap-sd-highspeed;
1427*4882a593Smuzhiyun	disable-wp;
1428*4882a593Smuzhiyun	sd-uhs-sdr104;
1429*4882a593Smuzhiyun	vmmc-supply = <&vcc3v3_sd>;
1430*4882a593Smuzhiyun	vqmmc-supply = <&vccio_sd>;
1431*4882a593Smuzhiyun	pinctrl-names = "default";
1432*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
1433*4882a593Smuzhiyun	status = "okay";
1434*4882a593Smuzhiyun};
1435*4882a593Smuzhiyun
1436*4882a593Smuzhiyun&sfc {
1437*4882a593Smuzhiyun	status = "okay";
1438*4882a593Smuzhiyun	pinctrl-names = "default";
1439*4882a593Smuzhiyun	pinctrl-0 = <&fspi_pins>;
1440*4882a593Smuzhiyun	flash: m25p80@0 {
1441*4882a593Smuzhiyun		#address-cells = <1>;
1442*4882a593Smuzhiyun		#size-cells = <1>;
1443*4882a593Smuzhiyun		compatible = "spansion,m25p80", "jedec,spi-nor";
1444*4882a593Smuzhiyun		reg = <0>;
1445*4882a593Smuzhiyun		spi-max-frequency = <40000000>;
1446*4882a593Smuzhiyun		m25p,fast-read;
1447*4882a593Smuzhiyun	};
1448*4882a593Smuzhiyun};
1449*4882a593Smuzhiyun
1450*4882a593Smuzhiyun&spdif_8ch {
1451*4882a593Smuzhiyun	status = "disabled";
1452*4882a593Smuzhiyun	pinctrl-names = "default";
1453*4882a593Smuzhiyun	pinctrl-0 = <&spdifm1_tx>;
1454*4882a593Smuzhiyun};
1455*4882a593Smuzhiyun
1456*4882a593Smuzhiyun&tsadc {
1457*4882a593Smuzhiyun	status = "okay";
1458*4882a593Smuzhiyun};
1459*4882a593Smuzhiyun
1460*4882a593Smuzhiyun&u2phy0_host {
1461*4882a593Smuzhiyun	status = "okay";
1462*4882a593Smuzhiyun};
1463*4882a593Smuzhiyun
1464*4882a593Smuzhiyun&u2phy0_otg {
1465*4882a593Smuzhiyun	status = "okay";
1466*4882a593Smuzhiyun};
1467*4882a593Smuzhiyun
1468*4882a593Smuzhiyun&u2phy1_host {
1469*4882a593Smuzhiyun	status = "okay";
1470*4882a593Smuzhiyun};
1471*4882a593Smuzhiyun
1472*4882a593Smuzhiyun&u2phy1_otg {
1473*4882a593Smuzhiyun	status = "okay";
1474*4882a593Smuzhiyun};
1475*4882a593Smuzhiyun
1476*4882a593Smuzhiyun&usb2phy0 {
1477*4882a593Smuzhiyun	status = "okay";
1478*4882a593Smuzhiyun};
1479*4882a593Smuzhiyun
1480*4882a593Smuzhiyun&usb2phy1 {
1481*4882a593Smuzhiyun	status = "okay";
1482*4882a593Smuzhiyun};
1483*4882a593Smuzhiyun
1484*4882a593Smuzhiyun&usb_host0_ehci {
1485*4882a593Smuzhiyun	status = "okay";
1486*4882a593Smuzhiyun};
1487*4882a593Smuzhiyun
1488*4882a593Smuzhiyun&usb_host0_ohci {
1489*4882a593Smuzhiyun	status = "okay";
1490*4882a593Smuzhiyun};
1491*4882a593Smuzhiyun
1492*4882a593Smuzhiyun&usb_host1_ehci {
1493*4882a593Smuzhiyun	status = "okay";
1494*4882a593Smuzhiyun};
1495*4882a593Smuzhiyun
1496*4882a593Smuzhiyun&usb_host1_ohci {
1497*4882a593Smuzhiyun	status = "okay";
1498*4882a593Smuzhiyun};
1499*4882a593Smuzhiyun
1500*4882a593Smuzhiyun&usbdrd_dwc3 {
1501*4882a593Smuzhiyun	dr_mode = "otg";
1502*4882a593Smuzhiyun	extcon = <&usb2phy0>;
1503*4882a593Smuzhiyun	status = "okay";
1504*4882a593Smuzhiyun};
1505*4882a593Smuzhiyun
1506*4882a593Smuzhiyun&usbdrd30 {
1507*4882a593Smuzhiyun	status = "okay";
1508*4882a593Smuzhiyun};
1509*4882a593Smuzhiyun
1510*4882a593Smuzhiyun&usbhost_dwc3 {
1511*4882a593Smuzhiyun	status = "okay";
1512*4882a593Smuzhiyun};
1513*4882a593Smuzhiyun
1514*4882a593Smuzhiyun&usbhost30 {
1515*4882a593Smuzhiyun	status = "okay";
1516*4882a593Smuzhiyun};
1517*4882a593Smuzhiyun
1518*4882a593Smuzhiyun&vad {
1519*4882a593Smuzhiyun	rockchip,audio-src = <&i2s1_8ch>;
1520*4882a593Smuzhiyun	rockchip,buffer-time-ms = <128>;
1521*4882a593Smuzhiyun	rockchip,det-channel = <0>;
1522*4882a593Smuzhiyun	rockchip,mode = <0>;
1523*4882a593Smuzhiyun};
1524*4882a593Smuzhiyun
1525*4882a593Smuzhiyun&vdpu {
1526*4882a593Smuzhiyun	status = "okay";
1527*4882a593Smuzhiyun};
1528*4882a593Smuzhiyun
1529*4882a593Smuzhiyun&vdpu_mmu {
1530*4882a593Smuzhiyun	status = "okay";
1531*4882a593Smuzhiyun};
1532*4882a593Smuzhiyun
1533*4882a593Smuzhiyun&vepu {
1534*4882a593Smuzhiyun	status = "okay";
1535*4882a593Smuzhiyun};
1536*4882a593Smuzhiyun
1537*4882a593Smuzhiyun&vepu_mmu {
1538*4882a593Smuzhiyun	status = "okay";
1539*4882a593Smuzhiyun};
1540*4882a593Smuzhiyun
1541*4882a593Smuzhiyun&vop {
1542*4882a593Smuzhiyun	status = "okay";
1543*4882a593Smuzhiyun	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
1544*4882a593Smuzhiyun	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>, <&cru PLL_GPLL>;
1545*4882a593Smuzhiyun	disable-win-move;
1546*4882a593Smuzhiyun};
1547*4882a593Smuzhiyun
1548*4882a593Smuzhiyun&vop_mmu {
1549*4882a593Smuzhiyun	status = "okay";
1550*4882a593Smuzhiyun};
1551*4882a593Smuzhiyun
1552*4882a593Smuzhiyun&vp0 {
1553*4882a593Smuzhiyun	cursor-win-id = <ROCKCHIP_VOP2_CLUSTER0>;
1554*4882a593Smuzhiyun};
1555*4882a593Smuzhiyun
1556*4882a593Smuzhiyun&vp1 {
1557*4882a593Smuzhiyun	cursor-win-id = <ROCKCHIP_VOP2_CLUSTER1>;
1558*4882a593Smuzhiyun};
1559*4882a593Smuzhiyun
1560*4882a593Smuzhiyun&edp {
1561*4882a593Smuzhiyun	status = "disabled";
1562*4882a593Smuzhiyun	pinctrl-names = "default";
1563*4882a593Smuzhiyun	pinctrl-0 = <&edpdpm0_pins>;
1564*4882a593Smuzhiyun
1565*4882a593Smuzhiyun	ports {
1566*4882a593Smuzhiyun		port@1 {
1567*4882a593Smuzhiyun			reg = <1>;
1568*4882a593Smuzhiyun
1569*4882a593Smuzhiyun			edp_out_panel: endpoint {
1570*4882a593Smuzhiyun				remote-endpoint = <&panel_in_edp>;
1571*4882a593Smuzhiyun			};
1572*4882a593Smuzhiyun		};
1573*4882a593Smuzhiyun	};
1574*4882a593Smuzhiyun};
1575*4882a593Smuzhiyun
1576*4882a593Smuzhiyun&edp_phy {
1577*4882a593Smuzhiyun	status = "disabled";
1578*4882a593Smuzhiyun};
1579*4882a593Smuzhiyun
1580*4882a593Smuzhiyun&edp_in_vp0 {
1581*4882a593Smuzhiyun	status = "disabled";
1582*4882a593Smuzhiyun};
1583*4882a593Smuzhiyun
1584*4882a593Smuzhiyun&edp_in_vp1 {
1585*4882a593Smuzhiyun	status = "disabled";
1586*4882a593Smuzhiyun};
1587*4882a593Smuzhiyun
1588*4882a593Smuzhiyun&route_edp {
1589*4882a593Smuzhiyun	status = "disabled";
1590*4882a593Smuzhiyun	connect = <&vp1_out_edp>;
1591*4882a593Smuzhiyun};
1592*4882a593Smuzhiyun&route_dsi1 {
1593*4882a593Smuzhiyun	status = "disabled";
1594*4882a593Smuzhiyun	connect = <&vp1_out_dsi1>;
1595*4882a593Smuzhiyun};
1596*4882a593Smuzhiyun
1597*4882a593Smuzhiyun&dsi1_in_vp0 {
1598*4882a593Smuzhiyun	status = "disabled";
1599*4882a593Smuzhiyun};
1600*4882a593Smuzhiyun
1601*4882a593Smuzhiyun&dsi1_in_vp1 {
1602*4882a593Smuzhiyun	status = "disabled";
1603*4882a593Smuzhiyun};
1604*4882a593Smuzhiyun
1605*4882a593Smuzhiyun&dsi1 {
1606*4882a593Smuzhiyun	status = "disabled";
1607*4882a593Smuzhiyun	//rockchip,lane-rate = <1000>;
1608*4882a593Smuzhiyun	dsi1_panel: panel@0 {
1609*4882a593Smuzhiyun		status = "okay";
1610*4882a593Smuzhiyun		compatible = "simple-panel-dsi";
1611*4882a593Smuzhiyun		reg = <0>;
1612*4882a593Smuzhiyun		reset-delay-ms = <60>;
1613*4882a593Smuzhiyun		enable-delay-ms = <60>;
1614*4882a593Smuzhiyun		prepare-delay-ms = <60>;
1615*4882a593Smuzhiyun		unprepare-delay-ms = <60>;
1616*4882a593Smuzhiyun		disable-delay-ms = <60>;
1617*4882a593Smuzhiyun		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
1618*4882a593Smuzhiyun			MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
1619*4882a593Smuzhiyun		dsi,format = <MIPI_DSI_FMT_RGB888>;
1620*4882a593Smuzhiyun		dsi,lanes  = <4>;
1621*4882a593Smuzhiyun		panel-init-sequence = [
1622*4882a593Smuzhiyun		];
1623*4882a593Smuzhiyun
1624*4882a593Smuzhiyun		panel-exit-sequence = [
1625*4882a593Smuzhiyun		];
1626*4882a593Smuzhiyun
1627*4882a593Smuzhiyun		panel-width-mm = <68>;
1628*4882a593Smuzhiyun        panel-height-mm = <121>;
1629*4882a593Smuzhiyun        backlight = <&dsi1_backlight>;
1630*4882a593Smuzhiyun		enable-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
1631*4882a593Smuzhiyun
1632*4882a593Smuzhiyun        display-timings {
1633*4882a593Smuzhiyun			native-mode = <&panel7_1024x600>;
1634*4882a593Smuzhiyun            panel7_1024x600: timings {
1635*4882a593Smuzhiyun                hback-porch     = <48>;
1636*4882a593Smuzhiyun                hfront-porch    = <40>;
1637*4882a593Smuzhiyun                hactive                 = <1024>;
1638*4882a593Smuzhiyun                hsync-len               = <48>;
1639*4882a593Smuzhiyun                vback-porch     = <48>;
1640*4882a593Smuzhiyun                vfront-porch    = <40>;
1641*4882a593Smuzhiyun                vactive         = <600>;
1642*4882a593Smuzhiyun                vsync-len       = <4>;
1643*4882a593Smuzhiyun                clock-frequency = <45000000>;
1644*4882a593Smuzhiyun                vsync-active    = <0>;
1645*4882a593Smuzhiyun                hsync-active    = <0>;
1646*4882a593Smuzhiyun                de-active       = <0>;
1647*4882a593Smuzhiyun                pixelclk-active = <0>;
1648*4882a593Smuzhiyun            };
1649*4882a593Smuzhiyun        };
1650*4882a593Smuzhiyun
1651*4882a593Smuzhiyun		ports {
1652*4882a593Smuzhiyun			#address-cells = <1>;
1653*4882a593Smuzhiyun			#size-cells = <0>;
1654*4882a593Smuzhiyun
1655*4882a593Smuzhiyun			port@0 {
1656*4882a593Smuzhiyun				reg = <0>;
1657*4882a593Smuzhiyun				panel_in_dsi: endpoint {
1658*4882a593Smuzhiyun					remote-endpoint = <&dsi_out_panel>;
1659*4882a593Smuzhiyun				};
1660*4882a593Smuzhiyun			};
1661*4882a593Smuzhiyun		};
1662*4882a593Smuzhiyun	};
1663*4882a593Smuzhiyun
1664*4882a593Smuzhiyun	ports {
1665*4882a593Smuzhiyun		#address-cells = <1>;
1666*4882a593Smuzhiyun		#size-cells = <0>;
1667*4882a593Smuzhiyun
1668*4882a593Smuzhiyun		port@1 {
1669*4882a593Smuzhiyun			reg = <1>;
1670*4882a593Smuzhiyun			dsi_out_panel: endpoint {
1671*4882a593Smuzhiyun				remote-endpoint = <&panel_in_dsi>;
1672*4882a593Smuzhiyun			};
1673*4882a593Smuzhiyun		};
1674*4882a593Smuzhiyun	};
1675*4882a593Smuzhiyun
1676*4882a593Smuzhiyun};
1677*4882a593Smuzhiyun
1678*4882a593Smuzhiyun&hdmi {
1679*4882a593Smuzhiyun	status = "disabled";
1680*4882a593Smuzhiyun	rockchip,phy-table =
1681*4882a593Smuzhiyun		<92812500  0x8009 0x0000 0x0270>,
1682*4882a593Smuzhiyun		<165000000 0x800b 0x0000 0x026d>,
1683*4882a593Smuzhiyun		<185625000 0x800b 0x0000 0x01ed>,
1684*4882a593Smuzhiyun		<297000000 0x800b 0x0000 0x01ad>,
1685*4882a593Smuzhiyun		<594000000 0x8029 0x0000 0x0088>,
1686*4882a593Smuzhiyun		<000000000 0x0000 0x0000 0x0000>;
1687*4882a593Smuzhiyun};
1688*4882a593Smuzhiyun
1689*4882a593Smuzhiyun&hdmi_in_vp0 {
1690*4882a593Smuzhiyun	status = "disabled";
1691*4882a593Smuzhiyun};
1692*4882a593Smuzhiyun
1693*4882a593Smuzhiyun&hdmi_in_vp1 {
1694*4882a593Smuzhiyun	status = "disabled";
1695*4882a593Smuzhiyun};
1696*4882a593Smuzhiyun
1697*4882a593Smuzhiyun&route_hdmi {
1698*4882a593Smuzhiyun	status = "disabled";
1699*4882a593Smuzhiyun	connect = <&vp0_out_hdmi>;
1700*4882a593Smuzhiyun};
1701*4882a593Smuzhiyun
1702*4882a593Smuzhiyun&lvds {
1703*4882a593Smuzhiyun	status = "disabled";
1704*4882a593Smuzhiyun	phys = <&video_phy0>;
1705*4882a593Smuzhiyun	phy-names = "phy";
1706*4882a593Smuzhiyun
1707*4882a593Smuzhiyun	ports {
1708*4882a593Smuzhiyun		port@1 {
1709*4882a593Smuzhiyun			reg = <1>;
1710*4882a593Smuzhiyun
1711*4882a593Smuzhiyun			lvds_out_panel: endpoint {
1712*4882a593Smuzhiyun				remote-endpoint = <&panel_in_lvds>;
1713*4882a593Smuzhiyun			};
1714*4882a593Smuzhiyun		};
1715*4882a593Smuzhiyun	};
1716*4882a593Smuzhiyun};
1717*4882a593Smuzhiyun
1718*4882a593Smuzhiyun&lvds_in_vp1 {
1719*4882a593Smuzhiyun	status = "disabled";
1720*4882a593Smuzhiyun};
1721*4882a593Smuzhiyun
1722*4882a593Smuzhiyun&lvds_in_vp2 {
1723*4882a593Smuzhiyun	status = "disabled";
1724*4882a593Smuzhiyun};
1725*4882a593Smuzhiyun
1726*4882a593Smuzhiyun&route_lvds {
1727*4882a593Smuzhiyun	status = "disabled";
1728*4882a593Smuzhiyun	connect = <&vp2_out_lvds>;
1729*4882a593Smuzhiyun};
1730*4882a593Smuzhiyun
1731*4882a593Smuzhiyun&rgb {
1732*4882a593Smuzhiyun        status = "disabled";
1733*4882a593Smuzhiyun	phys = <&video_phy0>;
1734*4882a593Smuzhiyun	phy-names = "phy";
1735*4882a593Smuzhiyun
1736*4882a593Smuzhiyun        ports {
1737*4882a593Smuzhiyun                port@1 {
1738*4882a593Smuzhiyun                        reg = <1>;
1739*4882a593Smuzhiyun                        rgb_out_panel: endpoint {
1740*4882a593Smuzhiyun                                remote-endpoint = <&panel_in_rgb>;
1741*4882a593Smuzhiyun                        };
1742*4882a593Smuzhiyun                };
1743*4882a593Smuzhiyun        };
1744*4882a593Smuzhiyun};
1745*4882a593Smuzhiyun
1746*4882a593Smuzhiyun
1747*4882a593Smuzhiyun&rgb_in_vp2 {
1748*4882a593Smuzhiyun        status = "disabled";
1749*4882a593Smuzhiyun};
1750*4882a593Smuzhiyun
1751*4882a593Smuzhiyun&route_rgb {
1752*4882a593Smuzhiyun        status = "disabled";
1753*4882a593Smuzhiyun        connect = <&vp2_out_rgb>;
1754*4882a593Smuzhiyun};
1755*4882a593Smuzhiyun
1756*4882a593Smuzhiyun/*
1757*4882a593Smuzhiyun&rgb {
1758*4882a593Smuzhiyun        status = "okay";
1759*4882a593Smuzhiyun
1760*4882a593Smuzhiyun        ports {
1761*4882a593Smuzhiyun                port@1 {
1762*4882a593Smuzhiyun                        reg = <1>;
1763*4882a593Smuzhiyun                        rgb_out_panel: endpoint {
1764*4882a593Smuzhiyun                                remote-endpoint = <&panel_in_rgb>;
1765*4882a593Smuzhiyun                        };
1766*4882a593Smuzhiyun                };
1767*4882a593Smuzhiyun        };
1768*4882a593Smuzhiyun};
1769*4882a593Smuzhiyun
1770*4882a593Smuzhiyun
1771*4882a593Smuzhiyun&rgb_in_vp2 {
1772*4882a593Smuzhiyun        status = "okay";
1773*4882a593Smuzhiyun};
1774*4882a593Smuzhiyun
1775*4882a593Smuzhiyun&route_rgb {
1776*4882a593Smuzhiyun        status = "okay";
1777*4882a593Smuzhiyun        connect = <&vp2_out_rgb>;
1778*4882a593Smuzhiyun};
1779*4882a593Smuzhiyun*/
1780*4882a593Smuzhiyun&xin32k {
1781*4882a593Smuzhiyun	status = "disabled";
1782*4882a593Smuzhiyun};
1783*4882a593Smuzhiyun
1784*4882a593Smuzhiyun&uart3 {
1785*4882a593Smuzhiyun	status = "okay";
1786*4882a593Smuzhiyun	pinctrl-names = "default";
1787*4882a593Smuzhiyun	pinctrl-0 = <&uart3m1_xfer>;
1788*4882a593Smuzhiyun};
1789*4882a593Smuzhiyun
1790*4882a593Smuzhiyun&uart4 {
1791*4882a593Smuzhiyun	status = "okay";
1792*4882a593Smuzhiyun	pinctrl-names = "default";
1793*4882a593Smuzhiyun	pinctrl-0 = <&uart4m1_xfer>;
1794*4882a593Smuzhiyun};
1795*4882a593Smuzhiyun
1796*4882a593Smuzhiyun&uart5 {
1797*4882a593Smuzhiyun	status = "okay";
1798*4882a593Smuzhiyun	pinctrl-names = "default";
1799*4882a593Smuzhiyun	pinctrl-0 = <&uart5m1_xfer>;
1800*4882a593Smuzhiyun};
1801*4882a593Smuzhiyun
1802*4882a593Smuzhiyun&spi0 {
1803*4882a593Smuzhiyun	pinctrl-names = "default", "high_speed";
1804*4882a593Smuzhiyun	pinctrl-0 = <&spi0m1_cs0 &spi0m1_pins>;
1805*4882a593Smuzhiyun	pinctrl-1 = <&spi0m1_cs0 &spi0m1_pins_hs>;
1806*4882a593Smuzhiyun	status = "disabled";
1807*4882a593Smuzhiyun
1808*4882a593Smuzhiyun	spi@0 {
1809*4882a593Smuzhiyun		compatible = "rockchip,spidev";
1810*4882a593Smuzhiyun		reg = <0>;
1811*4882a593Smuzhiyun		spi-max-frequency = <50000000>;
1812*4882a593Smuzhiyun	};
1813*4882a593Smuzhiyun};
1814*4882a593Smuzhiyun
1815*4882a593Smuzhiyun&spi2 {
1816*4882a593Smuzhiyun	pinctrl-names = "default", "high_speed";
1817*4882a593Smuzhiyun	pinctrl-0 = <&spi2m1_cs0 &spi2m1_cs1 &spi2m1_pins>;
1818*4882a593Smuzhiyun	pinctrl-1 = <&spi2m1_cs0 &spi2m1_cs1 &spi2m1_pins_hs>;
1819*4882a593Smuzhiyun	status = "okay";
1820*4882a593Smuzhiyun
1821*4882a593Smuzhiyun	spi@0 {
1822*4882a593Smuzhiyun		compatible = "rockchip,spidev";
1823*4882a593Smuzhiyun		reg = <0>;
1824*4882a593Smuzhiyun		spi-max-frequency = <50000000>;
1825*4882a593Smuzhiyun	};
1826*4882a593Smuzhiyun
1827*4882a593Smuzhiyun	spi@1 {
1828*4882a593Smuzhiyun		compatible = "rockchip,spidev";
1829*4882a593Smuzhiyun		reg = <1>;
1830*4882a593Smuzhiyun		spi-max-frequency = <50000000>;
1831*4882a593Smuzhiyun	};
1832*4882a593Smuzhiyun};
1833