1/* 2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 ethernet0 = &gmac0; 10 ethernet1 = &gmac1; 11 mmc0 = &sdhci; 12 mmc1 = &sdmmc0; 13 mmc2 = &sdmmc1; 14 }; 15 16 chosen { 17 stdout-path = &uart2; 18 u-boot,spl-boot-order = &sdmmc0, &sdhci, &nandc0, &spi_nand, &spi_nor; 19 }; 20 21 secure-otp@fe3a0000 { 22 compatible = "rockchip,rk3568-secure-otp"; 23 reg = <0x0 0xfe3a0000 0x0 0x4000>; 24 secure_conf = <0xfdd18008>; 25 mask_addr = <0xfe880000>; 26 cru_rst_addr = <0xfdd20470>; 27 u-boot,dm-spl; 28 }; 29}; 30 31&i2c0 { 32 u-boot,dm-spl; 33 u-boot,dm-pre-reloc; 34 status = "okay"; 35}; 36&i2c0_xfer { 37 u-boot,dm-spl; 38 u-boot,dm-pre-reloc; 39 status = "okay"; 40}; 41&pcfg_pull_none_smt { 42 u-boot,dm-spl; 43 u-boot,dm-pre-reloc; 44 status = "okay"; 45}; 46 47&psci { 48 u-boot,dm-pre-reloc; 49 status = "okay"; 50}; 51 52&crypto { 53 u-boot,dm-spl; 54}; 55 56&uart2 { 57 clock-frequency = <24000000>; 58 u-boot,dm-spl; 59 /delete-property/ pinctrl-names; 60 /delete-property/ pinctrl-0; 61 status = "okay"; 62}; 63 64&grf { 65 u-boot,dm-spl; 66 status = "okay"; 67}; 68 69&pmugrf { 70 u-boot,dm-spl; 71 status = "okay"; 72}; 73 74&usb2phy0_grf { 75 u-boot,dm-pre-reloc; 76 status = "okay"; 77}; 78 79&usbdrd30 { 80 u-boot,dm-pre-reloc; 81 status = "okay"; 82}; 83 84&usbdrd_dwc3 { 85 u-boot,dm-pre-reloc; 86 status = "okay"; 87}; 88 89&usbhost30 { 90 u-boot,dm-pre-reloc; 91 status = "okay"; 92}; 93 94&usbhost_dwc3 { 95 u-boot,dm-pre-reloc; 96 status = "okay"; 97}; 98 99&usb2phy0 { 100 u-boot,dm-pre-reloc; 101 status = "okay"; 102}; 103 104&u2phy0_otg { 105 u-boot,dm-pre-reloc; 106 status = "okay"; 107}; 108 109&u2phy0_host { 110 u-boot,dm-pre-reloc; 111 status = "okay"; 112}; 113 114&cru { 115 u-boot,dm-spl; 116 status = "okay"; 117}; 118 119&pmucru { 120 u-boot,dm-spl; 121 status = "okay"; 122}; 123 124&pmugrf { 125 u-boot,dm-spl; 126 status = "okay"; 127}; 128 129&rng { 130 u-boot,dm-pre-reloc; 131 status = "okay"; 132}; 133 134&sfc { 135 u-boot,dm-spl; 136 /delete-property/ pinctrl-names; 137 /delete-property/ pinctrl-0; 138 /delete-property/ assigned-clocks; 139 /delete-property/ assigned-clock-rates; 140 status = "okay"; 141 142 #address-cells = <1>; 143 #size-cells = <0>; 144 spi_nand: flash@0 { 145 u-boot,dm-spl; 146 compatible = "spi-nand"; 147 reg = <0>; 148 spi-tx-bus-width = <1>; 149 spi-rx-bus-width = <4>; 150 spi-max-frequency = <75000000>; 151 }; 152 153 spi_nor: flash@1 { 154 u-boot,dm-spl; 155 compatible = "jedec,spi-nor"; 156 label = "sfc_nor"; 157 reg = <0>; 158 spi-tx-bus-width = <1>; 159 spi-rx-bus-width = <4>; 160 spi-max-frequency = <100000000>; 161 }; 162}; 163 164&saradc { 165 u-boot,dm-pre-reloc; 166 status = "okay"; 167}; 168 169&sdmmc0 { 170 u-boot,dm-spl; 171 status = "okay"; 172}; 173 174&sdmmc0_pins { 175 u-boot,dm-spl; 176}; 177 178&sdmmc0_bus4 { 179 u-boot,dm-spl; 180}; 181 182&sdmmc0_clk { 183 u-boot,dm-spl; 184}; 185 186&sdmmc0_cmd { 187 u-boot,dm-spl; 188}; 189 190&sdmmc0_det { 191 u-boot,dm-spl; 192}; 193 194&sdmmc1 { 195 u-boot,dm-spl; 196 /delete-property/ pinctrl-names; 197 /delete-property/ pinctrl-0; 198 status = "okay"; 199}; 200 201&sdhci { 202 bus-width = <8>; 203 u-boot,dm-spl; 204 /delete-property/ pinctrl-names; 205 /delete-property/ pinctrl-0; 206 mmc-hs200-1_8v; 207 status = "okay"; 208}; 209 210&nandc0 { 211 u-boot,dm-spl; 212 status = "okay"; 213 #address-cells = <1>; 214 #size-cells = <0>; 215 /delete-property/ pinctrl-names; 216 /delete-property/ pinctrl-0; 217 218 nand@0 { 219 u-boot,dm-spl; 220 reg = <0>; 221 nand-ecc-mode = "hw"; 222 nand-ecc-strength = <16>; 223 nand-ecc-step-size = <1024>; 224 }; 225}; 226 227&gmac0_clkin { 228 u-boot,dm-pre-reloc; 229}; 230 231&gmac1_clkin { 232 u-boot,dm-pre-reloc; 233}; 234 235&gmac0 { 236 u-boot,dm-pre-reloc; 237 phy-mode = "rgmii"; 238 clock_in_out = "output"; 239 240 snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; 241 snps,reset-active-low; 242 /* Reset time is 20ms, 100ms for rtl8211f */ 243 snps,reset-delays-us = <0 20000 100000>; 244 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 245 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; 246 assigned-clock-rates = <0>, <125000000>; 247 248 pinctrl-names = "default"; 249 pinctrl-0 = <&gmac0_miim 250 &gmac0_tx_bus2 251 &gmac0_rx_bus2 252 &gmac0_rgmii_clk 253 &gmac0_rgmii_bus>; 254 255 tx_delay = <0x3c>; 256 rx_delay = <0x2f>; 257 258 phy-handle = <&rgmii_phy0>; 259 status = "disabled"; 260}; 261 262&gmac1 { 263 u-boot,dm-pre-reloc; 264 phy-mode = "rgmii"; 265 clock_in_out = "output"; 266 267 snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; 268 snps,reset-active-low; 269 /* Reset time is 20ms, 100ms for rtl8211f */ 270 snps,reset-delays-us = <0 20000 100000>; 271 272 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 273 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; 274 assigned-clock-rates = <0>, <125000000>; 275 276 pinctrl-names = "default"; 277 pinctrl-0 = <&gmac1m1_miim 278 &gmac1m1_tx_bus2 279 &gmac1m1_rx_bus2 280 &gmac1m1_rgmii_clk 281 &gmac1m1_rgmii_bus>; 282 283 tx_delay = <0x4f>; 284 rx_delay = <0x26>; 285 286 phy-handle = <&rgmii_phy1>; 287 status = "disabled"; 288}; 289 290&gmac0_stmmac_axi_setup { 291 u-boot,dm-pre-reloc; 292}; 293 294&gmac0_mtl_rx_setup { 295 u-boot,dm-pre-reloc; 296 queue0 { 297 u-boot,dm-pre-reloc; 298 }; 299}; 300 301&gmac0_mtl_tx_setup { 302 u-boot,dm-pre-reloc; 303 queue0 { 304 u-boot,dm-pre-reloc; 305 }; 306}; 307 308&gmac1_stmmac_axi_setup { 309 u-boot,dm-pre-reloc; 310}; 311 312&gmac1_mtl_rx_setup { 313 u-boot,dm-pre-reloc; 314 queue0 { 315 u-boot,dm-pre-reloc; 316 }; 317}; 318 319&gmac1_mtl_tx_setup { 320 u-boot,dm-pre-reloc; 321 queue0 { 322 u-boot,dm-pre-reloc; 323 }; 324}; 325 326&mdio0 { 327 u-boot,dm-pre-reloc; 328 rgmii_phy0: phy@0 { 329 compatible = "ethernet-phy-ieee802.3-c22"; 330 u-boot,dm-pre-reloc; 331 reg = <0x0>; 332 }; 333}; 334 335&mdio1 { 336 u-boot,dm-pre-reloc; 337 rgmii_phy1: phy@0 { 338 compatible = "ethernet-phy-ieee802.3-c22"; 339 u-boot,dm-pre-reloc; 340 reg = <0x0>; 341 }; 342}; 343 344&gmac0_miim { 345 u-boot,dm-pre-reloc; 346}; 347 348&gmac0_clkinout { 349 u-boot,dm-pre-reloc; 350}; 351 352&gmac0_rx_bus2 { 353 u-boot,dm-pre-reloc; 354}; 355 356&gmac0_tx_bus2 { 357 u-boot,dm-pre-reloc; 358}; 359 360&gmac0_rgmii_clk { 361 u-boot,dm-pre-reloc; 362}; 363 364&gmac0_rgmii_bus { 365 u-boot,dm-pre-reloc; 366}; 367 368&gmac1m1_miim { 369 u-boot,dm-pre-reloc; 370}; 371 372&gmac1m1_clkinout { 373 u-boot,dm-pre-reloc; 374}; 375 376&gmac1m1_rx_bus2 { 377 u-boot,dm-pre-reloc; 378}; 379 380&gmac1m1_tx_bus2 { 381 u-boot,dm-pre-reloc; 382}; 383 384&gmac1m1_rgmii_clk { 385 u-boot,dm-pre-reloc; 386}; 387 388&gmac1m1_rgmii_bus { 389 u-boot,dm-pre-reloc; 390}; 391 392ð0_clkout_pins { 393 u-boot,dm-pre-reloc; 394}; 395 396ð1m1_clkout_pins { 397 u-boot,dm-pre-reloc; 398}; 399 400&pcie30phy { 401 u-boot,dm-pre-reloc; 402 status = "okay"; 403}; 404 405&pcie3x2 { 406 u-boot,dm-pre-reloc; 407 status = "okay"; 408}; 409 410&pinctrl { 411 u-boot,dm-pre-reloc; 412 status = "okay"; 413}; 414 415&gpio0 { 416 u-boot,dm-spl; 417}; 418 419&gpio1 { 420 u-boot,dm-spl; 421}; 422 423&gpio2 { 424 u-boot,dm-spl; 425}; 426 427&pcfg_pull_none_drv_level_1 { 428 u-boot,dm-spl; 429}; 430 431&pcfg_pull_none_drv_level_2 { 432 u-boot,dm-spl; 433}; 434 435 436&pcfg_pull_up_drv_level_1 { 437 u-boot,dm-spl; 438}; 439 440&pcfg_pull_up_drv_level_2 { 441 u-boot,dm-spl; 442}; 443 444&pcfg_pull_up { 445 u-boot,dm-spl; 446}; 447 448&pcfg_pull_none { 449 u-boot,dm-spl; 450}; 451 452&wdt { 453 u-boot,dm-pre-reloc; 454 status = "okay"; 455}; 456 457&otp { 458 u-boot,dm-spl; 459 status = "okay"; 460}; 461 462#if 0 463&i2c0 { 464 u-boot,dm-spl; 465 u-boot,dm-pre-reloc; 466 status = "okay"; 467 i2c_eeprom:eeprom@51 { 468 compatible = "atmel,24c256", "i2c-eeprom"; 469 reg = <0x51>; 470 pagesize = <64>; 471 }; 472}; 473&i2c0_xfer { 474 u-boot,dm-spl; 475 u-boot,dm-pre-reloc; 476 status = "okay"; 477}; 478&pcfg_pull_none_smt { 479 u-boot,dm-spl; 480 u-boot,dm-pre-reloc; 481 status = "okay"; 482}; 483 484&i2c1 { 485 u-boot,dm-pre-reloc; 486 status = "okay"; 487}; 488 489&i2c1_xfer { 490 u-boot,dm-pre-reloc; 491 status = "okay"; 492}; 493 494&pcfg_pull_none_smt { 495 u-boot,dm-pre-reloc; 496 status = "okay"; 497}; 498#endif 499 500