xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3568-toybrick-x0.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
8*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h>
9*4882a593Smuzhiyun#include "rk3568.dtsi"
10*4882a593Smuzhiyun#include "rk3568-toybrick.dtsi"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/delete-node/ &adc_keys;
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun/ {
15*4882a593Smuzhiyun	compatible = "rockchip,rk3568-toybrick", "rockchip,rk3568";
16*4882a593Smuzhiyun	adc-keys {
17*4882a593Smuzhiyun		compatible = "adc-keys";
18*4882a593Smuzhiyun		io-channels = <&saradc 0>;
19*4882a593Smuzhiyun		io-channel-names = "buttons";
20*4882a593Smuzhiyun		poll-interval = <100>;
21*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun		menu-key {
24*4882a593Smuzhiyun		    linux,code = <KEY_MENU>;
25*4882a593Smuzhiyun		    label = "menu";
26*4882a593Smuzhiyun		    press-threshold-microvolt = <1250000>;
27*4882a593Smuzhiyun		};
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun		mute-key {
30*4882a593Smuzhiyun		    linux,code = <KEY_MUTE>;
31*4882a593Smuzhiyun		    label = "mute";
32*4882a593Smuzhiyun		    press-threshold-microvolt = <850000>;
33*4882a593Smuzhiyun		};
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun		vol-down-key {
36*4882a593Smuzhiyun		    linux,code = <KEY_VOLUMEDOWN>;
37*4882a593Smuzhiyun		    label = "volume down";
38*4882a593Smuzhiyun		    press-threshold-microvolt = <400000>;
39*4882a593Smuzhiyun		};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun		vol-up-key {
42*4882a593Smuzhiyun		    linux,code = <KEY_VOLUMEUP>;
43*4882a593Smuzhiyun		    label = "volume up";
44*4882a593Smuzhiyun		    press-threshold-microvolt = <20000>;
45*4882a593Smuzhiyun		};
46*4882a593Smuzhiyun	};
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun    gpio_leds: gpio-leds {
49*4882a593Smuzhiyun		compatible = "gpio-leds";
50*4882a593Smuzhiyun		led@1 {
51*4882a593Smuzhiyun			gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
52*4882a593Smuzhiyun			label = "blue"; // Blue LED
53*4882a593Smuzhiyun			retain-state-suspended;
54*4882a593Smuzhiyun		};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun		led@2 {
57*4882a593Smuzhiyun			gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>;
58*4882a593Smuzhiyun			label = "red"; // Red LED
59*4882a593Smuzhiyun			retain-state-suspended;
60*4882a593Smuzhiyun		};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun		led@3 {
63*4882a593Smuzhiyun			gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
64*4882a593Smuzhiyun			label = "green"; // Green LED
65*4882a593Smuzhiyun			retain-state-suspended;
66*4882a593Smuzhiyun		};
67*4882a593Smuzhiyun	};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun	pcie20_3v3: gpio-regulator {
70*4882a593Smuzhiyun		compatible = "regulator-gpio";
71*4882a593Smuzhiyun		regulator-name = "pcie20_3v3";
72*4882a593Smuzhiyun		regulator-min-microvolt = <100000>;
73*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
74*4882a593Smuzhiyun		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
75*4882a593Smuzhiyun		gpios-states = <0x1>;
76*4882a593Smuzhiyun		states = <100000 0x0
77*4882a593Smuzhiyun			  3300000 0x1>;
78*4882a593Smuzhiyun	};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun	pcie30_avdd0v9: pcie30-avdd0v9 {
81*4882a593Smuzhiyun		compatible = "regulator-fixed";
82*4882a593Smuzhiyun		regulator-name = "pcie30_avdd0v9";
83*4882a593Smuzhiyun		regulator-always-on;
84*4882a593Smuzhiyun		regulator-boot-on;
85*4882a593Smuzhiyun		regulator-min-microvolt = <900000>;
86*4882a593Smuzhiyun		regulator-max-microvolt = <900000>;
87*4882a593Smuzhiyun		vin-supply = <&vcc3v3_sys>;
88*4882a593Smuzhiyun	};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun	pcie30_avdd1v8: pcie30-avdd1v8 {
91*4882a593Smuzhiyun		compatible = "regulator-fixed";
92*4882a593Smuzhiyun		regulator-name = "pcie30_avdd1v8";
93*4882a593Smuzhiyun		regulator-always-on;
94*4882a593Smuzhiyun		regulator-boot-on;
95*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
96*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
97*4882a593Smuzhiyun		vin-supply = <&vcc3v3_sys>;
98*4882a593Smuzhiyun	};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun	pcie30_3v3: gpio-regulator {
101*4882a593Smuzhiyun		compatible = "regulator-gpio";
102*4882a593Smuzhiyun		regulator-name = "pcie30_3v3";
103*4882a593Smuzhiyun		regulator-min-microvolt = <100000>;
104*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
105*4882a593Smuzhiyun		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
106*4882a593Smuzhiyun		gpios-states = <0x1>;
107*4882a593Smuzhiyun		states = <100000 0x0
108*4882a593Smuzhiyun			  3300000 0x1>;
109*4882a593Smuzhiyun	};
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun	rk_headset: rk-headset {
112*4882a593Smuzhiyun		compatible = "rockchip_headset";
113*4882a593Smuzhiyun		headset_gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>;
114*4882a593Smuzhiyun		pinctrl-names = "default";
115*4882a593Smuzhiyun		pinctrl-0 = <&hp_det>;
116*4882a593Smuzhiyun		io-channels = <&saradc 1>;
117*4882a593Smuzhiyun	};
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun	rk809_sound_micarray: rk809-sound-micarray {
120*4882a593Smuzhiyun		status = "disabled";
121*4882a593Smuzhiyun		compatible = "simple-audio-card";
122*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
123*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,rk809-codec";
124*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun		simple-audio-card,dai-link@0 {
127*4882a593Smuzhiyun			format = "i2s";
128*4882a593Smuzhiyun			cpu {
129*4882a593Smuzhiyun				sound-dai = <&i2s1_8ch>;
130*4882a593Smuzhiyun			};
131*4882a593Smuzhiyun			codec {
132*4882a593Smuzhiyun				sound-dai = <&rk809_codec 0>;
133*4882a593Smuzhiyun			};
134*4882a593Smuzhiyun		};
135*4882a593Smuzhiyun		simple-audio-card,dai-link@1 {
136*4882a593Smuzhiyun			format = "i2s";
137*4882a593Smuzhiyun			cpu {
138*4882a593Smuzhiyun				sound-dai = <&i2s1_8ch>;
139*4882a593Smuzhiyun			};
140*4882a593Smuzhiyun			codec {
141*4882a593Smuzhiyun				sound-dai = <&es7210>;
142*4882a593Smuzhiyun			};
143*4882a593Smuzhiyun		};
144*4882a593Smuzhiyun	};
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun	rt5672-sound {
147*4882a593Smuzhiyun		compatible = "rockchip-rt5670";
148*4882a593Smuzhiyun		status = "disabled";
149*4882a593Smuzhiyun		dais {
150*4882a593Smuzhiyun			dai0 {
151*4882a593Smuzhiyun				audio-codec = <&rt5670>;
152*4882a593Smuzhiyun				audio-controller = <&i2s1_8ch>;
153*4882a593Smuzhiyun				format = "i2s";
154*4882a593Smuzhiyun			};
155*4882a593Smuzhiyun			dai1 {
156*4882a593Smuzhiyun				audio-codec = <&rt5670>;
157*4882a593Smuzhiyun				audio-controller = <&i2s1_8ch>;
158*4882a593Smuzhiyun				format = "i2s";
159*4882a593Smuzhiyun			};
160*4882a593Smuzhiyun			dai2 {
161*4882a593Smuzhiyun				audio-codec = <&es7210>;
162*4882a593Smuzhiyun				audio-controller = <&i2s1_8ch>;
163*4882a593Smuzhiyun				format = "i2s";
164*4882a593Smuzhiyun			};
165*4882a593Smuzhiyun		};
166*4882a593Smuzhiyun	};
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun	vcc2v5_sys: vcc2v5-ddr {
169*4882a593Smuzhiyun		compatible = "regulator-fixed";
170*4882a593Smuzhiyun		regulator-name = "vcc2v5-sys";
171*4882a593Smuzhiyun		regulator-always-on;
172*4882a593Smuzhiyun		regulator-boot-on;
173*4882a593Smuzhiyun		regulator-min-microvolt = <2500000>;
174*4882a593Smuzhiyun		regulator-max-microvolt = <2500000>;
175*4882a593Smuzhiyun		vin-supply = <&vcc3v3_sys>;
176*4882a593Smuzhiyun	};
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun    vcc_camera: vcc-camera-regulator {
179*4882a593Smuzhiyun		compatible = "regulator-fixed";
180*4882a593Smuzhiyun		gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
181*4882a593Smuzhiyun		pinctrl-names = "default";
182*4882a593Smuzhiyun		pinctrl-0 = <&camera_pwr>;
183*4882a593Smuzhiyun		regulator-name = "vcc_camera";
184*4882a593Smuzhiyun		enable-active-high;
185*4882a593Smuzhiyun		regulator-always-on;
186*4882a593Smuzhiyun		regulator-boot-on;
187*4882a593Smuzhiyun	};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun	vcc3v3_bu: vcc3v3-bu {
190*4882a593Smuzhiyun		compatible = "regulator-fixed";
191*4882a593Smuzhiyun		regulator-name = "vcc3v3_bu";
192*4882a593Smuzhiyun		regulator-always-on;
193*4882a593Smuzhiyun		regulator-boot-on;
194*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
195*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
196*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
197*4882a593Smuzhiyun	};
198*4882a593Smuzhiyun};
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun&combphy0_us {
201*4882a593Smuzhiyun	status = "okay";
202*4882a593Smuzhiyun};
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun&combphy1_usq {
205*4882a593Smuzhiyun	status = "okay";
206*4882a593Smuzhiyun};
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun&combphy2_psq {
209*4882a593Smuzhiyun	status = "okay";
210*4882a593Smuzhiyun};
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun&csi2_dphy_hw {
213*4882a593Smuzhiyun	status = "okay";
214*4882a593Smuzhiyun};
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun&csi2_dphy0 {
217*4882a593Smuzhiyun	status = "okay";
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun	ports {
220*4882a593Smuzhiyun		#address-cells = <1>;
221*4882a593Smuzhiyun		#size-cells = <0>;
222*4882a593Smuzhiyun		port@0 {
223*4882a593Smuzhiyun			reg = <0>;
224*4882a593Smuzhiyun			#address-cells = <1>;
225*4882a593Smuzhiyun			#size-cells = <0>;
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun			mipi_in_ucam0: endpoint@1 {
228*4882a593Smuzhiyun				reg = <1>;
229*4882a593Smuzhiyun				remote-endpoint = <&ucam_out0>;
230*4882a593Smuzhiyun				data-lanes = <1 2>;
231*4882a593Smuzhiyun			};
232*4882a593Smuzhiyun			mipi_in_ucam1: endpoint@2 {
233*4882a593Smuzhiyun				reg = <2>;
234*4882a593Smuzhiyun				remote-endpoint = <&gc8034_out>;
235*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
236*4882a593Smuzhiyun			};
237*4882a593Smuzhiyun			mipi_in_ucam2: endpoint@3 {
238*4882a593Smuzhiyun				reg = <3>;
239*4882a593Smuzhiyun				remote-endpoint = <&ov5695_out>;
240*4882a593Smuzhiyun				data-lanes = <1 2>;
241*4882a593Smuzhiyun			};
242*4882a593Smuzhiyun		};
243*4882a593Smuzhiyun		port@1 {
244*4882a593Smuzhiyun			reg = <1>;
245*4882a593Smuzhiyun			#address-cells = <1>;
246*4882a593Smuzhiyun			#size-cells = <0>;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun			csidphy_out: endpoint@0 {
249*4882a593Smuzhiyun				reg = <0>;
250*4882a593Smuzhiyun				remote-endpoint = <&isp0_in>;
251*4882a593Smuzhiyun			};
252*4882a593Smuzhiyun		};
253*4882a593Smuzhiyun	};
254*4882a593Smuzhiyun};
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun&gmac0 {
257*4882a593Smuzhiyun	phy-mode = "rgmii";
258*4882a593Smuzhiyun	clock_in_out = "output";
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun	snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
261*4882a593Smuzhiyun	snps,reset-active-low;
262*4882a593Smuzhiyun	/* Reset time is 20ms, 100ms for rtl8211f */
263*4882a593Smuzhiyun	snps,reset-delays-us = <0 20000 100000>;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
266*4882a593Smuzhiyun	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
267*4882a593Smuzhiyun	assigned-clock-rates = <0>, <125000000>;
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun	pinctrl-names = "default";
270*4882a593Smuzhiyun	pinctrl-0 = <&gmac0_miim
271*4882a593Smuzhiyun		     &gmac0_tx_bus2
272*4882a593Smuzhiyun		     &gmac0_rx_bus2
273*4882a593Smuzhiyun		     &gmac0_rgmii_clk
274*4882a593Smuzhiyun		     &gmac0_rgmii_bus>;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun	tx_delay = <0x37>;
277*4882a593Smuzhiyun	rx_delay = <0x2e>;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun	phy-handle = <&rgmii_phy0>;
280*4882a593Smuzhiyun	status = "okay";
281*4882a593Smuzhiyun};
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun&gmac1 {
284*4882a593Smuzhiyun	phy-mode = "rgmii";
285*4882a593Smuzhiyun	clock_in_out = "output";
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun	snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
288*4882a593Smuzhiyun	snps,reset-active-low;
289*4882a593Smuzhiyun	/* Reset time is 20ms, 100ms for rtl8211f */
290*4882a593Smuzhiyun	snps,reset-delays-us = <0 20000 100000>;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
293*4882a593Smuzhiyun	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
294*4882a593Smuzhiyun	assigned-clock-rates = <0>, <125000000>;
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun	pinctrl-names = "default";
297*4882a593Smuzhiyun	pinctrl-0 = <&gmac1m1_miim
298*4882a593Smuzhiyun		     &gmac1m1_tx_bus2
299*4882a593Smuzhiyun		     &gmac1m1_rx_bus2
300*4882a593Smuzhiyun		     &gmac1m1_rgmii_clk
301*4882a593Smuzhiyun		     &gmac1m1_rgmii_bus>;
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun	tx_delay = <0x47>;
304*4882a593Smuzhiyun	rx_delay = <0x28>;
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun	phy-handle = <&rgmii_phy1>;
307*4882a593Smuzhiyun	status = "okay";
308*4882a593Smuzhiyun};
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun&i2c3 {
311*4882a593Smuzhiyun	status = "okay";
312*4882a593Smuzhiyun	rt5670: rt5670@1c {
313*4882a593Smuzhiyun	    status = "okay";
314*4882a593Smuzhiyun		#sound-dai-cell = <0>;
315*4882a593Smuzhiyun		compatible = "realtek,rt5670";
316*4882a593Smuzhiyun		reg = <0x1c>;
317*4882a593Smuzhiyun	};
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun    es7210: es7210@40 {
320*4882a593Smuzhiyun		#sound-dai-cells = <0>;
321*4882a593Smuzhiyun		compatible = "MicArray_0";
322*4882a593Smuzhiyun		reg = <0x40>;
323*4882a593Smuzhiyun		clocks = <&cru I2S1_MCLKOUT_RX>;//csqerr
324*4882a593Smuzhiyun		clock-names = "mclk";
325*4882a593Smuzhiyun	};
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun	es7210_1: es7210@42 {
328*4882a593Smuzhiyun		compatible = "MicArray_1";
329*4882a593Smuzhiyun		reg = <0x42>;
330*4882a593Smuzhiyun	};
331*4882a593Smuzhiyun};
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun&i2c4 {
334*4882a593Smuzhiyun	status = "okay";
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun	gc8034: gc8034@37 {
337*4882a593Smuzhiyun		compatible = "galaxycore,gc8034";
338*4882a593Smuzhiyun		reg = <0x37>;
339*4882a593Smuzhiyun		clocks = <&cru CLK_CIF_OUT>;//CLK_CAM0_OUT>;
340*4882a593Smuzhiyun		clock-names = "xvclk";
341*4882a593Smuzhiyun		power-domains = <&power RK3568_PD_VI>;
342*4882a593Smuzhiyun		pinctrl-names = "default";
343*4882a593Smuzhiyun		pinctrl-0 = <&cif_clk>;
344*4882a593Smuzhiyun		reset-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
345*4882a593Smuzhiyun		pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>;
346*4882a593Smuzhiyun		rockchip,grf = <&grf>;
347*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
348*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
349*4882a593Smuzhiyun		rockchip,camera-module-name = "RK-CMK-8M-2-v1";
350*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "CK8401";
351*4882a593Smuzhiyun		port {
352*4882a593Smuzhiyun			gc8034_out: endpoint {
353*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam1>;
354*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
355*4882a593Smuzhiyun			};
356*4882a593Smuzhiyun		};
357*4882a593Smuzhiyun	};
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun    ov9750_1: ov9750_1@36 {
360*4882a593Smuzhiyun		compatible = "ovti,ov9750";
361*4882a593Smuzhiyun		reg = <0x36>;
362*4882a593Smuzhiyun		clocks = <&cru CLK_CIF_OUT>;
363*4882a593Smuzhiyun		clock-names = "xvclk";
364*4882a593Smuzhiyun		pinctrl-names = "default";
365*4882a593Smuzhiyun		pinctrl-0 = <&cif_clk>;
366*4882a593Smuzhiyun		power-domains = <&power RK3568_PD_VI>;
367*4882a593Smuzhiyun		reset-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
368*4882a593Smuzhiyun		pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
369*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
370*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
371*4882a593Smuzhiyun		rockchip,camera-module-name = "CMK-OT0854-FV1";
372*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "CHT-842B-MD";
373*4882a593Smuzhiyun		port {
374*4882a593Smuzhiyun			ucam_out0: endpoint {
375*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam0>;
376*4882a593Smuzhiyun				data-lanes = <1 2>;
377*4882a593Smuzhiyun			};
378*4882a593Smuzhiyun		};
379*4882a593Smuzhiyun	};
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun	ov5695: ov5695@36 {
382*4882a593Smuzhiyun		status = "okay";
383*4882a593Smuzhiyun		compatible = "ovti,ov5695";
384*4882a593Smuzhiyun		reg = <0x36>;
385*4882a593Smuzhiyun		clocks = <&cru CLK_CIF_OUT>;
386*4882a593Smuzhiyun		clock-names = "xvclk";
387*4882a593Smuzhiyun		power-domains = <&power RK3568_PD_VI>;
388*4882a593Smuzhiyun		pinctrl-names = "default";
389*4882a593Smuzhiyun		pinctrl-0 = <&cif_clk>;
390*4882a593Smuzhiyun		reset-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
391*4882a593Smuzhiyun		pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>;
392*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
393*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
394*4882a593Smuzhiyun		rockchip,camera-module-name = "TongJu";
395*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "CHT842-MD";
396*4882a593Smuzhiyun		port {
397*4882a593Smuzhiyun			ov5695_out: endpoint {
398*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam2>;
399*4882a593Smuzhiyun				data-lanes = <1 2>;
400*4882a593Smuzhiyun			};
401*4882a593Smuzhiyun		};
402*4882a593Smuzhiyun	};
403*4882a593Smuzhiyun};
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun&i2c5 {
406*4882a593Smuzhiyun	status = "okay";
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun	gs_mxc6655xa: gs_mxc6655xa@15 {
409*4882a593Smuzhiyun		status = "okay";
410*4882a593Smuzhiyun		compatible = "gs_mxc6655xa";
411*4882a593Smuzhiyun		pinctrl-names = "default";
412*4882a593Smuzhiyun		pinctrl-0 = <&mxc6655xa_irq_pin>;
413*4882a593Smuzhiyun		reg = <0x15>;
414*4882a593Smuzhiyun		irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>;
415*4882a593Smuzhiyun		irq_enable = <0>;
416*4882a593Smuzhiyun		poll_delay_ms = <30>;
417*4882a593Smuzhiyun		type = <SENSOR_TYPE_ACCEL>;
418*4882a593Smuzhiyun		power-off-in-suspend = <1>;
419*4882a593Smuzhiyun		layout = <1>;
420*4882a593Smuzhiyun	};
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun    mxc6655xa: mxc6655xa@15 {
423*4882a593Smuzhiyun		status = "disabled";
424*4882a593Smuzhiyun		compatible = "gs_mxc6655xa";
425*4882a593Smuzhiyun		pinctrl-names = "default";
426*4882a593Smuzhiyun		pinctrl-0 = <&mxc6655xa_irq_pin>;
427*4882a593Smuzhiyun		reg = <0x15>;
428*4882a593Smuzhiyun		irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>;
429*4882a593Smuzhiyun		irq_enable = <0>;
430*4882a593Smuzhiyun		poll_delay_ms = <30>;
431*4882a593Smuzhiyun		type = <SENSOR_TYPE_ACCEL>;
432*4882a593Smuzhiyun		power-off-in-suspend = <1>;
433*4882a593Smuzhiyun		layout = <1>;
434*4882a593Smuzhiyun	};
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun    hym8563: hym8563@51 {
437*4882a593Smuzhiyun		compatible = "haoyu,hym8563";
438*4882a593Smuzhiyun		reg = <0x51>;
439*4882a593Smuzhiyun		pinctrl-names = "default";
440*4882a593Smuzhiyun		pinctrl-0 = <&rtc_int>;
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
443*4882a593Smuzhiyun		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
444*4882a593Smuzhiyun	};
445*4882a593Smuzhiyun};
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun&i2s1_8ch {
448*4882a593Smuzhiyun	status = "okay";
449*4882a593Smuzhiyun	#sound-dai-cells = <0>;
450*4882a593Smuzhiyun	rockchip,clk-trcm = <1>;
451*4882a593Smuzhiyun	pinctrl-names = "default";
452*4882a593Smuzhiyun	pinctrl-0 = <&i2s1m0_sclktx
453*4882a593Smuzhiyun		     &i2s1m0_sclkrx
454*4882a593Smuzhiyun		     &i2s1m0_lrcktx
455*4882a593Smuzhiyun		     &i2s1m0_sclkrx
456*4882a593Smuzhiyun		     &i2s1m0_lrckrx
457*4882a593Smuzhiyun		     &i2s1m0_sdo0
458*4882a593Smuzhiyun		     &i2s1m0_sdi0
459*4882a593Smuzhiyun		     &i2s1m0_sdi1
460*4882a593Smuzhiyun		     &i2s1m0_sdi2
461*4882a593Smuzhiyun		     &i2s1m0_sdi3>;
462*4882a593Smuzhiyun};
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun&mdio0 {
465*4882a593Smuzhiyun	rgmii_phy0: phy@0 {
466*4882a593Smuzhiyun		compatible = "ethernet-phy-ieee802.3-c22";
467*4882a593Smuzhiyun		reg = <0x0>;
468*4882a593Smuzhiyun	};
469*4882a593Smuzhiyun};
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun&mdio1 {
472*4882a593Smuzhiyun	rgmii_phy1: phy@0 {
473*4882a593Smuzhiyun		compatible = "ethernet-phy-ieee802.3-c22";
474*4882a593Smuzhiyun		reg = <0x0>;
475*4882a593Smuzhiyun	};
476*4882a593Smuzhiyun};
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun&pcie30phy {
479*4882a593Smuzhiyun	status = "okay";
480*4882a593Smuzhiyun};
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun&pcie3x2 {
483*4882a593Smuzhiyun	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
484*4882a593Smuzhiyun	vpcie3v3-supply = <&pcie30_3v3>;
485*4882a593Smuzhiyun	status = "okay";
486*4882a593Smuzhiyun};
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun&pwm7 {
489*4882a593Smuzhiyun	status = "okay";
490*4882a593Smuzhiyun};
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun&rk809_sound {
493*4882a593Smuzhiyun	status = "okay";
494*4882a593Smuzhiyun};
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun&rkisp {
497*4882a593Smuzhiyun	status = "okay";
498*4882a593Smuzhiyun};
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun&rkisp_mmu {
501*4882a593Smuzhiyun	status = "okay";
502*4882a593Smuzhiyun};
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun&rkisp_vir0 {
505*4882a593Smuzhiyun	status = "okay";
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun	port {
508*4882a593Smuzhiyun		#address-cells = <1>;
509*4882a593Smuzhiyun		#size-cells = <0>;
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun		isp0_in: endpoint@0 {
512*4882a593Smuzhiyun			reg = <0>;
513*4882a593Smuzhiyun			remote-endpoint = <&csidphy_out>;
514*4882a593Smuzhiyun		};
515*4882a593Smuzhiyun	};
516*4882a593Smuzhiyun};
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun&sata2 {
519*4882a593Smuzhiyun	status = "okay";
520*4882a593Smuzhiyun};
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun&sdio_pwrseq {
523*4882a593Smuzhiyun	compatible = "mmc-pwrseq-simple";
524*4882a593Smuzhiyun	clocks = <&rk809 1>;
525*4882a593Smuzhiyun	clock-names = "ext_clock";
526*4882a593Smuzhiyun	pinctrl-names = "default";
527*4882a593Smuzhiyun	pinctrl-0 = <&wifi_enable_h>;
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun	/*
530*4882a593Smuzhiyun	 * On the module itself this is one of these (depending
531*4882a593Smuzhiyun	 * on the actual card populated):
532*4882a593Smuzhiyun	 * - SDIO_RESET_L_WL_REG_ON
533*4882a593Smuzhiyun	 * - PDN (power down when low)
534*4882a593Smuzhiyun	 */
535*4882a593Smuzhiyun	reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
536*4882a593Smuzhiyun	post-power-on-delay-ms = <20>;
537*4882a593Smuzhiyun	status = "okay";
538*4882a593Smuzhiyun};
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun&sdmmc1 {
541*4882a593Smuzhiyun	status = "disabled";
542*4882a593Smuzhiyun};
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun&sdmmc2 {
545*4882a593Smuzhiyun	max-frequency = <150000000>;
546*4882a593Smuzhiyun	supports-sdio;
547*4882a593Smuzhiyun	bus-width = <4>;
548*4882a593Smuzhiyun	disable-wp;
549*4882a593Smuzhiyun	cap-sd-highspeed;
550*4882a593Smuzhiyun	cap-sdio-irq;
551*4882a593Smuzhiyun	keep-power-in-suspend;
552*4882a593Smuzhiyun	mmc-pwrseq = <&sdio_pwrseq>;
553*4882a593Smuzhiyun	non-removable;
554*4882a593Smuzhiyun	pinctrl-names = "default";
555*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
556*4882a593Smuzhiyun	sd-uhs-sdr104;
557*4882a593Smuzhiyun	status = "okay";
558*4882a593Smuzhiyun};
559*4882a593Smuzhiyun
560*4882a593Smuzhiyun&uart1 {
561*4882a593Smuzhiyun	status = "disabled";
562*4882a593Smuzhiyun	pinctrl-names = "default";
563*4882a593Smuzhiyun	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
564*4882a593Smuzhiyun};
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun&uart8 {
567*4882a593Smuzhiyun	status = "okay";
568*4882a593Smuzhiyun	pinctrl-names = "default";
569*4882a593Smuzhiyun	pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>;
570*4882a593Smuzhiyun};
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun&vcc3v3_lcd0_n {
573*4882a593Smuzhiyun	gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
574*4882a593Smuzhiyun	enable-active-high;
575*4882a593Smuzhiyun};
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun&vcc3v3_lcd1_n {
578*4882a593Smuzhiyun	gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
579*4882a593Smuzhiyun	enable-active-high;
580*4882a593Smuzhiyun};
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun&video_phy0 {
583*4882a593Smuzhiyun	status = "okay";
584*4882a593Smuzhiyun};
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun&video_phy1 {
587*4882a593Smuzhiyun	status = "disabled";
588*4882a593Smuzhiyun};
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun&wireless_wlan {
591*4882a593Smuzhiyun	pinctrl-names = "default";
592*4882a593Smuzhiyun	pinctrl-0 = <&wifi_host_wake_irq>;
593*4882a593Smuzhiyun	WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
594*4882a593Smuzhiyun};
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun&wireless_bluetooth {
597*4882a593Smuzhiyun	compatible = "bluetooth-platdata";
598*4882a593Smuzhiyun	clocks = <&rk809 1>;
599*4882a593Smuzhiyun	clock-names = "ext_clock";
600*4882a593Smuzhiyun	//wifi-bt-power-toggle;
601*4882a593Smuzhiyun	uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
602*4882a593Smuzhiyun	pinctrl-names = "default", "rts_gpio";
603*4882a593Smuzhiyun	pinctrl-0 = <&uart8m0_rtsn>;
604*4882a593Smuzhiyun	pinctrl-1 = <&uart8_pin>;
605*4882a593Smuzhiyun	BT,reset_gpio    = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
606*4882a593Smuzhiyun	BT,wake_gpio     = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
607*4882a593Smuzhiyun	BT,wake_host_irq = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
608*4882a593Smuzhiyun	status = "okay";
609*4882a593Smuzhiyun};
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun&pinctrl {
612*4882a593Smuzhiyun	cam {
613*4882a593Smuzhiyun		camera_pwr: camera-pwr {
614*4882a593Smuzhiyun			rockchip,pins =
615*4882a593Smuzhiyun				/* camera power en */
616*4882a593Smuzhiyun				<0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
617*4882a593Smuzhiyun		};
618*4882a593Smuzhiyun	};
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun	headphone {
621*4882a593Smuzhiyun		hp_det: hp-det {
622*4882a593Smuzhiyun			rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>;
623*4882a593Smuzhiyun		};
624*4882a593Smuzhiyun	};
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun	i2s1 {
627*4882a593Smuzhiyun		/omit-if-no-ref/
628*4882a593Smuzhiyun		i2s1m0_lrckrx: i2s1m0-lrckrx {
629*4882a593Smuzhiyun			rockchip,pins =
630*4882a593Smuzhiyun				/* i2s1m0_lrckrx */
631*4882a593Smuzhiyun				<1 RK_PA6 1 &pcfg_pull_up_drv_level_4>;
632*4882a593Smuzhiyun		};
633*4882a593Smuzhiyun		/omit-if-no-ref/
634*4882a593Smuzhiyun		i2s1m0_lrcktx: i2s1m0-lrcktx {
635*4882a593Smuzhiyun			rockchip,pins =
636*4882a593Smuzhiyun				/* i2s1m0_lrcktx */
637*4882a593Smuzhiyun				<1 RK_PA5 1 &pcfg_pull_up_drv_level_4>;
638*4882a593Smuzhiyun		};
639*4882a593Smuzhiyun		/omit-if-no-ref/
640*4882a593Smuzhiyun		i2s1m0_mclk: i2s1m0-mclk {
641*4882a593Smuzhiyun			rockchip,pins =
642*4882a593Smuzhiyun				/* i2s1m0_mclk */
643*4882a593Smuzhiyun				<1 RK_PA2 1 &pcfg_pull_up_drv_level_4>;
644*4882a593Smuzhiyun		};
645*4882a593Smuzhiyun		/omit-if-no-ref/
646*4882a593Smuzhiyun		i2s1m0_sclkrx: i2s1m0-sclkrx {
647*4882a593Smuzhiyun			rockchip,pins =
648*4882a593Smuzhiyun				/* i2s1m0_sclkrx */
649*4882a593Smuzhiyun				<1 RK_PA4 1 &pcfg_pull_up_drv_level_4>;
650*4882a593Smuzhiyun		};
651*4882a593Smuzhiyun		/omit-if-no-ref/
652*4882a593Smuzhiyun		i2s1m0_sclktx: i2s1m0-sclktx {
653*4882a593Smuzhiyun			rockchip,pins =
654*4882a593Smuzhiyun				/* i2s1m0_sclktx */
655*4882a593Smuzhiyun				<1 RK_PA3 1 &pcfg_pull_up_drv_level_4>;
656*4882a593Smuzhiyun		};
657*4882a593Smuzhiyun		/omit-if-no-ref/
658*4882a593Smuzhiyun		i2s1m0_sdi0: i2s1m0-sdi0 {
659*4882a593Smuzhiyun			rockchip,pins =
660*4882a593Smuzhiyun				/* i2s1m0_sdi0 */
661*4882a593Smuzhiyun				<1 RK_PB3 1 &pcfg_pull_up_drv_level_4>;
662*4882a593Smuzhiyun		};
663*4882a593Smuzhiyun		/omit-if-no-ref/
664*4882a593Smuzhiyun		i2s1m0_sdi1: i2s1m0-sdi1 {
665*4882a593Smuzhiyun			rockchip,pins =
666*4882a593Smuzhiyun				/* i2s1m0_sdi1 */
667*4882a593Smuzhiyun				<1 RK_PB2 2 &pcfg_pull_up_drv_level_4>;
668*4882a593Smuzhiyun		};
669*4882a593Smuzhiyun		/omit-if-no-ref/
670*4882a593Smuzhiyun		i2s1m0_sdi2: i2s1m0-sdi2 {
671*4882a593Smuzhiyun			rockchip,pins =
672*4882a593Smuzhiyun				/* i2s1m0_sdi2 */
673*4882a593Smuzhiyun				<1 RK_PB1 2 &pcfg_pull_up_drv_level_4>;
674*4882a593Smuzhiyun		};
675*4882a593Smuzhiyun		/omit-if-no-ref/
676*4882a593Smuzhiyun		i2s1m0_sdi3: i2s1m0-sdi3 {
677*4882a593Smuzhiyun			rockchip,pins =
678*4882a593Smuzhiyun				/* i2s1m0_sdi3 */
679*4882a593Smuzhiyun				<1 RK_PB0 2 &pcfg_pull_up_drv_level_4>;
680*4882a593Smuzhiyun		};
681*4882a593Smuzhiyun		/omit-if-no-ref/
682*4882a593Smuzhiyun		i2s1m0_sdo0: i2s1m0-sdo0 {
683*4882a593Smuzhiyun			rockchip,pins =
684*4882a593Smuzhiyun				/* i2s1m0_sdo0 */
685*4882a593Smuzhiyun				<1 RK_PA7 1 &pcfg_pull_up_drv_level_4>;
686*4882a593Smuzhiyun		};
687*4882a593Smuzhiyun	};
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun	leds_pin: leds-pin {
690*4882a593Smuzhiyun		rockchip,pins =
691*4882a593Smuzhiyun			<4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>,
692*4882a593Smuzhiyun			<4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>,
693*4882a593Smuzhiyun			<4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
694*4882a593Smuzhiyun	};
695*4882a593Smuzhiyun
696*4882a593Smuzhiyun	mxc6655xa {
697*4882a593Smuzhiyun		mxc6655xa_irq_pin: mxc6655xa_irq_pin {
698*4882a593Smuzhiyun			rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
699*4882a593Smuzhiyun		};
700*4882a593Smuzhiyun	};
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun	rtc {
703*4882a593Smuzhiyun		rtc_int: rtc-int {
704*4882a593Smuzhiyun			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
705*4882a593Smuzhiyun		};
706*4882a593Smuzhiyun	};
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun	sdio-pwrseq {
709*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
710*4882a593Smuzhiyun			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
711*4882a593Smuzhiyun		};
712*4882a593Smuzhiyun	};
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun	wireless-wlan {
715*4882a593Smuzhiyun		wifi_host_wake_irq: wifi-host-wake-irq {
716*4882a593Smuzhiyun			rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>;
717*4882a593Smuzhiyun		};
718*4882a593Smuzhiyun	};
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun	wireless-bluetooth {
721*4882a593Smuzhiyun		uart8_pin: uart8-pin {
722*4882a593Smuzhiyun			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
723*4882a593Smuzhiyun		};
724*4882a593Smuzhiyun	};
725*4882a593Smuzhiyun};
726