1/* 2 * SPDX-License-Identifier: GPL-2.0+ 3 * 4 * (C) Copyright 2021 Rockchip Electronics Co., Ltd 5 */ 6 7/dts-v1/; 8#include "rk3568.dtsi" 9#include <dt-bindings/input/input.h> 10 11/ { 12 model = "Rockchip RK3568 Evaluation Board"; 13 compatible = "rockchip,rk3568-evb", "rockchip,rk3568"; 14 15 aliases { 16 ethernet0 = &gmac0; 17 ethernet1 = &gmac1; 18 mmc0 = &sdhci; 19 mmc1 = &sdmmc0; 20 mmc2 = &sdmmc1; 21 }; 22 23 chosen { 24 stdout-path = &uart2; 25 u-boot,spl-boot-order = &spi_nand; 26 }; 27 28 adc-keys { 29 compatible = "adc-keys"; 30 io-channels = <&saradc 0>; 31 io-channel-names = "buttons"; 32 keyup-threshold-microvolt = <1800000>; 33 u-boot,dm-spl; 34 status = "okay"; 35 36 volumeup-key { 37 u-boot,dm-spl; 38 linux,code = <KEY_VOLUMEUP>; 39 label = "volume up"; 40 press-threshold-microvolt = <9>; 41 }; 42 }; 43}; 44 45&crypto { 46 u-boot,dm-pre-reloc; 47 status = "okay"; 48}; 49 50&uart2 { 51 clock-frequency = <24000000>; 52 u-boot,dm-spl; 53 /delete-property/ pinctrl-names; 54 /delete-property/ pinctrl-0; 55 status = "okay"; 56}; 57 58&grf { 59 u-boot,dm-pre-reloc; 60 status = "okay"; 61}; 62 63&pmugrf { 64 u-boot,dm-pre-reloc; 65 status = "okay"; 66}; 67 68&usb2phy0_grf { 69 u-boot,dm-pre-reloc; 70 status = "okay"; 71}; 72 73&usbdrd30 { 74 u-boot,dm-pre-reloc; 75 status = "okay"; 76}; 77 78&usbdrd_dwc3 { 79 u-boot,dm-pre-reloc; 80 status = "okay"; 81}; 82 83&usbhost30 { 84 u-boot,dm-pre-reloc; 85 status = "okay"; 86}; 87 88&usbhost_dwc3 { 89 u-boot,dm-pre-reloc; 90 status = "okay"; 91}; 92 93&usb2phy0 { 94 u-boot,dm-pre-reloc; 95 status = "okay"; 96}; 97 98&u2phy0_otg { 99 u-boot,dm-pre-reloc; 100 status = "okay"; 101}; 102 103&u2phy0_host { 104 u-boot,dm-pre-reloc; 105 status = "okay"; 106}; 107 108&cru { 109 u-boot,dm-pre-reloc; 110 status = "okay"; 111}; 112 113&pmucru { 114 u-boot,dm-pre-reloc; 115 status = "okay"; 116}; 117 118&gmac0_clkin{ 119 u-boot,dm-pre-reloc; 120}; 121 122&gmac1_clkin { 123 u-boot,dm-pre-reloc; 124}; 125 126&gmac0 { 127 u-boot,dm-pre-reloc; 128 phy-mode = "rgmii"; 129 clock_in_out = "output"; 130 131 snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; 132 snps,reset-active-low; 133 /* Reset time is 20ms, 100ms for rtl8211f */ 134 snps,reset-delays-us = <0 20000 100000>; 135 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 136 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; 137 assigned-clock-rates = <0>, <125000000>; 138 139 pinctrl-names = "default"; 140 pinctrl-0 = <&gmac0_miim 141 &gmac0_tx_bus2 142 &gmac0_rx_bus2 143 &gmac0_rgmii_clk 144 &gmac0_rgmii_bus>; 145 146 tx_delay = <0x3c>; 147 rx_delay = <0x2f>; 148 149 phy-handle = <&rgmii_phy0>; 150 status = "disabled"; 151}; 152 153&gmac1 { 154 u-boot,dm-pre-reloc; 155 phy-mode = "rgmii"; 156 clock_in_out = "output"; 157 158 snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; 159 snps,reset-active-low; 160 /* Reset time is 20ms, 100ms for rtl8211f */ 161 snps,reset-delays-us = <0 20000 100000>; 162 163 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 164 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; 165 assigned-clock-rates = <0>, <125000000>; 166 167 pinctrl-names = "default"; 168 pinctrl-0 = <&gmac1m1_miim 169 &gmac1m1_tx_bus2 170 &gmac1m1_rx_bus2 171 &gmac1m1_rgmii_clk 172 &gmac1m1_rgmii_bus>; 173 174 tx_delay = <0x4f>; 175 rx_delay = <0x26>; 176 177 phy-handle = <&rgmii_phy1>; 178 status = "disabled"; 179}; 180 181&gmac0_stmmac_axi_setup { 182 u-boot,dm-pre-reloc; 183}; 184 185&gmac0_mtl_rx_setup { 186 u-boot,dm-pre-reloc; 187 queue0 { 188 u-boot,dm-pre-reloc; 189 }; 190}; 191 192&gmac0_mtl_tx_setup { 193 u-boot,dm-pre-reloc; 194 queue0 { 195 u-boot,dm-pre-reloc; 196 }; 197}; 198 199&gmac1_stmmac_axi_setup { 200 u-boot,dm-pre-reloc; 201}; 202 203&gmac1_mtl_rx_setup { 204 u-boot,dm-pre-reloc; 205 queue0 { 206 u-boot,dm-pre-reloc; 207 }; 208}; 209 210&gmac1_mtl_tx_setup { 211 u-boot,dm-pre-reloc; 212 queue0 { 213 u-boot,dm-pre-reloc; 214 }; 215}; 216 217&mdio0 { 218 u-boot,dm-pre-reloc; 219 rgmii_phy0: phy@0 { 220 compatible = "ethernet-phy-ieee802.3-c22"; 221 u-boot,dm-pre-reloc; 222 reg = <0x0>; 223 }; 224}; 225 226&mdio1 { 227 u-boot,dm-pre-reloc; 228 rgmii_phy1: phy@0 { 229 compatible = "ethernet-phy-ieee802.3-c22"; 230 u-boot,dm-pre-reloc; 231 reg = <0x0>; 232 }; 233}; 234 235&gmac0_miim { 236 u-boot,dm-pre-reloc; 237}; 238 239&gmac0_clkinout { 240 u-boot,dm-pre-reloc; 241}; 242 243&gmac0_rx_bus2 { 244 u-boot,dm-pre-reloc; 245}; 246 247&gmac0_tx_bus2 { 248 u-boot,dm-pre-reloc; 249}; 250 251&gmac0_rgmii_clk { 252 u-boot,dm-pre-reloc; 253}; 254 255&gmac0_rgmii_bus { 256 u-boot,dm-pre-reloc; 257}; 258 259&gmac1m1_miim { 260 u-boot,dm-pre-reloc; 261}; 262 263&gmac1m1_clkinout { 264 u-boot,dm-pre-reloc; 265}; 266 267&gmac1m1_rx_bus2 { 268 u-boot,dm-pre-reloc; 269}; 270 271&gmac1m1_tx_bus2 { 272 u-boot,dm-pre-reloc; 273}; 274 275&gmac1m1_rgmii_clk { 276 u-boot,dm-pre-reloc; 277}; 278 279&gmac1m1_rgmii_bus { 280 u-boot,dm-pre-reloc; 281}; 282 283ð0_clkout_pins { 284 u-boot,dm-pre-reloc; 285}; 286 287ð1m1_clkout_pins { 288 u-boot,dm-pre-reloc; 289}; 290 291&pinctrl { 292 u-boot,dm-pre-reloc; 293 status = "okay"; 294}; 295 296&gpio2 { 297 u-boot,dm-pre-reloc; 298}; 299 300&pcfg_pull_none_drv_level_1 { 301 u-boot,dm-pre-reloc; 302}; 303 304&pcfg_pull_none_drv_level_2 { 305 u-boot,dm-pre-reloc; 306}; 307 308&pcfg_pull_none { 309 u-boot,dm-pre-reloc; 310}; 311 312&wdt { 313 u-boot,dm-pre-reloc; 314 status = "okay"; 315}; 316 317&sfc { 318 u-boot,dm-spl; 319 /delete-property/ pinctrl-names; 320 /delete-property/ pinctrl-0; 321 /delete-property/ assigned-clocks; 322 /delete-property/ assigned-clock-rates; 323 status = "okay"; 324 325 #address-cells = <1>; 326 #size-cells = <0>; 327 spi_nand: flash@0 { 328 u-boot,dm-spl; 329 compatible = "spi-nand"; 330 reg = <0>; 331 spi-tx-bus-width = <1>; 332 spi-rx-bus-width = <4>; 333 spi-max-frequency = <96000000>; 334 }; 335}; 336 337&saradc { 338 u-boot,dm-spl; 339 status = "okay"; 340}; 341