1/dts-v1/; 2 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/pwm/pwm.h> 5#include <dt-bindings/input/rk-input.h> 6#include <dt-bindings/display/drm_mipi_dsi.h> 7#include <dt-bindings/display/rockchip_vop.h> 8#include <dt-bindings/display/media-bus-format.h> 9#include "rk3568.dtsi" 10 11/ { 12 model = "Forlinx OK-x-U40 Board"; 13 compatible = "forlinx,ok3568", "rockchip,rk3568-evb1-ddr4-v10", "rockchip,rk3568"; 14 15 forlinx_control { 16 status = "disabled"; 17 video-hdmi = "hdmi"; 18 video-mipi-edp = "mipi"; 19 video-lvds-rgb = "lvds"; 20 }; 21 22 leds: leds { 23 compatible = "gpio-leds"; 24 work_led: work { 25 gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 26 linux,default-trigger = "heartbeat"; 27 }; 28 }; 29 30 /* backlight */ 31 dsi1_backlight: dsi1-backlight { 32 compatible = "pwm-backlight"; 33 pwms = <&pwm14 0 20000 0>; 34 brightness-levels = < 35 0 20 20 21 21 22 22 23 36 23 24 24 25 25 26 26 27 37 27 28 28 29 29 30 30 31 38 31 32 32 33 33 34 34 35 39 35 36 36 37 37 38 38 39 40 40 41 42 43 44 45 46 47 41 48 49 50 51 52 53 54 55 42 56 57 58 59 60 61 62 63 43 64 65 66 67 68 69 70 71 44 72 73 74 75 76 77 78 79 45 80 81 82 83 84 85 86 87 46 88 89 90 91 92 93 94 95 47 96 97 98 99 100 101 102 103 48 104 105 106 107 108 109 110 111 49 112 113 114 115 116 117 118 119 50 120 121 122 123 124 125 126 127 51 128 129 130 131 132 133 134 135 52 136 137 138 139 140 141 142 143 53 144 145 146 147 148 149 150 151 54 152 153 154 155 156 157 158 159 55 160 161 162 163 164 165 166 167 56 168 169 170 171 172 173 174 175 57 176 177 178 179 180 181 182 183 58 184 185 186 187 188 189 190 191 59 192 193 194 195 196 197 198 199 60 200 201 202 203 204 205 206 207 61 208 209 210 211 212 213 214 215 62 216 217 218 219 220 221 222 223 63 224 225 226 227 228 229 230 231 64 232 233 234 235 236 237 238 239 65 240 241 242 243 244 245 246 247 66 248 249 250 251 252 253 254 255 67 >; 68 default-brightness-level = <200>; 69 is-forlinx; 70 }; 71 72 lvds_backlight: lvds-backlight { 73 compatible = "pwm-backlight"; 74 pwms = <&pwm3 0 20000 0>; 75 brightness-levels = < 76 0 20 20 21 21 22 22 23 77 23 24 24 25 25 26 26 27 78 27 28 28 29 29 30 30 31 79 31 32 32 33 33 34 34 35 80 35 36 36 37 37 38 38 39 81 40 41 42 43 44 45 46 47 82 48 49 50 51 52 53 54 55 83 56 57 58 59 60 61 62 63 84 64 65 66 67 68 69 70 71 85 72 73 74 75 76 77 78 79 86 80 81 82 83 84 85 86 87 87 88 89 90 91 92 93 94 95 88 96 97 98 99 100 101 102 103 89 104 105 106 107 108 109 110 111 90 112 113 114 115 116 117 118 119 91 120 121 122 123 124 125 126 127 92 128 129 130 131 132 133 134 135 93 136 137 138 139 140 141 142 143 94 144 145 146 147 148 149 150 151 95 152 153 154 155 156 157 158 159 96 160 161 162 163 164 165 166 167 97 168 169 170 171 172 173 174 175 98 176 177 178 179 180 181 182 183 99 184 185 186 187 188 189 190 191 100 192 193 194 195 196 197 198 199 101 200 201 202 203 204 205 206 207 102 208 209 210 211 212 213 214 215 103 216 217 218 219 220 221 222 223 104 224 225 226 227 228 229 230 231 105 232 233 234 235 236 237 238 239 106 240 241 242 243 244 245 246 247 107 248 249 250 251 252 253 254 255 108 >; 109 default-brightness-level = <200>; 110 is-forlinx; 111 }; 112 113 rgb_backlight: rgb-backlight { 114 compatible = "pwm-backlight"; 115 pwms = <&pwm5 0 20000 0>; 116 brightness-levels = < 117 0 20 20 21 21 22 22 23 118 23 24 24 25 25 26 26 27 119 27 28 28 29 29 30 30 31 120 31 32 32 33 33 34 34 35 121 35 36 36 37 37 38 38 39 122 40 41 42 43 44 45 46 47 123 48 49 50 51 52 53 54 55 124 56 57 58 59 60 61 62 63 125 64 65 66 67 68 69 70 71 126 72 73 74 75 76 77 78 79 127 80 81 82 83 84 85 86 87 128 88 89 90 91 92 93 94 95 129 96 97 98 99 100 101 102 103 130 104 105 106 107 108 109 110 111 131 112 113 114 115 116 117 118 119 132 120 121 122 123 124 125 126 127 133 128 129 130 131 132 133 134 135 134 136 137 138 139 140 141 142 143 135 144 145 146 147 148 149 150 151 136 152 153 154 155 156 157 158 159 137 160 161 162 163 164 165 166 167 138 168 169 170 171 172 173 174 175 139 176 177 178 179 180 181 182 183 140 184 185 186 187 188 189 190 191 141 192 193 194 195 196 197 198 199 142 200 201 202 203 204 205 206 207 143 208 209 210 211 212 213 214 215 144 216 217 218 219 220 221 222 223 145 224 225 226 227 228 229 230 231 146 232 233 234 235 236 237 238 239 147 240 241 242 243 244 245 246 247 148 248 249 250 251 252 253 254 255 149 >; 150 default-brightness-level = <200>; 151 is-forlinx; 152 }; 153 154 edp_backlight: edp-backlight { 155 compatible = "pwm-backlight"; 156 pwms = <&pwm4 0 20000 0>; 157 brightness-levels = < 158 0 20 20 21 21 22 22 23 159 23 24 24 25 25 26 26 27 160 27 28 28 29 29 30 30 31 161 31 32 32 33 33 34 34 35 162 35 36 36 37 37 38 38 39 163 40 41 42 43 44 45 46 47 164 48 49 50 51 52 53 54 55 165 56 57 58 59 60 61 62 63 166 64 65 66 67 68 69 70 71 167 72 73 74 75 76 77 78 79 168 80 81 82 83 84 85 86 87 169 88 89 90 91 92 93 94 95 170 96 97 98 99 100 101 102 103 171 104 105 106 107 108 109 110 111 172 112 113 114 115 116 117 118 119 173 120 121 122 123 124 125 126 127 174 128 129 130 131 132 133 134 135 175 136 137 138 139 140 141 142 143 176 144 145 146 147 148 149 150 151 177 152 153 154 155 156 157 158 159 178 160 161 162 163 164 165 166 167 179 168 169 170 171 172 173 174 175 180 176 177 178 179 180 181 182 183 181 184 185 186 187 188 189 190 191 182 192 193 194 195 196 197 198 199 183 200 201 202 203 204 205 206 207 184 208 209 210 211 212 213 214 215 185 216 217 218 219 220 221 222 223 186 224 225 226 227 228 229 230 231 187 232 233 234 235 236 237 238 239 188 240 241 242 243 244 245 246 247 189 248 249 250 251 252 253 254 255 190 >; 191 default-brightness-level = <200>; 192 }; 193 194 /* panel */ 195 edp-panel { 196 compatible = "simple-panel"; 197 prepare-delay-ms = <120>; 198 enable-delay-ms = <120>; 199 unprepare-delay-ms = <120>; 200 disable-delay-ms = <120>; 201 backlight = <&edp_backlight>; 202 enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; 203 204 port { 205 panel_in_edp: endpoint { 206 remote-endpoint = <&edp_out_panel>; 207 }; 208 }; 209 }; 210 211 lvds-panel { 212 compatible = "simple-panel"; 213 backlight = <&lvds_backlight>; 214 power-supply = <&vcc5v_lvds_en>; 215 enable-delay-ms = <20>; 216 prepare-delay-ms = <20>; 217 unprepare-delay-ms = <20>; 218 disable-delay-ms = <20>; 219 bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>; 220 width-mm = <152>; 221 height-mm = <91>; 222 223 display-timings { 224 native-mode = <&lvds_1280x800>; 225 226 lvds_1280x800: timing0 { 227 clock-frequency = <71000000>; 228 hactive = <1280>; 229 vactive = <800>; 230 hback-porch = <10>; 231 hfront-porch = <140>; 232 hsync-len = <10>; 233 vback-porch = <1>; 234 vfront-porch = <2>; 235 vsync-len = <20>; 236 hsync-active = <0>; 237 vsync-active = <1>; 238 de-active = <1>; 239 pixelclk-active = <0>; 240 }; 241 }; 242 243 ports { 244 #address-cells = <1>; 245 #size-cells = <0>; 246 247 port@0 { 248 reg = <0>; 249 dual-lvds-even-pixels; 250 panel_in_lvds: endpoint { 251 remote-endpoint = <&lvds_out_panel>; 252 }; 253 }; 254 }; 255 }; 256 257 rgb-panel { 258 compatible = "simple-panel"; 259 backlight = <&rgb_backlight>; 260 bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>; 261 enable-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; 262 263 display-timings { 264 native-mode = <&rgb_1024x600>; 265 266 rgb_1024x600: timing0 { 267 clock-frequency = <51200000>; 268 hactive = <1024>; 269 vactive = <600>; 270 hfront-porch = <160>; 271 hback-porch = <320>; 272 hsync-len = <1>; 273 vback-porch = <35>; 274 vfront-porch = <12>; 275 vsync-len = <1>; 276 hsync-active = <0>; 277 vsync-active = <0>; 278 de-active = <1>; 279 pixelclk-active = <1>; 280 }; 281 }; 282 283 ports { 284 #address-cells = <1>; 285 #size-cells = <0>; 286 287 port@0 { 288 reg = <0>; 289 panel_in_rgb: endpoint { 290 remote-endpoint = <&rgb_out_panel>; 291 }; 292 }; 293 294 }; 295 }; 296 297 hdmi_sound: hdmi-sound { 298 status = "okay"; 299 compatible = "rockchip,hdmi"; 300 rockchip,mclk-fs = <128>; 301 rockchip,card-name = "rockchip,hdmi"; 302 rockchip,cpu = <&i2s0_8ch>; 303 rockchip,codec = <&hdmi>; 304 rockchip,jack-det; 305 }; 306 307 pdmics: dummy-codec { 308 status = "disabled"; 309 compatible = "rockchip,dummy-codec"; 310 #sound-dai-cells = <0>; 311 }; 312 313 pdm_mic_array: pdm-mic-array { 314 status = "disabled"; 315 compatible = "simple-audio-card"; 316 simple-audio-card,name = "rockchip,pdm-mic-array"; 317 simple-audio-card,cpu { 318 sound-dai = <&pdm>; 319 }; 320 simple-audio-card,codec { 321 sound-dai = <&pdmics>; 322 }; 323 }; 324 325 audiopwmout_diff: audiopwmout-diff { 326 status = "disabled"; 327 compatible = "simple-audio-card"; 328 simple-audio-card,format = "i2s"; 329 simple-audio-card,name = "rockchip,audiopwmout-diff"; 330 simple-audio-card,mclk-fs = <256>; 331 simple-audio-card,bitclock-master = <&master>; 332 simple-audio-card,frame-master = <&master>; 333 simple-audio-card,cpu { 334 sound-dai = <&i2s3_2ch>; 335 }; 336 master: simple-audio-card,codec { 337 sound-dai = <&dig_acodec>; 338 }; 339 }; 340 341 rk809_sound: rk809-sound { 342 status = "okay"; 343 compatible = "rockchip,multicodecs-card"; 344 rockchip,card-name = "rockchip-rk809"; 345 hp-det-gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; 346 rockchip,format = "i2s"; 347 rockchip,mclk-fs = <256>; 348 rockchip,cpu = <&i2s1_8ch>; 349 rockchip,codec = <&rk809_codec>; 350 pinctrl-names = "default"; 351 pinctrl-0 = <&hp_det>; 352 353 }; 354 355 spdif-sound { 356 status = "disabled"; 357 compatible = "simple-audio-card"; 358 simple-audio-card,name = "ROCKCHIP,SPDIF"; 359 simple-audio-card,cpu { 360 sound-dai = <&spdif_8ch>; 361 }; 362 simple-audio-card,codec { 363 sound-dai = <&spdif_out>; 364 }; 365 }; 366 367 spdif_out: spdif-out { 368 status = "disabled"; 369 compatible = "linux,spdif-dit"; 370 #sound-dai-cells = <0>; 371 }; 372 373 vcc12v: vcc-12v { 374 compatible = "regulator-fixed"; 375 regulator-name = "vcc12v"; 376 regulator-always-on; 377 regulator-boot-on; 378 regulator-min-microvolt = <12000000>; 379 regulator-max-microvolt = <12000000>; 380 }; 381 382 vcc5v0_sys: vcc5v0-sys { 383 compatible = "regulator-fixed"; 384 regulator-name = "vcc5v0_sys"; 385 regulator-always-on; 386 regulator-boot-on; 387 regulator-min-microvolt = <5000000>; 388 regulator-max-microvolt = <5000000>; 389 vin-supply = <&vcc12v>; 390 }; 391 392 vcc3v3_sys: vcc3v3-sys { 393 compatible = "regulator-fixed"; 394 regulator-name = "vcc3v3_sys"; 395 regulator-always-on; 396 regulator-boot-on; 397 regulator-min-microvolt = <3300000>; 398 regulator-max-microvolt = <3300000>; 399 vin-supply = <&vcc5v0_sys>; 400 }; 401 402 //for main board 403 vcc3v3: vcc-3v3 { 404 compatible = "regulator-fixed"; 405 regulator-name = "vcc3v3"; 406 regulator-always-on; 407 regulator-boot-on; 408 regulator-min-microvolt = <3300000>; 409 regulator-max-microvolt = <3300000>; 410 vin-supply = <&vcc5v0_sys>; 411 }; 412 413 vcc1v8: vcc-1v8 { 414 compatible = "regulator-fixed"; 415 regulator-name = "vcc1v8"; 416 regulator-always-on; 417 regulator-boot-on; 418 regulator-min-microvolt = <1800000>; 419 regulator-max-microvolt = <1800000>; 420 vin-supply = <&vcc3v3>; 421 }; 422 423 vcc1v2: vcc-1v2 { 424 compatible = "regulator-fixed"; 425 regulator-name = "vcc1v2"; 426 regulator-always-on; 427 regulator-boot-on; 428 regulator-min-microvolt = <1200000>; 429 regulator-max-microvolt = <1200000>; 430 vin-supply = <&vcc3v3>; 431 }; 432 433 vcc2v8: vcc-2v8 { 434 compatible = "regulator-fixed"; 435 regulator-name = "vcc2v8"; 436 regulator-always-on; 437 regulator-boot-on; 438 regulator-min-microvolt = <2800000>; 439 regulator-max-microvolt = <2800000>; 440 vin-supply = <&vcc3v3>; 441 }; 442 443 vcc5v_lvds_en: vcc5v-lvds-en { 444 compatible = "regulator-fixed"; 445 regulator-name = "vcc5v_lvds_en"; 446 regulator-boot-on; 447 regulator-min-microvolt = <5000000>; 448 regulator-max-microvolt = <5000000>; 449 enable-active-high; 450 gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; 451 vin-supply = <&vcc5v0_sys>; 452 453 regulator-state-mem { 454 regulator-off-in-suspend; 455 }; 456 }; 457 458 vcc3v3_s: vcc-3v3-s { 459 compatible = "regulator-fixed"; 460 regulator-name = "vcc3v3_s"; 461 regulator-always-on; 462 regulator-boot-on; 463 regulator-min-microvolt = <3300000>; 464 regulator-max-microvolt = <3300000>; 465 gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; 466 vin-supply = <&vcc3v3>; 467 }; 468 469 sdio_pwrseq: sdio-pwrseq { 470 compatible = "mmc-pwrseq-simple"; 471 clocks = <&rk809 1>; 472 clock-names = "ext_clock"; 473 474 /* 475 * On the module itself this is one of these (depending 476 * on the actual card populated): 477 * - SDIO_RESET_L_WL_REG_ON 478 * - PDN (power down when low) 479 */ 480 post-power-on-delay-ms = <200>; 481 reset-gpios = <&extio EXTIO_GPIO_P27 GPIO_ACTIVE_LOW>; 482 }; 483 484 vcc2v5_sys: vcc2v5-ddr { 485 compatible = "regulator-fixed"; 486 regulator-name = "vcc2v5-sys"; 487 regulator-always-on; 488 regulator-boot-on; 489 regulator-min-microvolt = <2500000>; 490 regulator-max-microvolt = <2500000>; 491 vin-supply = <&vcc3v3_sys>; 492 }; 493 494 4g-rst { 495 compatible = "regulator-fixed"; 496 regulator-name = "4g-rst"; 497 regulator-min-microvolt = <3300000>; 498 regulator-max-microvolt = <3300000>; 499 gpio = <&extio EXTIO_GPIO_P14 GPIO_ACTIVE_LOW>; 500 enable-active-low; 501 regulator-boot-on; 502 regulator-always-on; 503 status = "okay"; 504 }; 505 506 4g-pwr { 507 compatible = "regulator-fixed"; 508 regulator-name = "4g-pwr"; 509 regulator-min-microvolt = <3300000>; 510 regulator-max-microvolt = <3300000>; 511 gpio = <&extio EXTIO_GPIO_P11 GPIO_ACTIVE_HIGH>; 512 enable-active-high; 513 regulator-boot-on; 514 regulator-always-on; 515 status = "okay"; 516 }; 517 518 debug: debug@fd904000 { 519 compatible = "rockchip,debug"; 520 reg = <0x0 0xfd904000 0x0 0x1000>, 521 <0x0 0xfd905000 0x0 0x1000>, 522 <0x0 0xfd906000 0x0 0x1000>, 523 <0x0 0xfd907000 0x0 0x1000>; 524 }; 525 526 cspmu: cspmu@fd90c000 { 527 compatible = "rockchip,cspmu"; 528 reg = <0x0 0xfd90c000 0x0 0x1000>, 529 <0x0 0xfd90d000 0x0 0x1000>, 530 <0x0 0xfd90e000 0x0 0x1000>, 531 <0x0 0xfd90f000 0x0 0x1000>; 532 }; 533 534 adc_keys: adc-keys { 535 compatible = "adc-keys"; 536 io-channels = <&saradc 0>; 537 io-channel-names = "buttons"; 538 keyup-threshold-microvolt = <1800000>; 539 poll-interval = <100>; 540 541 vol-up-key { 542 label = "volume up"; 543 linux,code = <KEY_VOLUMEUP>; 544 press-threshold-microvolt = <729000>; 545 }; 546 547 vol-down-key { 548 label = "volume down"; 549 linux,code = <KEY_VOLUMEDOWN>; 550 press-threshold-microvolt = <1080000>; 551 }; 552 553 menu-key { 554 label = "menu"; 555 linux,code = <KEY_MENU>; 556 press-threshold-microvolt = <1286000>; 557 }; 558 559 enter-key { 560 label = "enter"; 561 linux,code = <KEY_ENTER>; 562 press-threshold-microvolt = <1409000>; 563 }; 564 565 home-key { 566 label = "home"; 567 linux,code = <KEY_HOME>; 568 press-threshold-microvolt = <1495000>; 569 }; 570 }; 571 572 wakeup-keys { 573 compatible = "gpio-keys"; 574 pinctrl-names = "default"; 575 pinctrl-0 = <&wakeup_keys>; 576 577 wakeup-k6 { 578 label = "wakeup"; 579 linux,code = <KEY_WAKEUP>; 580 gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>; 581 gpio-key,wakeup; 582 }; 583 }; 584 585 fiq-debugger { 586 compatible = "rockchip,fiq-debugger"; 587 rockchip,serial-id = <2>; 588 rockchip,wake-irq = <0>; 589 /* If enable uart uses irq instead of fiq */ 590 rockchip,irq-mode-enable = <1>; 591 rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ 592 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>; 593 pinctrl-names = "default"; 594 pinctrl-0 = <&uart2m0_xfer>; 595 status = "okay"; 596 }; 597 598 ext_cam_clk: external-camera-clock { 599 compatible = "fixed-clock"; 600 clock-frequency = <24000000>; 601 clock-output-names = "CLK_CAMERA_24MHZ"; 602 #clock-cells = <0>; 603 }; 604}; 605 606&reserved_memory { 607 ramoops: ramoops@110000 { 608 compatible = "ramoops"; 609 reg = <0x0 0x110000 0x0 0xf0000>; 610 record-size = <0x20000>; 611 console-size = <0x80000>; 612 ftrace-size = <0x00000>; 613 pmsg-size = <0x50000>; 614 }; 615}; 616 617&rng { 618 status = "okay"; 619}; 620 621&rockchip_suspend { 622 status = "okay"; 623}; 624 625&bus_npu { 626 bus-supply = <&vdd_logic>; 627 pvtm-supply = <&vdd_cpu>; 628 status = "okay"; 629}; 630 631&cpu0 { 632 cpu-supply = <&vdd_cpu>; 633}; 634 635&dfi { 636 status = "okay"; 637}; 638 639&dmc { 640 center-supply = <&vdd_logic>; 641 status = "okay"; 642}; 643 644&gpu { 645 mali-supply = <&vdd_gpu>; 646 status = "okay"; 647}; 648 649&i2c0 { 650 status = "okay"; 651 652 vdd_cpu: tcs4525@1c { 653 compatible = "tcs,tcs452x"; 654 reg = <0x1c>; 655 vin-supply = <&vcc5v0_sys>; 656 regulator-compatible = "fan53555-reg"; 657 regulator-name = "vdd_cpu"; 658 regulator-min-microvolt = <712500>; 659 regulator-max-microvolt = <1390000>; 660 regulator-init-microvolt = <900000>; 661 regulator-ramp-delay = <2300>; 662 fcs,suspend-voltage-selector = <1>; 663 regulator-boot-on; 664 regulator-always-on; 665 regulator-state-mem { 666 regulator-off-in-suspend; 667 }; 668 }; 669 670 rk809: pmic@20 { 671 compatible = "rockchip,rk809"; 672 reg = <0x20>; 673 interrupt-parent = <&gpio0>; 674 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 675 676 pinctrl-names = "default", "pmic-sleep", 677 "pmic-power-off", "pmic-reset"; 678 pinctrl-0 = <&pmic_int>; 679 pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; 680 pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; 681 pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; 682 683 rockchip,system-power-controller; 684 wakeup-source; 685 #clock-cells = <1>; 686 clock-output-names = "rk808-clkout1", "rk808-clkout2"; 687 //fb-inner-reg-idxs = <2>; 688 /* 1: rst regs (default in codes), 0: rst the pmic */ 689 pmic-reset-func = <0>; 690 /* not save the PMIC_POWER_EN register in uboot */ 691 not-save-power-en = <1>; 692 693 vcc1-supply = <&vcc3v3_sys>; 694 vcc2-supply = <&vcc3v3_sys>; 695 vcc3-supply = <&vcc3v3_sys>; 696 vcc4-supply = <&vcc3v3_sys>; 697 vcc5-supply = <&vcc3v3_sys>; 698 vcc6-supply = <&vcc3v3_sys>; 699 vcc7-supply = <&vcc3v3_sys>; 700 vcc8-supply = <&vcc3v3_sys>; 701 vcc9-supply = <&vcc3v3_sys>; 702 703 pwrkey { 704 status = "okay"; 705 }; 706 707 pinctrl_rk8xx: pinctrl_rk8xx { 708 gpio-controller; 709 #gpio-cells = <2>; 710 711 rk817_slppin_null: rk817_slppin_null { 712 pins = "gpio_slp"; 713 function = "pin_fun0"; 714 }; 715 716 rk817_slppin_slp: rk817_slppin_slp { 717 pins = "gpio_slp"; 718 function = "pin_fun1"; 719 }; 720 721 rk817_slppin_pwrdn: rk817_slppin_pwrdn { 722 pins = "gpio_slp"; 723 function = "pin_fun2"; 724 }; 725 726 rk817_slppin_rst: rk817_slppin_rst { 727 pins = "gpio_slp"; 728 function = "pin_fun3"; 729 }; 730 }; 731 732 regulators { 733 vdd_logic: DCDC_REG1 { 734 regulator-always-on; 735 regulator-boot-on; 736 regulator-min-microvolt = <500000>; 737 regulator-max-microvolt = <1350000>; 738 regulator-init-microvolt = <900000>; 739 regulator-ramp-delay = <6001>; 740 regulator-initial-mode = <0x2>; 741 regulator-name = "vdd_logic"; 742 regulator-state-mem { 743 regulator-off-in-suspend; 744 }; 745 }; 746 747 vdd_gpu: DCDC_REG2 { 748 regulator-always-on; 749 regulator-boot-on; 750 regulator-min-microvolt = <500000>; 751 regulator-max-microvolt = <1350000>; 752 regulator-init-microvolt = <900000>; 753 regulator-ramp-delay = <6001>; 754 regulator-initial-mode = <0x2>; 755 regulator-name = "vdd_gpu"; 756 regulator-state-mem { 757 regulator-off-in-suspend; 758 }; 759 }; 760 761 vcc_ddr: DCDC_REG3 { 762 regulator-always-on; 763 regulator-boot-on; 764 regulator-initial-mode = <0x2>; 765 regulator-name = "vcc_ddr"; 766 regulator-state-mem { 767 regulator-on-in-suspend; 768 }; 769 }; 770 771 vdd_npu: DCDC_REG4 { 772 regulator-always-on; 773 regulator-boot-on; 774 regulator-min-microvolt = <500000>; 775 regulator-max-microvolt = <1350000>; 776 regulator-init-microvolt = <900000>; 777 regulator-ramp-delay = <6001>; 778 regulator-initial-mode = <0x2>; 779 regulator-name = "vdd_npu"; 780 regulator-state-mem { 781 regulator-off-in-suspend; 782 }; 783 }; 784 785 vdda0v9_image: LDO_REG1 { 786 regulator-boot-on; 787 regulator-always-on; 788 regulator-min-microvolt = <900000>; 789 regulator-max-microvolt = <900000>; 790 regulator-name = "vdda0v9_image"; 791 regulator-state-mem { 792 regulator-off-in-suspend; 793 }; 794 }; 795 796 vdda_0v9: LDO_REG2 { 797 regulator-always-on; 798 regulator-boot-on; 799 regulator-min-microvolt = <900000>; 800 regulator-max-microvolt = <900000>; 801 regulator-name = "vdda_0v9"; 802 regulator-state-mem { 803 regulator-off-in-suspend; 804 }; 805 }; 806 807 vdda0v9_pmu: LDO_REG3 { 808 regulator-always-on; 809 regulator-boot-on; 810 regulator-min-microvolt = <900000>; 811 regulator-max-microvolt = <900000>; 812 regulator-name = "vdda0v9_pmu"; 813 regulator-state-mem { 814 regulator-on-in-suspend; 815 regulator-suspend-microvolt = <900000>; 816 }; 817 }; 818 819 vccio_acodec: LDO_REG4 { 820 regulator-always-on; 821 regulator-boot-on; 822 regulator-min-microvolt = <3300000>; 823 regulator-max-microvolt = <3300000>; 824 regulator-name = "vccio_acodec"; 825 regulator-state-mem { 826 regulator-off-in-suspend; 827 }; 828 }; 829 830 vccio_sd: LDO_REG5 { 831 regulator-always-on; 832 regulator-boot-on; 833 regulator-min-microvolt = <1800000>; 834 regulator-max-microvolt = <3300000>; 835 regulator-name = "vccio_sd"; 836 regulator-state-mem { 837 regulator-off-in-suspend; 838 }; 839 }; 840 841 vcc3v3_pmu: LDO_REG6 { 842 regulator-always-on; 843 regulator-boot-on; 844 regulator-min-microvolt = <3300000>; 845 regulator-max-microvolt = <3300000>; 846 regulator-name = "vcc3v3_pmu"; 847 regulator-state-mem { 848 regulator-on-in-suspend; 849 regulator-suspend-microvolt = <3300000>; 850 }; 851 }; 852 853 vcca_1v8: LDO_REG7 { 854 regulator-always-on; 855 regulator-boot-on; 856 regulator-min-microvolt = <1800000>; 857 regulator-max-microvolt = <1800000>; 858 regulator-name = "vcca_1v8"; 859 regulator-state-mem { 860 regulator-off-in-suspend; 861 }; 862 }; 863 864 vcca1v8_pmu: LDO_REG8 { 865 regulator-always-on; 866 regulator-boot-on; 867 regulator-min-microvolt = <1800000>; 868 regulator-max-microvolt = <1800000>; 869 regulator-name = "vcca1v8_pmu"; 870 regulator-state-mem { 871 regulator-on-in-suspend; 872 regulator-suspend-microvolt = <1800000>; 873 }; 874 }; 875 876 vcca1v8_image: LDO_REG9 { 877 regulator-always-on; 878 regulator-boot-on; 879 regulator-min-microvolt = <1800000>; 880 regulator-max-microvolt = <1800000>; 881 regulator-name = "vcca1v8_image"; 882 regulator-state-mem { 883 regulator-off-in-suspend; 884 }; 885 }; 886 887 vcc_1v8: DCDC_REG5 { 888 regulator-always-on; 889 regulator-boot-on; 890 regulator-min-microvolt = <1800000>; 891 regulator-max-microvolt = <1800000>; 892 regulator-name = "vcc_1v8"; 893 regulator-state-mem { 894 regulator-off-in-suspend; 895 }; 896 }; 897 898 vcc_3v3: SWITCH_REG1 { 899 regulator-always-on; 900 regulator-boot-on; 901 regulator-name = "vcc_3v3"; 902 regulator-state-mem { 903 regulator-off-in-suspend; 904 }; 905 }; 906 907 vcc3v3_sd: SWITCH_REG2 { 908 regulator-always-on; 909 regulator-boot-on; 910 regulator-name = "vcc3v3_sd"; 911 regulator-state-mem { 912 regulator-off-in-suspend; 913 }; 914 }; 915 }; 916 917 rk809_codec: codec { 918 #sound-dai-cells = <0>; 919 compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; 920 clocks = <&cru I2S1_MCLKOUT>; 921 clock-names = "mclk"; 922 assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; 923 assigned-clock-rates = <12288000>; 924 assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; 925 pinctrl-names = "default"; 926 pinctrl-0 = <&i2s1m0_mclk>; 927 hp-volume = <3>; 928 spk-volume = <3>; 929 mic-in-differential; 930 status = "okay"; 931 }; 932 }; 933}; 934 935&i2s0_8ch { 936 status = "okay"; 937}; 938 939&i2s1_8ch { 940 status = "okay"; 941 rockchip,clk-trcm = <1>; 942 pinctrl-names = "default"; 943 pinctrl-0 = <&i2s1m0_sclktx 944 &i2s1m0_lrcktx 945 &i2s1m0_sdi0 946 &i2s1m0_sdo0>; 947}; 948 949&iep { 950 status = "okay"; 951}; 952 953&iep_mmu { 954 status = "okay"; 955}; 956 957&jpegd { 958 status = "okay"; 959}; 960 961&jpegd_mmu { 962 status = "okay"; 963}; 964 965&mpp_srv { 966 status = "okay"; 967}; 968 969&nandc0 { 970 #address-cells = <1>; 971 #size-cells = <0>; 972 status = "okay"; 973 974 nand@0 { 975 reg = <0>; 976 nand-bus-width = <8>; 977 nand-ecc-mode = "hw"; 978 nand-ecc-strength = <16>; 979 nand-ecc-step-size = <1024>; 980 }; 981}; 982 983 /* 984 * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. 985 * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; 986 * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages 987 * must be consistent with the software configuration correspondingly 988 * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration 989 * should also be configured to 1.8V accordingly; 990 * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration 991 * should also be configured to 3.3V accordingly; 992 * 3/ VCCIO2 voltage control selection (0xFDC20140) 993 * BIT[0]: 0x0: from GPIO_0A7 (default) 994 * BIT[0]: 0x1: from GRF 995 * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: 996 * L:VCCIO2 must supply 3.3V 997 * H:VCCIO2 must supply 1.8V 998 */ 999&pmu_io_domains { 1000 status = "okay"; 1001 pmuio1-supply = <&vcc3v3_pmu>; 1002 pmuio2-supply = <&vcc3v3_pmu>; 1003 vccio1-supply = <&vccio_acodec>; 1004 vccio3-supply = <&vccio_sd>; 1005 vccio4-supply = <&vcc_1v8>; 1006 vccio5-supply = <&vcc_3v3>; 1007 vccio6-supply = <&vcc_1v8>; 1008 vccio7-supply = <&vcc_3v3>; 1009}; 1010 1011&rk_rga { 1012 status = "okay"; 1013}; 1014 1015&rkvdec { 1016 status = "okay"; 1017}; 1018 1019&rkvdec_mmu { 1020 status = "okay"; 1021}; 1022 1023&rkvenc { 1024 venc-supply = <&vdd_logic>; 1025 status = "okay"; 1026}; 1027 1028&rkvenc_mmu { 1029 status = "okay"; 1030}; 1031 1032&rknpu { 1033 rknpu-supply = <&vdd_npu>; 1034 status = "okay"; 1035}; 1036 1037&rknpu_mmu { 1038 status = "okay"; 1039}; 1040 1041&sdhci { 1042 bus-width = <8>; 1043 supports-emmc; 1044 non-removable; 1045 max-frequency = <200000000>; 1046 status = "okay"; 1047}; 1048 1049&sfc { 1050 status = "okay"; 1051 pinctrl-names = "default"; 1052 pinctrl-0 = <&fspi_pins>; 1053 flash: m25p80@0 { 1054 #address-cells = <1>; 1055 #size-cells = <1>; 1056 compatible = "spansion,m25p80", "jedec,spi-nor"; 1057 reg = <0>; 1058 spi-max-frequency = <40000000>; 1059 m25p,fast-read; 1060 }; 1061}; 1062 1063&spdif_8ch { 1064 status = "disabled"; 1065 pinctrl-names = "default"; 1066 pinctrl-0 = <&spdifm1_tx>; 1067}; 1068 1069&tsadc { 1070 status = "okay"; 1071}; 1072 1073&vad { 1074 rockchip,audio-src = <&i2s1_8ch>; 1075 rockchip,buffer-time-ms = <128>; 1076 rockchip,det-channel = <0>; 1077 rockchip,mode = <0>; 1078}; 1079 1080&vdpu { 1081 status = "okay"; 1082}; 1083 1084&vdpu_mmu { 1085 status = "okay"; 1086}; 1087 1088&vepu { 1089 status = "okay"; 1090}; 1091 1092&vepu_mmu { 1093 status = "okay"; 1094}; 1095 1096&xin32k { 1097 status = "disabled"; 1098}; 1099 1100/* TF card */ 1101&sdmmc0 { 1102 max-frequency = <150000000>; 1103 supports-sd; 1104 bus-width = <4>; 1105 cap-mmc-highspeed; 1106 cap-sd-highspeed; 1107 disable-wp; 1108 sd-uhs-sdr104; 1109 vmmc-supply = <&vcc3v3_sd>; 1110 vqmmc-supply = <&vccio_sd>; 1111 pinctrl-names = "default"; 1112 pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; 1113 status = "okay"; 1114}; 1115 1116/* WIFI */ 1117&sdmmc2 { 1118 max-frequency = <150000000>; 1119 supports-sdio; 1120 bus-width = <4>; 1121 disable-wp; 1122 cap-sd-highspeed; 1123 cap-sdio-irq; 1124 keep-power-in-suspend; 1125 mmc-pwrseq = <&sdio_pwrseq>; 1126 non-removable; 1127 pinctrl-names = "default"; 1128 pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; 1129 sd-uhs-sdr104; 1130 status = "okay"; 1131}; 1132 1133&saradc { 1134 status = "okay"; 1135 vref-supply = <&vcca_1v8>; 1136}; 1137 1138/* TTL */ 1139&uart0 { 1140 status = "okay"; 1141}; 1142 1143/* Bluetooth */ 1144&uart8 { 1145 status = "okay"; 1146 pinctrl-names = "default"; 1147 pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>; 1148}; 1149 1150/* 485 */ 1151&uart9 { 1152 status = "okay"; 1153 pinctrl-names = "default"; 1154 pinctrl-0 = <&uart9m1_xfer>; 1155}; 1156 1157&can0 { 1158 assigned-clocks = <&cru CLK_CAN0>; 1159 assigned-clock-rates = <200000000>; 1160 pinctrl-names = "default"; 1161 pinctrl-0 = <&can0m0_pins>; 1162 status = "okay"; 1163}; 1164 1165&can1 { 1166 assigned-clocks = <&cru CLK_CAN1>; 1167 assigned-clock-rates = <200000000>; 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&can1m1_pins>; 1170 status = "okay"; 1171}; 1172 1173&gmac0 { 1174 phy-mode = "rgmii-rxid"; 1175 clock_in_out = "output"; 1176 1177 snps,reset-gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; 1178 snps,reset-active-low; 1179 /* Reset time is 20ms, 100ms for rtl8211f */ 1180 snps,reset-delays-us = <0 20000 100000>; 1181 1182 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>, <&cru CLK_MAC0_OUT>; 1183 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; 1184 assigned-clock-rates = <0>, <125000000>, <25000000>; 1185 1186 pinctrl-names = "default"; 1187 pinctrl-0 = <&gmac0_miim 1188 &gmac0_tx_bus2 1189 &gmac0_rx_bus2 1190 &gmac0_rgmii_clk 1191 &gmac0_rgmii_bus>; 1192 1193 tx_delay = <0x36>; 1194/* rx_delay = <0x00>; */ 1195 1196 phy-handle = <&rgmii_phy0>; 1197 status = "okay"; 1198}; 1199 1200&gmac1 { 1201 phy-mode = "rgmii-rxid"; 1202 clock_in_out = "output"; 1203 1204 snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; 1205 snps,reset-active-low; 1206 /* Reset time is 20ms, 100ms for rtl8211f */ 1207 snps,reset-delays-us = <0 20000 100000>; 1208 1209 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>, <&cru CLK_MAC1_OUT>; 1210 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; 1211 assigned-clock-rates = <0>, <125000000>, <25000000>; 1212 1213 pinctrl-names = "default"; 1214 pinctrl-0 = <&gmac1m1_miim 1215 &gmac1m1_tx_bus2 1216 &gmac1m1_rx_bus2 1217 &gmac1m1_rgmii_clk 1218 &gmac1m1_rgmii_bus>; 1219 1220 tx_delay = <0x47>; 1221/* rx_delay = <0x00>; */ 1222 1223 phy-handle = <&rgmii_phy1>; 1224 status = "okay"; 1225}; 1226 1227&mdio0 { 1228 rgmii_phy0: phy@0 { 1229 compatible = "ethernet-phy-ieee802.3-c22"; 1230 reg = <0x0>; 1231 clocks = <&cru CLK_MAC0_OUT>; 1232 }; 1233}; 1234 1235&mdio1 { 1236 rgmii_phy1: phy@0 { 1237 compatible = "ethernet-phy-ieee802.3-c22"; 1238 reg = <0x0>; 1239 clocks = <&cru CLK_MAC1_OUT>; 1240 }; 1241}; 1242 1243&i2c2 { 1244 pinctrl-0 = <&i2c2m1_xfer>; 1245 status = "okay"; 1246 1247 extio: pcal6524@22 { 1248 compatible = "nxp,pcal6524"; 1249 reg = <0x22>; 1250 interrupt-parent = <&gpio0>; 1251 interrupts = <RK_PA0 IRQ_TYPE_EDGE_FALLING>; 1252 gpio-controller; 1253 pinctrl-0 = <&extio_int_gpio>; 1254 pinctrl-names = "default"; 1255 #gpio-cells = <2>; 1256 interrupt-controller; 1257 #interrupt-cells = <2>; 1258 status = "okay"; 1259 }; 1260 1261 rx8010: rx8010@32 { 1262 compatible = "epson,rx8010"; 1263 reg = <0x32>; 1264 status = "okay"; 1265 }; 1266 1267 pcf8563: pcf8563@51 { 1268 compatible = "nxp,pcf8563"; 1269 reg = <0x51>; 1270 status = "okay"; 1271 }; 1272 1273 gt9xx_rgb: gt9xx-rgb@14 { 1274 compatible = "goodix,gt928"; 1275 reg = <0x14>; 1276 interrupt-parent = <&extio>; 1277 interrupts = <EXTIO_GPIO_P03 IRQ_TYPE_EDGE_FALLING>; 1278 irq-gpio = <&extio EXTIO_GPIO_P03 GPIO_ACTIVE_HIGH>; 1279 reset-gpio = <&extio EXTIO_GPIO_P02 GPIO_ACTIVE_HIGH>; 1280 touchscreen-size-x = <800>; 1281 touchscreen-size-y = <480>; 1282 touchscreen-inverted-x; 1283 touchscreen-inverted-y; 1284 uniq = "rgb"; 1285 status = "okay"; 1286 }; 1287 1288 tsc2007_rgb: tsc2007-rgb@48 { 1289 compatible = "ti,tsc2007"; 1290 reg = <0x48>; 1291 interrupt-parent = <&extio>; 1292 interrupts = <EXTIO_GPIO_P04 IRQ_TYPE_EDGE_FALLING>; 1293 irq-gpio = <&extio EXTIO_GPIO_P04 GPIO_ACTIVE_LOW>; 1294 ti,x-plate-ohms = <180>; 1295 status = "okay"; 1296 }; 1297}; 1298 1299/* usb2 comb phy0 */ 1300&usb2phy0 { 1301 status = "okay"; 1302}; 1303 1304/* usb2 comb phy0 port0 */ 1305&u2phy0_otg { 1306 status = "okay"; 1307}; 1308 1309/* usb2 comb phy0 port1 */ 1310&u2phy0_host { 1311 status = "okay"; 1312}; 1313 1314/* USB 3.0 OTG/SATA Combo PHY_0 */ 1315&combphy0_us { 1316 status = "okay"; 1317}; 1318 1319/* USB 3.0 OTG controller */ 1320&usbdrd30 { 1321 status = "okay"; 1322}; 1323 1324&usbdrd_dwc3 { 1325 extcon = <&usb2phy0>; 1326 status = "okay"; 1327}; 1328 1329/* USB 3.0 Host/SATA/QSGMII Combo PHY_1 */ 1330&combphy1_usq { 1331 status = "okay"; 1332}; 1333 1334/* USB 3.0 Host_1 controller */ 1335&usbhost30 { 1336 status = "okay"; 1337}; 1338 1339&usbhost_dwc3 { 1340 status = "okay"; 1341}; 1342 1343/* usb2 comb phy1 */ 1344&usb2phy1 { 1345 status = "okay"; 1346}; 1347 1348/* usb2 comb phy1 port0 */ 1349&u2phy1_otg { 1350 status = "okay"; 1351}; 1352 1353/* usb2 comb phy1 port1 */ 1354&u2phy1_host { 1355 status = "okay"; 1356}; 1357 1358/* usb2 host2 controller for high speed */ 1359&usb_host0_ehci { 1360 status = "okay"; 1361}; 1362 1363/* usb2 host2 controller for full/low speed */ 1364&usb_host0_ohci { 1365 status = "okay"; 1366}; 1367 1368/* usb2 host3 controller for high speed */ 1369&usb_host1_ehci { 1370 status = "okay"; 1371}; 1372 1373/* usb2 host3 controller for full/low speed */ 1374&usb_host1_ohci { 1375 status = "okay"; 1376}; 1377 1378/* PCIE Gen2 x 1 lane phy */ 1379&combphy2_psq { 1380 status = "okay"; 1381}; 1382 1383&pcie2x1 { 1384 reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; 1385 pinctrl-0 = <&pcie20m0_pins>; 1386 status = "okay"; 1387}; 1388 1389/* PCIE Gen3 x 2 lane phy */ 1390&pcie30phy { 1391 status = "okay"; 1392}; 1393 1394&pcie3x2 { 1395 reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; 1396 pinctrl-0 = <&pcie30x2m0_pins>; 1397 status = "okay"; 1398}; 1399 1400&pinctrl { 1401 wakeup { 1402 wakeup_keys: wakeup-keys { 1403 rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; 1404 }; 1405 }; 1406 1407 extio { 1408 extio_int_gpio: extio-int-gpio { 1409 rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; 1410 }; 1411 1412 extio_rst_gpio: extio-rst-gpio { 1413 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1414 }; 1415 }; 1416 1417 headphone { 1418 hp_det: hp-det { 1419 rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 1420 }; 1421 }; 1422 1423 pmic { 1424 pmic_int: pmic_int { 1425 rockchip,pins = 1426 <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 1427 }; 1428 1429 soc_slppin_gpio: soc_slppin_gpio { 1430 rockchip,pins = 1431 <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>; 1432 }; 1433 1434 soc_slppin_slp: soc_slppin_slp { 1435 rockchip,pins = 1436 <0 RK_PA2 1 &pcfg_pull_up>; 1437 }; 1438 1439 soc_slppin_rst: soc_slppin_rst { 1440 rockchip,pins = 1441 <0 RK_PA2 2 &pcfg_pull_none>; 1442 }; 1443 }; 1444}; 1445 1446/* mipi dsi1 */ 1447&dsi1 { 1448 status = "disabled"; 1449 //rockchip,lane-rate = <1000>; 1450 1451 dsi1-panel { 1452 status = "okay"; 1453 compatible = "simple-panel-dsi"; 1454 reg = <0>; 1455 reset-delay-ms = <60>; 1456 enable-delay-ms = <60>; 1457 prepare-delay-ms = <60>; 1458 unprepare-delay-ms = <60>; 1459 disable-delay-ms = <60>; 1460 dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 1461 MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 1462 dsi,format = <MIPI_DSI_FMT_RGB888>; 1463 dsi,lanes = <4>; 1464 panel-init-sequence = [ 1465 ]; 1466 1467 panel-exit-sequence = [ 1468 ]; 1469 1470 panel-width-mm = <68>; 1471 panel-height-mm = <121>; 1472 backlight = <&dsi1_backlight>; 1473 enable-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; 1474 1475 display-timings { 1476 native-mode = <&dsi1_1024x600>; 1477 1478 dsi1_1024x600: timing0 { 1479 clock-frequency = <45000000>; 1480 hactive = <1024>; 1481 vactive = <600>; 1482 hback-porch = <48>; 1483 hfront-porch = <40>; 1484 hsync-len = <48>; 1485 vback-porch = <48>; 1486 vfront-porch = <40>; 1487 vsync-len = <4>; 1488 hsync-active = <0>; 1489 vsync-active = <0>; 1490 de-active = <0>; 1491 pixelclk-active = <0>; 1492 }; 1493 }; 1494 1495 ports { 1496 #address-cells = <1>; 1497 #size-cells = <0>; 1498 1499 port@0 { 1500 reg = <0>; 1501 panel_in_dsi: endpoint { 1502 remote-endpoint = <&dsi_out_panel>; 1503 }; 1504 }; 1505 }; 1506 }; 1507 1508 ports { 1509 #address-cells = <1>; 1510 #size-cells = <0>; 1511 1512 port@1 { 1513 reg = <1>; 1514 dsi_out_panel: endpoint { 1515 remote-endpoint = <&panel_in_dsi>; 1516 }; 1517 }; 1518 }; 1519 1520}; 1521 1522&dsi1_in_vp0 { 1523 status = "disabled"; 1524}; 1525 1526&dsi1_in_vp1 { 1527 status = "disabled"; 1528}; 1529 1530&route_dsi1 { 1531 status = "disabled"; 1532 connect = <&vp1_out_dsi1>; 1533}; 1534 1535/* edp */ 1536&edp { 1537 status = "disabled"; 1538 pinctrl-names = "default"; 1539 pinctrl-0 = <&edpdpm0_pins>; 1540 1541 ports { 1542 port@1 { 1543 reg = <1>; 1544 edp_out_panel: endpoint { 1545 remote-endpoint = <&panel_in_edp>; 1546 }; 1547 }; 1548 }; 1549}; 1550 1551&edp_phy { 1552 status = "disabled"; 1553}; 1554 1555&edp_in_vp0 { 1556 status = "disabled"; 1557}; 1558 1559&edp_in_vp1 { 1560 status = "disabled"; 1561}; 1562 1563&route_edp { 1564 status = "disabled"; 1565 connect = <&vp1_out_edp>; 1566}; 1567 1568/* lvds */ 1569&lvds { 1570 status = "disabled"; 1571 phys = <&video_phy0>; 1572 phy-names = "phy"; 1573 1574 ports { 1575 port@1 { 1576 reg = <1>; 1577 lvds_out_panel: endpoint { 1578 remote-endpoint = <&panel_in_lvds>; 1579 }; 1580 }; 1581 }; 1582}; 1583 1584&lvds_in_vp1 { 1585 status = "disabled"; 1586}; 1587 1588&lvds_in_vp2 { 1589 status = "disabled"; 1590}; 1591 1592&route_lvds { 1593 status = "disabled"; 1594 connect = <&vp2_out_lvds>; 1595}; 1596 1597/* rgb */ 1598&rgb { 1599 status = "disabled"; 1600 phys = <&video_phy0>; 1601 phy-names = "phy"; 1602 1603 ports { 1604 port@1 { 1605 reg = <1>; 1606 rgb_out_panel: endpoint { 1607 remote-endpoint = <&panel_in_rgb>; 1608 }; 1609 }; 1610 }; 1611}; 1612 1613&rgb_in_vp2 { 1614 status = "disabled"; 1615}; 1616 1617&route_rgb { 1618 status = "disabled"; 1619 connect = <&vp2_out_rgb>; 1620}; 1621 1622/* hdmi */ 1623&hdmi { 1624 status = "disabled"; 1625 rockchip,phy-table = 1626 <92812500 0x8009 0x0000 0x0270>, 1627 <165000000 0x800b 0x0000 0x026d>, 1628 <185625000 0x800b 0x0000 0x01ed>, 1629 <297000000 0x800b 0x0000 0x01ad>, 1630 <594000000 0x8029 0x0000 0x0088>, 1631 <000000000 0x0000 0x0000 0x0000>; 1632}; 1633 1634&hdmi_in_vp0 { 1635 status = "disabled"; 1636}; 1637 1638&hdmi_in_vp1 { 1639 status = "disabled"; 1640}; 1641 1642&route_hdmi { 1643 status = "disabled"; 1644 connect = <&vp0_out_hdmi>; 1645}; 1646 1647/* lvds backlight */ 1648&pwm3 { 1649 status = "okay"; 1650}; 1651 1652/* edp backlight */ 1653&pwm4 { 1654 status = "okay"; 1655}; 1656 1657/* rgb backlight */ 1658&pwm5 { 1659 status = "okay"; 1660}; 1661 1662/* dsi1 backlight */ 1663&pwm14 { 1664 status = "okay"; 1665}; 1666 1667&i2c3 { 1668 status = "okay"; 1669 1670 gt9xx_lvds: gt9xx@5d { 1671 compatible = "goodix,gt928"; 1672 reg = <0x5d>; 1673 interrupt-parent = <&extio>; 1674 interrupts = <EXTIO_GPIO_P00 IRQ_TYPE_EDGE_FALLING>; 1675 irq-gpio = <&extio EXTIO_GPIO_P00 GPIO_ACTIVE_HIGH>; 1676 reset-gpio = <&extio EXTIO_GPIO_P01 GPIO_ACTIVE_HIGH>; 1677 touchscreen-size-x = <1280>; 1678 touchscreen-size-y = <800>; 1679 touchscreen-swapped-x-y; 1680 uniq = "lvds"; 1681 status = "okay"; 1682 }; 1683 1684 cam2_ov5645: cam2_ov5645@3c { 1685 status = "okay"; 1686 compatible = "ovti,ov5645"; 1687 reg = <0x3c>; 1688 clocks = <&ext_cam_clk>; 1689 clock-names = "xclk"; 1690 clock-frequency = <24000000>; 1691 1692 reset-gpios = <&extio EXTIO_GPIO_P17 GPIO_ACTIVE_LOW>; 1693 enable-gpios = <&extio EXTIO_GPIO_P20 GPIO_ACTIVE_HIGH>; 1694 1695 rockchip,camera-module-index = <1>; 1696 rockchip,camera-module-facing = "front"; 1697 rockchip,camera-module-name = "NC"; 1698 rockchip,camera-module-lens-name = "NC"; 1699 port { 1700 cam2_ov5645_out: endpoint { 1701 remote-endpoint = <&mipi_in_ucam2>; 1702 data-lanes = <1 2>; 1703 }; 1704 }; 1705 }; 1706}; 1707 1708&i2c4 { 1709 status = "okay"; 1710 1711 gt9xx_dsi: gt9xx@14 { 1712 compatible = "goodix,gt928"; 1713 reg = <0x14>; 1714 interrupt-parent = <&extio>; 1715 interrupts = <EXTIO_GPIO_P06 IRQ_TYPE_EDGE_FALLING>; 1716 irq-gpio = <&extio EXTIO_GPIO_P06 GPIO_ACTIVE_HIGH>; 1717 reset-gpio = <&extio EXTIO_GPIO_P05 GPIO_ACTIVE_HIGH>; 1718 touchscreen-size-x = <1024>; 1719 touchscreen-size-y = <600>; 1720 uniq = "dsi"; 1721 status = "okay"; 1722 }; 1723 1724 polytouch: edt-ft5x06@38{ 1725 compatible = "edt,edt-ft5406", "edt,edt-ft5x06"; 1726 reg = <0x38>; 1727 interrupt-parent = <&extio>; 1728 interrupts = <EXTIO_GPIO_P06 IRQ_TYPE_EDGE_FALLING>; 1729 irq-gpio = <&extio EXTIO_GPIO_P06 GPIO_ACTIVE_HIGH>; 1730 reset-gpio = <&extio EXTIO_GPIO_P05 GPIO_ACTIVE_HIGH>; 1731 touchscreen-size-x = <1024>; 1732 touchscreen-size-y = <600>; 1733 status = "okay"; 1734 }; 1735 1736 cam1_ov5645: cam1_ov5645@3c { 1737 status = "okay"; 1738 compatible = "ovti,ov5645"; 1739 reg = <0x3c>; 1740 clocks = <&ext_cam_clk>; 1741 clock-names = "xclk"; 1742 clock-frequency = <24000000>; 1743 1744 reset-gpios = <&extio EXTIO_GPIO_P21 GPIO_ACTIVE_LOW>; 1745 enable-gpios = <&extio EXTIO_GPIO_P22 GPIO_ACTIVE_HIGH>; 1746 1747 rockchip,camera-module-index = <0>; 1748 rockchip,camera-module-facing = "front"; 1749 rockchip,camera-module-name = "NC"; 1750 rockchip,camera-module-lens-name = "NC"; 1751 port { 1752 cam1_ov5645_out: endpoint { 1753 remote-endpoint = <&mipi_in_ucam1>; 1754 data-lanes = <1 2>; 1755 }; 1756 }; 1757 }; 1758}; 1759 1760&vop { 1761 status = "okay"; 1762 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; 1763 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>, <&cru PLL_GPLL>; 1764 disable-win-move; 1765}; 1766 1767&vop_mmu { 1768 status = "okay"; 1769}; 1770 1771&vp0 { 1772 cursor-win-id = <ROCKCHIP_VOP2_CLUSTER0>; 1773}; 1774 1775&vp1 { 1776 cursor-win-id = <ROCKCHIP_VOP2_CLUSTER1>; 1777}; 1778 1779&video_phy0 { 1780 status = "okay"; 1781}; 1782 1783&video_phy1 { 1784 status = "okay"; 1785}; 1786 1787&csi2_dphy_hw { 1788 status = "okay"; 1789}; 1790 1791&csi2_dphy1 { 1792 status = "okay"; 1793 1794 ports { 1795 #address-cells = <1>; 1796 #size-cells = <0>; 1797 port@0 { 1798 reg = <0>; 1799 #address-cells = <1>; 1800 #size-cells = <0>; 1801 1802 mipi_in_ucam1: endpoint@1 { 1803 reg = <1>; 1804 remote-endpoint = <&cam1_ov5645_out>; 1805 data-lanes = <1 2>; 1806 }; 1807 }; 1808 port@1 { 1809 reg = <1>; 1810 #address-cells = <1>; 1811 #size-cells = <0>; 1812 1813 csidphy1_out: endpoint@0 { 1814 reg = <0>; 1815 remote-endpoint = <&isp0_in>; 1816 }; 1817 }; 1818 }; 1819}; 1820 1821&rkisp { 1822 status = "okay"; 1823}; 1824 1825&rkisp_mmu { 1826 status = "okay"; 1827}; 1828 1829&rkisp_vir0 { 1830 status = "okay"; 1831 1832 port { 1833 #address-cells = <1>; 1834 #size-cells = <0>; 1835 1836 isp0_in: endpoint@0 { 1837 reg = <0>; 1838 remote-endpoint = <&csidphy1_out>; 1839 }; 1840 }; 1841}; 1842 1843&csi2_dphy2 { 1844 status = "okay"; 1845 ports { 1846 #address-cells = <1>; 1847 #size-cells = <0>; 1848 port@0 { 1849 reg = <0>; 1850 #address-cells = <1>; 1851 #size-cells = <0>; 1852 1853 mipi_in_ucam2: endpoint@1 { 1854 reg = <1>; 1855 remote-endpoint = <&cam2_ov5645_out>; 1856 data-lanes = <1 2>; 1857 }; 1858 }; 1859 port@1 { 1860 reg = <1>; 1861 #address-cells = <1>; 1862 #size-cells = <0>; 1863 1864 csidphy2_out: endpoint@0 { 1865 reg = <0>; 1866 remote-endpoint = <&mipi_csi2_input>; 1867 }; 1868 }; 1869 }; 1870}; 1871 1872&mipi_csi2_hw { 1873 status = "okay"; 1874}; 1875 1876&mipi_csi2 { 1877 status = "okay"; 1878 ports { 1879 #address-cells = <1>; 1880 #size-cells = <0>; 1881 port@0 { 1882 reg = <0>; 1883 #address-cells = <1>; 1884 #size-cells = <0>; 1885 1886 mipi_csi2_input: endpoint@1 { 1887 reg = <1>; 1888 remote-endpoint = <&csidphy2_out>; 1889 data-lanes = <1 2>; 1890 }; 1891 }; 1892 1893 port@1 { 1894 reg = <1>; 1895 #address-cells = <1>; 1896 #size-cells = <0>; 1897 1898 mipi_csi2_output: endpoint@0 { 1899 reg = <0>; 1900 remote-endpoint = <&cif_mipi_in>; 1901 data-lanes = <1 2>; 1902 }; 1903 }; 1904 }; 1905}; 1906 1907&rkcif { 1908 status = "okay"; 1909}; 1910 1911&rkcif_mmu { 1912 status = "okay"; 1913}; 1914 1915&rkcif_mipi_lvds { 1916 status = "okay"; 1917 port { 1918 cif_mipi_in: endpoint { 1919 remote-endpoint = <&mipi_csi2_output>; 1920 data-lanes = <1 2>; 1921 }; 1922 }; 1923}; 1924