1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3568-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/pinctrl/rockchip.h> 10#include <dt-bindings/soc/rockchip,boot-mode.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/power/rk3568-power.h> 13#include <dt-bindings/soc/rockchip-system-status.h> 14#include <dt-bindings/suspend/rockchip-rk3568.h> 15#include <dt-bindings/thermal/thermal.h> 16#include "rk3568-dram-default-timing.dtsi" 17 18/ { 19 compatible = "rockchip,rk3568"; 20 21 interrupt-parent = <&gic>; 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 aliases { 26 csi2dphy0 = &csi2_dphy0; 27 csi2dphy1 = &csi2_dphy1; 28 csi2dphy2 = &csi2_dphy2; 29 dsi0 = &dsi0; 30 dsi1 = &dsi1; 31 ethernet0 = &gmac0; 32 ethernet1 = &gmac1; 33 gpio0 = &gpio0; 34 gpio1 = &gpio1; 35 gpio2 = &gpio2; 36 gpio3 = &gpio3; 37 gpio4 = &gpio4; 38 i2c0 = &i2c0; 39 i2c1 = &i2c1; 40 i2c2 = &i2c2; 41 i2c3 = &i2c3; 42 i2c4 = &i2c4; 43 i2c5 = &i2c5; 44 mmc0 = &sdhci; 45 mmc1 = &sdmmc0; 46 mmc2 = &sdmmc1; 47 mmc3 = &sdmmc2; 48 serial0 = &uart0; 49 serial1 = &uart1; 50 serial2 = &uart2; 51 serial3 = &uart3; 52 serial4 = &uart4; 53 serial5 = &uart5; 54 serial6 = &uart6; 55 serial7 = &uart7; 56 serial8 = &uart8; 57 serial9 = &uart9; 58 spi0 = &spi0; 59 spi1 = &spi1; 60 spi2 = &spi2; 61 spi3 = &spi3; 62 }; 63 64 cpus { 65 #address-cells = <2>; 66 #size-cells = <0>; 67 68 cpu0: cpu@0 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a55"; 71 reg = <0x0 0x0>; 72 enable-method = "psci"; 73 clocks = <&scmi_clk 0>; 74 operating-points-v2 = <&cpu0_opp_table>; 75 cpu-idle-states = <&CPU_SLEEP>; 76 #cooling-cells = <2>; 77 dynamic-power-coefficient = <187>; 78 }; 79 80 cpu1: cpu@100 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a55"; 83 reg = <0x0 0x100>; 84 enable-method = "psci"; 85 clocks = <&scmi_clk 0>; 86 operating-points-v2 = <&cpu0_opp_table>; 87 cpu-idle-states = <&CPU_SLEEP>; 88 }; 89 90 cpu2: cpu@200 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a55"; 93 reg = <0x0 0x200>; 94 enable-method = "psci"; 95 clocks = <&scmi_clk 0>; 96 operating-points-v2 = <&cpu0_opp_table>; 97 cpu-idle-states = <&CPU_SLEEP>; 98 }; 99 100 cpu3: cpu@300 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a55"; 103 reg = <0x0 0x300>; 104 enable-method = "psci"; 105 clocks = <&scmi_clk 0>; 106 operating-points-v2 = <&cpu0_opp_table>; 107 cpu-idle-states = <&CPU_SLEEP>; 108 }; 109 110 idle-states { 111 entry-method = "psci"; 112 CPU_SLEEP: cpu-sleep { 113 compatible = "arm,idle-state"; 114 local-timer-stop; 115 arm,psci-suspend-param = <0x0010000>; 116 entry-latency-us = <100>; 117 exit-latency-us = <120>; 118 min-residency-us = <1000>; 119 }; 120 }; 121 }; 122 123 cpu0_opp_table: cpu0-opp-table { 124 compatible = "operating-points-v2"; 125 opp-shared; 126 127 mbist-vmin = <825000 900000 950000>; 128 nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&cpu_opp_info>; 129 nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info"; 130 rockchip,max-volt = <1150000>; 131 rockchip,pvtm-voltage-sel = < 132 0 84000 0 133 84001 87000 1 134 87001 91000 2 135 91001 100000 3 136 >; 137 rockchip,pvtm-freq = <408000>; 138 rockchip,pvtm-volt = <900000>; 139 rockchip,pvtm-ch = <0 5>; 140 rockchip,pvtm-sample-time = <1000>; 141 rockchip,pvtm-number = <10>; 142 rockchip,pvtm-error = <1000>; 143 rockchip,pvtm-ref-temp = <40>; 144 rockchip,pvtm-temp-prop = <26 26>; 145 rockchip,thermal-zone = "soc-thermal"; 146 rockchip,temp-hysteresis = <5000>; 147 rockchip,low-temp = <0>; 148 rockchip,low-temp-adjust-volt = < 149 /* MHz MHz uV */ 150 0 1992 75000 151 >; 152 153 opp-408000000 { 154 opp-hz = /bits/ 64 <408000000>; 155 opp-microvolt = <850000 850000 1150000>; 156 clock-latency-ns = <40000>; 157 }; 158 opp-600000000 { 159 opp-hz = /bits/ 64 <600000000>; 160 opp-microvolt = <850000 850000 1150000>; 161 clock-latency-ns = <40000>; 162 }; 163 opp-816000000 { 164 opp-hz = /bits/ 64 <816000000>; 165 opp-microvolt = <850000 850000 1150000>; 166 clock-latency-ns = <40000>; 167 opp-suspend; 168 }; 169 opp-1104000000 { 170 opp-hz = /bits/ 64 <1104000000>; 171 opp-microvolt = <900000 900000 1150000>; 172 opp-microvolt-L0 = <900000 900000 1150000>; 173 opp-microvolt-L1 = <850000 850000 1150000>; 174 opp-microvolt-L2 = <850000 850000 1150000>; 175 opp-microvolt-L3 = <850000 850000 1150000>; 176 clock-latency-ns = <40000>; 177 }; 178 opp-1416000000 { 179 opp-hz = /bits/ 64 <1416000000>; 180 opp-microvolt = <1025000 1025000 1150000>; 181 opp-microvolt-L0 = <1025000 1025000 1150000>; 182 opp-microvolt-L1 = <975000 975000 1150000>; 183 opp-microvolt-L2 = <950000 950000 1150000>; 184 opp-microvolt-L3 = <925000 925000 1150000>; 185 clock-latency-ns = <40000>; 186 }; 187 opp-1608000000 { 188 opp-hz = /bits/ 64 <1608000000>; 189 opp-microvolt = <1100000 1100000 1150000>; 190 opp-microvolt-L0 = <1100000 1100000 1150000>; 191 opp-microvolt-L1 = <1050000 1050000 1150000>; 192 opp-microvolt-L2 = <1025000 1025000 1150000>; 193 opp-microvolt-L3 = <1000000 1000000 1150000>; 194 clock-latency-ns = <40000>; 195 }; 196 opp-1800000000 { 197 opp-hz = /bits/ 64 <1800000000>; 198 opp-microvolt = <1150000 1150000 1150000>; 199 opp-microvolt-L0 = <1150000 1150000 1150000>; 200 opp-microvolt-L1 = <1100000 1100000 1150000>; 201 opp-microvolt-L2 = <1075000 1075000 1150000>; 202 opp-microvolt-L3 = <1050000 1050000 1150000>; 203 clock-latency-ns = <40000>; 204 }; 205 opp-1992000000 { 206 opp-hz = /bits/ 64 <1992000000>; 207 opp-microvolt = <1150000 1150000 1150000>; 208 opp-microvolt-L0 = <1150000 1150000 1150000>; 209 opp-microvolt-L1 = <1150000 1150000 1150000>; 210 opp-microvolt-L2 = <1125000 1125000 1150000>; 211 opp-microvolt-L3 = <1100000 1100000 1150000>; 212 clock-latency-ns = <40000>; 213 }; 214 }; 215 216 arm-pmu { 217 compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3"; 218 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 222 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 223 }; 224 225 cpuinfo { 226 compatible = "rockchip,cpuinfo"; 227 nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; 228 nvmem-cell-names = "id", "cpu-version", "cpu-code"; 229 }; 230 231 display_subsystem: display-subsystem { 232 compatible = "rockchip,display-subsystem"; 233 memory-region = <&drm_logo>, <&drm_cubic_lut>; 234 memory-region-names = "drm-logo", "drm-cubic-lut"; 235 ports = <&vop_out>; 236 devfreq = <&dmc>; 237 238 route { 239 route_dsi0: route-dsi0 { 240 status = "disabled"; 241 logo,uboot = "logo.bmp"; 242 logo,kernel = "logo_kernel.bmp"; 243 logo,mode = "center"; 244 charge_logo,mode = "center"; 245 connect = <&vp0_out_dsi0>; 246 }; 247 route_dsi1: route-dsi1 { 248 status = "disabled"; 249 logo,uboot = "logo.bmp"; 250 logo,kernel = "logo_kernel.bmp"; 251 logo,mode = "center"; 252 charge_logo,mode = "center"; 253 connect = <&vp0_out_dsi1>; 254 }; 255 route_edp: route-edp { 256 status = "disabled"; 257 logo,uboot = "logo.bmp"; 258 logo,kernel = "logo_kernel.bmp"; 259 logo,mode = "center"; 260 charge_logo,mode = "center"; 261 connect = <&vp0_out_edp>; 262 }; 263 route_hdmi: route-hdmi { 264 status = "disabled"; 265 logo,uboot = "logo.bmp"; 266 logo,kernel = "logo_kernel.bmp"; 267 logo,mode = "center"; 268 charge_logo,mode = "center"; 269 connect = <&vp1_out_hdmi>; 270 }; 271 route_lvds: route-lvds { 272 status = "disabled"; 273 logo,uboot = "logo.bmp"; 274 logo,kernel = "logo_kernel.bmp"; 275 logo,mode = "center"; 276 charge_logo,mode = "center"; 277 connect = <&vp1_out_lvds>; 278 }; 279 route_rgb: route-rgb { 280 status = "disabled"; 281 logo,uboot = "logo.bmp"; 282 logo,kernel = "logo_kernel.bmp"; 283 logo,mode = "center"; 284 charge_logo,mode = "center"; 285 connect = <&vp2_out_rgb>; 286 }; 287 }; 288 }; 289 290 firmware { 291 scmi: scmi { 292 compatible = "arm,scmi-smc"; 293 shmem = <&scmi_shmem>; 294 arm,smc-id = <0x82000010>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 298 scmi_clk: protocol@14 { 299 reg = <0x14>; 300 #clock-cells = <1>; 301 302 rockchip,clk-init = <1104000000>; 303 }; 304 }; 305 306 sdei: sdei { 307 compatible = "arm,sdei-1.0"; 308 method = "smc"; 309 }; 310 }; 311 312 mipi_csi2: mipi-csi2 { 313 compatible = "rockchip,rk3568-mipi-csi2"; 314 rockchip,hw = <&mipi_csi2_hw>; 315 status = "disabled"; 316 }; 317 318 mpp_srv: mpp-srv { 319 compatible = "rockchip,mpp-service"; 320 rockchip,taskqueue-count = <6>; 321 rockchip,resetgroup-count = <6>; 322 status = "disabled"; 323 }; 324 325 psci { 326 compatible = "arm,psci-1.0"; 327 method = "smc"; 328 }; 329 330 reserved_memory: reserved-memory { 331 #address-cells = <2>; 332 #size-cells = <2>; 333 ranges; 334 335 drm_logo: drm-logo@00000000 { 336 compatible = "rockchip,drm-logo"; 337 reg = <0x0 0x0 0x0 0x0>; 338 }; 339 340 drm_cubic_lut: drm-cubic-lut@00000000 { 341 compatible = "rockchip,drm-cubic-lut"; 342 reg = <0x0 0x0 0x0 0x0>; 343 }; 344 }; 345 346 rockchip_suspend: rockchip-suspend { 347 compatible = "rockchip,pm-rk3568"; 348 status = "disabled"; 349 rockchip,sleep-debug-en = <1>; 350 rockchip,sleep-mode-config = < 351 (0 352 | RKPM_SLP_ARMOFF_LOGOFF 353 | RKPM_SLP_CENTER_OFF 354 | RKPM_SLP_HW_PLLS_OFF 355 | RKPM_SLP_PMUALIVE_32K 356 | RKPM_SLP_OSC_DIS 357 | RKPM_SLP_PMIC_LP 358 | RKPM_SLP_32K_PVTM 359 ) 360 >; 361 rockchip,wakeup-config = < 362 (0 363 | RKPM_GPIO_WKUP_EN 364 ) 365 >; 366 }; 367 368 rockchip_system_monitor: rockchip-system-monitor { 369 compatible = "rockchip,system-monitor"; 370 371 rockchip,thermal-zone = "soc-thermal"; 372 }; 373 374 thermal_zones: thermal-zones { 375 soc_thermal: soc-thermal { 376 polling-delay-passive = <20>; /* milliseconds */ 377 polling-delay = <1000>; /* milliseconds */ 378 sustainable-power = <905>; /* milliwatts */ 379 380 thermal-sensors = <&tsadc 0>; 381 trips { 382 threshold: trip-point-0 { 383 temperature = <75000>; 384 hysteresis = <2000>; 385 type = "passive"; 386 }; 387 target: trip-point-1 { 388 temperature = <85000>; 389 hysteresis = <2000>; 390 type = "passive"; 391 }; 392 soc_crit: soc-crit { 393 /* millicelsius */ 394 temperature = <125000>; 395 /* millicelsius */ 396 hysteresis = <2000>; 397 type = "critical"; 398 }; 399 }; 400 cooling-maps { 401 map0 { 402 trip = <&target>; 403 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 404 contribution = <1024>; 405 }; 406 map1 { 407 trip = <&target>; 408 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 409 contribution = <1024>; 410 }; 411 }; 412 }; 413 414 gpu_thermal: gpu-thermal { 415 polling-delay-passive = <20>; /* milliseconds */ 416 polling-delay = <1000>; /* milliseconds */ 417 418 thermal-sensors = <&tsadc 1>; 419 }; 420 }; 421 422 timer { 423 compatible = "arm,armv8-timer"; 424 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 425 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 426 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 427 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 428 arm,no-tick-in-suspend; 429 }; 430 431 gmac0_clkin: external-gmac0-clock { 432 compatible = "fixed-clock"; 433 clock-frequency = <125000000>; 434 clock-output-names = "gmac0_clkin"; 435 #clock-cells = <0>; 436 }; 437 438 gmac1_clkin: external-gmac1-clock { 439 compatible = "fixed-clock"; 440 clock-frequency = <125000000>; 441 clock-output-names = "gmac1_clkin"; 442 #clock-cells = <0>; 443 }; 444 445 gmac0_xpcsclk: xpcs-gmac0-clock { 446 compatible = "fixed-clock"; 447 clock-frequency = <125000000>; 448 clock-output-names = "clk_gmac0_xpcs_mii"; 449 #clock-cells = <0>; 450 }; 451 452 gmac1_xpcsclk: xpcs-gmac1-clock { 453 compatible = "fixed-clock"; 454 clock-frequency = <125000000>; 455 clock-output-names = "clk_gmac1_xpcs_mii"; 456 #clock-cells = <0>; 457 }; 458 459 i2s1_mclkin_rx: i2s1-mclkin-rx { 460 compatible = "fixed-clock"; 461 #clock-cells = <0>; 462 clock-frequency = <12288000>; 463 clock-output-names = "i2s1_mclkin_rx"; 464 }; 465 466 i2s1_mclkin_tx: i2s1-mclkin-tx { 467 compatible = "fixed-clock"; 468 #clock-cells = <0>; 469 clock-frequency = <12288000>; 470 clock-output-names = "i2s1_mclkin_tx"; 471 }; 472 473 i2s2_mclkin: i2s2-mclkin { 474 compatible = "fixed-clock"; 475 #clock-cells = <0>; 476 clock-frequency = <12288000>; 477 clock-output-names = "i2s2_mclkin"; 478 }; 479 480 i2s3_mclkin: i2s3-mclkin { 481 compatible = "fixed-clock"; 482 #clock-cells = <0>; 483 clock-frequency = <12288000>; 484 clock-output-names = "i2s3_mclkin"; 485 }; 486 487 mpll: mpll { 488 compatible = "fixed-clock"; 489 #clock-cells = <0>; 490 clock-frequency = <800000000>; 491 clock-output-names = "mpll"; 492 }; 493 494 xin24m: xin24m { 495 compatible = "fixed-clock"; 496 #clock-cells = <0>; 497 clock-frequency = <24000000>; 498 clock-output-names = "xin24m"; 499 }; 500 501 xin32k: xin32k { 502 compatible = "fixed-clock"; 503 clock-frequency = <32768>; 504 clock-output-names = "xin32k"; 505 #clock-cells = <0>; 506 pinctrl-names = "default"; 507 pinctrl-0 = <&clk32k_out0>; 508 }; 509 510 scmi_shmem: scmi-shmem@10f000 { 511 compatible = "arm,scmi-shmem"; 512 reg = <0x0 0x0010f000 0x0 0x100>; 513 }; 514 515 sata0: sata@fc000000 { 516 compatible = "snps,dwc-ahci"; 517 reg = <0 0xfc000000 0 0x1000>; 518 clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, 519 <&cru CLK_SATA0_RXOOB>; 520 clock-names = "sata", "pmalive", "rxoob"; 521 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 522 interrupt-names = "hostc"; 523 phys = <&combphy0_us PHY_TYPE_SATA>; 524 phy-names = "sata-phy"; 525 ports-implemented = <0x1>; 526 power-domains = <&power RK3568_PD_PIPE>; 527 status = "disabled"; 528 }; 529 530 sata1: sata@fc400000 { 531 compatible = "snps,dwc-ahci"; 532 reg = <0 0xfc400000 0 0x1000>; 533 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, 534 <&cru CLK_SATA1_RXOOB>; 535 clock-names = "sata", "pmalive", "rxoob"; 536 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 537 interrupt-names = "hostc"; 538 phys = <&combphy1_usq PHY_TYPE_SATA>; 539 phy-names = "sata-phy"; 540 ports-implemented = <0x1>; 541 power-domains = <&power RK3568_PD_PIPE>; 542 status = "disabled"; 543 }; 544 545 sata2: sata@fc800000 { 546 compatible = "snps,dwc-ahci"; 547 reg = <0 0xfc800000 0 0x1000>; 548 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, 549 <&cru CLK_SATA2_RXOOB>; 550 clock-names = "sata", "pmalive", "rxoob"; 551 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 552 interrupt-names = "hostc"; 553 phys = <&combphy2_psq PHY_TYPE_SATA>; 554 phy-names = "sata-phy"; 555 ports-implemented = <0x1>; 556 power-domains = <&power RK3568_PD_PIPE>; 557 status = "disabled"; 558 }; 559 560 usbdrd30: usbdrd { 561 compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3"; 562 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, 563 <&cru ACLK_USB3OTG0>, <&cru PCLK_PIPE>; 564 clock-names = "ref_clk", "suspend_clk", 565 "bus_clk", "pipe_clk"; 566 #address-cells = <2>; 567 #size-cells = <2>; 568 ranges; 569 status = "disabled"; 570 571 usbdrd_dwc3: dwc3@fcc00000 { 572 compatible = "snps,dwc3"; 573 reg = <0x0 0xfcc00000 0x0 0x400000>; 574 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 575 dr_mode = "otg"; 576 phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>; 577 phy-names = "usb2-phy", "usb3-phy"; 578 phy_type = "utmi_wide"; 579 power-domains = <&power RK3568_PD_PIPE>; 580 resets = <&cru SRST_USB3OTG0>; 581 reset-names = "usb3-otg"; 582 snps,dis_enblslpm_quirk; 583 snps,dis-u1-entry-quirk; 584 snps,dis-u2-entry-quirk; 585 snps,dis-u2-freeclk-exists-quirk; 586 snps,dis-del-phy-power-chg-quirk; 587 snps,dis-tx-ipgap-linecheck-quirk; 588 snps,dis_rxdet_inp3_quirk; 589 snps,xhci-trb-ent-quirk; 590 snps,parkmode-disable-ss-quirk; 591 quirk-skip-phy-init; 592 status = "disabled"; 593 }; 594 }; 595 596 usbhost30: usbhost { 597 compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3"; 598 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, 599 <&cru ACLK_USB3OTG1>, <&cru PCLK_PIPE>; 600 clock-names = "ref_clk", "suspend_clk", 601 "bus_clk", "pipe_clk"; 602 #address-cells = <2>; 603 #size-cells = <2>; 604 ranges; 605 status = "disabled"; 606 607 usbhost_dwc3: dwc3@fd000000 { 608 compatible = "snps,dwc3"; 609 reg = <0x0 0xfd000000 0x0 0x400000>; 610 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 611 dr_mode = "host"; 612 phys = <&u2phy0_host>, <&combphy1_usq PHY_TYPE_USB3>; 613 phy-names = "usb2-phy", "usb3-phy"; 614 phy_type = "utmi_wide"; 615 power-domains = <&power RK3568_PD_PIPE>; 616 resets = <&cru SRST_USB3OTG1>; 617 reset-names = "usb3-host"; 618 snps,dis_enblslpm_quirk; 619 snps,dis-u2-freeclk-exists-quirk; 620 snps,dis-del-phy-power-chg-quirk; 621 snps,dis-tx-ipgap-linecheck-quirk; 622 snps,dis_rxdet_inp3_quirk; 623 snps,xhci-trb-ent-quirk; 624 snps,parkmode-disable-ss-quirk; 625 status = "disabled"; 626 }; 627 }; 628 629 gic: interrupt-controller@fd400000 { 630 compatible = "arm,gic-v3"; 631 #interrupt-cells = <3>; 632 #address-cells = <2>; 633 #size-cells = <2>; 634 ranges; 635 interrupt-controller; 636 637 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ 638 <0x0 0xfd460000 0 0xc0000>; /* GICR */ 639 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 640 its: interrupt-controller@fd440000 { 641 compatible = "arm,gic-v3-its"; 642 msi-controller; 643 #msi-cells = <1>; 644 reg = <0x0 0xfd440000 0x0 0x20000>; 645 }; 646 }; 647 648 usb_host0_ehci: usb@fd800000 { 649 compatible = "generic-ehci"; 650 reg = <0x0 0xfd800000 0x0 0x40000>; 651 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 652 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 653 <&cru PCLK_USB>, <&usb2phy1>; 654 clock-names = "usbhost", "arbiter", "pclk", "utmi"; 655 phys = <&u2phy1_otg>; 656 phy-names = "usb2-phy"; 657 status = "disabled"; 658 }; 659 660 usb_host0_ohci: usb@fd840000 { 661 compatible = "generic-ohci"; 662 reg = <0x0 0xfd840000 0x0 0x40000>; 663 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 665 <&cru PCLK_USB>, <&usb2phy1>; 666 clock-names = "usbhost", "arbiter", "pclk", "utmi"; 667 phys = <&u2phy1_otg>; 668 phy-names = "usb2-phy"; 669 status = "disabled"; 670 }; 671 672 usb_host1_ehci: usb@fd880000 { 673 compatible = "generic-ehci"; 674 reg = <0x0 0xfd880000 0x0 0x40000>; 675 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 677 <&cru PCLK_USB>, <&usb2phy1>; 678 clock-names = "usbhost", "arbiter", "pclk", "utmi"; 679 phys = <&u2phy1_host>; 680 phy-names = "usb2-phy"; 681 status = "disabled"; 682 }; 683 684 usb_host1_ohci: usb@fd8c0000 { 685 compatible = "generic-ohci"; 686 reg = <0x0 0xfd8c0000 0x0 0x40000>; 687 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 689 <&cru PCLK_USB>, <&usb2phy1>; 690 clock-names = "usbhost", "arbiter", "pclk", "utmi"; 691 phys = <&u2phy1_host>; 692 phy-names = "usb2-phy"; 693 status = "disabled"; 694 }; 695 696 xpcs: syscon@fda00000 { 697 compatible = "rockchip,rk3568-xpcs", "syscon"; 698 reg = <0x0 0xfda00000 0x0 0x200000>; 699 status = "disabled"; 700 }; 701 702 pmugrf: syscon@fdc20000 { 703 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; 704 reg = <0x0 0xfdc20000 0x0 0x10000>; 705 706 pmu_io_domains: io-domains { 707 compatible = "rockchip,rk3568-pmu-io-voltage-domain"; 708 status = "disabled"; 709 }; 710 711 reboot_mode: reboot-mode { 712 compatible = "syscon-reboot-mode"; 713 offset = <0x200>; 714 mode-bootloader = <BOOT_BL_DOWNLOAD>; 715 mode-charge = <BOOT_CHARGING>; 716 mode-fastboot = <BOOT_FASTBOOT>; 717 mode-loader = <BOOT_BL_DOWNLOAD>; 718 mode-normal = <BOOT_NORMAL>; 719 mode-recovery = <BOOT_RECOVERY>; 720 mode-ums = <BOOT_UMS>; 721 mode-panic = <BOOT_PANIC>; 722 mode-watchdog = <BOOT_WATCHDOG>; 723 }; 724 }; 725 726 pipegrf: syscon@fdc50000 { 727 compatible = "rockchip,rk3568-pipegrf", "syscon"; 728 reg = <0x0 0xfdc50000 0x0 0x1000>; 729 }; 730 731 grf: syscon@fdc60000 { 732 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 733 reg = <0x0 0xfdc60000 0x0 0x10000>; 734 735 io_domains: io-domains { 736 compatible = "rockchip,rk3568-io-voltage-domain"; 737 status = "disabled"; 738 }; 739 740 lvds: lvds { 741 compatible = "rockchip,rk3568-lvds"; 742 phys = <&video_phy0>; 743 phy-names = "phy"; 744 status = "disabled"; 745 746 ports { 747 #address-cells = <1>; 748 #size-cells = <0>; 749 750 port@0 { 751 reg = <0>; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 755 lvds_in_vp1: endpoint@1 { 756 reg = <1>; 757 remote-endpoint = <&vp1_out_lvds>; 758 status = "disabled"; 759 }; 760 761 lvds_in_vp2: endpoint@2 { 762 reg = <2>; 763 remote-endpoint = <&vp2_out_lvds>; 764 status = "disabled"; 765 }; 766 }; 767 }; 768 }; 769 770 rgb: rgb { 771 compatible = "rockchip,rk3568-rgb"; 772 pinctrl-names = "default"; 773 pinctrl-0 = <&lcdc_ctl>; 774 status = "disabled"; 775 776 ports { 777 #address-cells = <1>; 778 #size-cells = <0>; 779 780 port@0 { 781 reg = <0>; 782 #address-cells = <1>; 783 #size-cells = <0>; 784 785 rgb_in_vp2: endpoint@2 { 786 reg = <2>; 787 remote-endpoint = <&vp2_out_rgb>; 788 status = "disabled"; 789 }; 790 }; 791 }; 792 }; 793 794 }; 795 796 pipe_phy_grf0: syscon@fdc70000 { 797 compatible = "rockchip,pipe-phy-grf", "syscon"; 798 reg = <0x0 0xfdc70000 0x0 0x1000>; 799 }; 800 801 pipe_phy_grf1: syscon@fdc80000 { 802 compatible = "rockchip,pipe-phy-grf", "syscon"; 803 reg = <0x0 0xfdc80000 0x0 0x1000>; 804 }; 805 806 pipe_phy_grf2: syscon@fdc90000 { 807 compatible = "rockchip,pipe-phy-grf", "syscon"; 808 reg = <0x0 0xfdc90000 0x0 0x1000>; 809 }; 810 811 usb2phy0_grf: syscon@fdca0000 { 812 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 813 reg = <0x0 0xfdca0000 0x0 0x8000>; 814 }; 815 816 usb2phy1_grf: syscon@fdca8000 { 817 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 818 reg = <0x0 0xfdca8000 0x0 0x8000>; 819 }; 820 821 edp_phy_grf: syscon@fdcb0000 { 822 compatible = "rockchip,rk3568-edp-phy-grf", "syscon", "simple-mfd"; 823 reg = <0x0 0xfdcb0000 0x0 0x100>; 824 clocks = <&cru PCLK_EDPPHY_GRF>; 825 826 edp_phy: edp-phy { 827 compatible = "rockchip,rk3568-edp-phy"; 828 clocks = <&pmucru XIN_OSC0_EDPPHY_G>; 829 clock-names = "refclk"; 830 #phy-cells = <0>; 831 status = "disabled"; 832 }; 833 }; 834 835 pcie30_phy_grf: syscon@fdcb8000 { 836 compatible = "rockchip,pcie30-phy-grf", "syscon"; 837 reg = <0x0 0xfdcb8000 0x0 0x10000>; 838 }; 839 840 sram: sram@fdcc0000 { 841 compatible = "mmio-sram"; 842 reg = <0x0 0xfdcc0000 0x0 0xb000>; 843 844 #address-cells = <1>; 845 #size-cells = <1>; 846 ranges = <0x0 0x0 0xfdcc0000 0xb000>; 847 848 /* start address and size should be 4k algin */ 849 rkvdec_sram: rkvdec-sram@0 { 850 reg = <0x0 0xb000>; 851 }; 852 }; 853 854 pmucru: clock-controller@fdd00000 { 855 compatible = "rockchip,rk3568-pmucru"; 856 reg = <0x0 0xfdd00000 0x0 0x1000>; 857 rockchip,grf = <&grf>; 858 rockchip,pmugrf = <&pmugrf>; 859 #clock-cells = <1>; 860 #reset-cells = <1>; 861 862 assigned-clocks = <&pmucru SCLK_32K_IOE>; 863 assigned-clock-parents = <&pmucru CLK_RTC_32K>; 864 }; 865 866 cru: clock-controller@fdd20000 { 867 compatible = "rockchip,rk3568-cru"; 868 reg = <0x0 0xfdd20000 0x0 0x1000>; 869 rockchip,grf = <&grf>; 870 #clock-cells = <1>; 871 #reset-cells = <1>; 872 873 assigned-clocks = 874 <&pmucru CLK_RTC_32K>, <&cru ACLK_RKVDEC_PRE>, 875 <&cru CLK_RKVDEC_CORE>, <&pmucru PLL_PPLL>, 876 <&pmucru PCLK_PMU>, <&cru PLL_CPLL>, 877 <&cru CPLL_500M>, <&cru CPLL_333M>, 878 <&cru CPLL_250M>, <&cru CPLL_125M>, 879 <&cru CPLL_100M>, <&cru CPLL_62P5M>, 880 <&cru CPLL_50M>, <&cru CPLL_25M>, 881 <&cru PLL_GPLL>, 882 <&cru ACLK_BUS>, <&cru PCLK_BUS>, 883 <&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>, 884 <&cru HCLK_TOP>, <&cru PCLK_TOP>, 885 <&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>, 886 <&cru PLL_NPLL>, <&cru ACLK_PIPE>, 887 <&cru PCLK_PIPE>, <&cru CLK_I2S0_8CH_TX_SRC>, 888 <&cru CLK_I2S0_8CH_RX_SRC>, <&cru CLK_I2S1_8CH_TX_SRC>, 889 <&cru CLK_I2S1_8CH_RX_SRC>, <&cru CLK_I2S2_2CH_SRC>, 890 <&cru CLK_I2S2_2CH_SRC>, <&cru CLK_I2S3_2CH_RX_SRC>, 891 <&cru CLK_I2S3_2CH_TX_SRC>, <&cru MCLK_SPDIF_8CH_SRC>, 892 <&cru ACLK_VOP>; 893 assigned-clock-rates = 894 <32768>, <300000000>, 895 <300000000>, <200000000>, 896 <100000000>, <1000000000>, 897 <500000000>, <333000000>, 898 <250000000>, <125000000>, 899 <100000000>, <62500000>, 900 <50000000>, <25000000>, 901 <1188000000>, 902 <150000000>, <100000000>, 903 <500000000>, <400000000>, 904 <150000000>, <100000000>, 905 <300000000>, <150000000>, 906 <1200000000>, <400000000>, 907 <100000000>, <1188000000>, 908 <1188000000>, <1188000000>, 909 <1188000000>, <1188000000>, 910 <1188000000>, <1188000000>, 911 <1188000000>, <1188000000>, 912 <500000000>; 913 assigned-clock-parents = 914 <&pmucru CLK_RTC32K_FRAC>, <&cru PLL_GPLL>, 915 <&cru PLL_GPLL>; 916 }; 917 918 i2c0: i2c@fdd40000 { 919 compatible = "rockchip,rk3399-i2c"; 920 reg = <0x0 0xfdd40000 0x0 0x1000>; 921 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 922 clock-names = "i2c", "pclk"; 923 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 924 pinctrl-names = "default"; 925 pinctrl-0 = <&i2c0_xfer>; 926 #address-cells = <1>; 927 #size-cells = <0>; 928 status = "disabled"; 929 }; 930 931 uart0: serial@fdd50000 { 932 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 933 reg = <0x0 0xfdd50000 0x0 0x100>; 934 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; 936 clock-names = "baudclk", "apb_pclk"; 937 reg-shift = <2>; 938 reg-io-width = <4>; 939 dmas = <&dmac0 0>, <&dmac0 1>; 940 pinctrl-names = "default"; 941 pinctrl-0 = <&uart0_xfer>; 942 status = "disabled"; 943 }; 944 945 pwm0: pwm@fdd70000 { 946 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 947 reg = <0x0 0xfdd70000 0x0 0x10>; 948 #pwm-cells = <3>; 949 pinctrl-names = "active"; 950 pinctrl-0 = <&pwm0m0_pins>; 951 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 952 clock-names = "pwm", "pclk"; 953 status = "disabled"; 954 }; 955 956 pwm1: pwm@fdd70010 { 957 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 958 reg = <0x0 0xfdd70010 0x0 0x10>; 959 #pwm-cells = <3>; 960 pinctrl-names = "active"; 961 pinctrl-0 = <&pwm1m0_pins>; 962 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 963 clock-names = "pwm", "pclk"; 964 status = "disabled"; 965 }; 966 967 pwm2: pwm@fdd70020 { 968 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 969 reg = <0x0 0xfdd70020 0x0 0x10>; 970 #pwm-cells = <3>; 971 pinctrl-names = "active"; 972 pinctrl-0 = <&pwm2m0_pins>; 973 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 974 clock-names = "pwm", "pclk"; 975 status = "disabled"; 976 }; 977 978 pwm3: pwm@fdd70030 { 979 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 980 reg = <0x0 0xfdd70030 0x0 0x10>; 981 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 983 #pwm-cells = <3>; 984 pinctrl-names = "active"; 985 pinctrl-0 = <&pwm3_pins>; 986 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 987 clock-names = "pwm", "pclk"; 988 status = "disabled"; 989 }; 990 991 pmu: power-management@fdd90000 { 992 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; 993 reg = <0x0 0xfdd90000 0x0 0x1000>; 994 995 power: power-controller { 996 compatible = "rockchip,rk3568-power-controller"; 997 #power-domain-cells = <1>; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 status = "okay"; 1001 1002 /* These power domains are grouped by VD_NPU */ 1003 pd_npu@RK3568_PD_NPU { 1004 reg = <RK3568_PD_NPU>; 1005 clocks = <&cru ACLK_NPU_PRE>, 1006 <&cru HCLK_NPU_PRE>, 1007 <&cru PCLK_NPU_PRE>; 1008 pm_qos = <&qos_npu>; 1009 }; 1010 /* These power domains are grouped by VD_GPU */ 1011 pd_gpu@RK3568_PD_GPU { 1012 reg = <RK3568_PD_GPU>; 1013 clocks = <&cru ACLK_GPU_PRE>, 1014 <&cru PCLK_GPU_PRE>; 1015 pm_qos = <&qos_gpu>; 1016 }; 1017 /* These power domains are grouped by VD_LOGIC */ 1018 pd_vi@RK3568_PD_VI { 1019 reg = <RK3568_PD_VI>; 1020 clocks = <&cru HCLK_VI>, 1021 <&cru PCLK_VI>; 1022 pm_qos = <&qos_isp>, 1023 <&qos_vicap0>, 1024 <&qos_vicap1>; 1025 }; 1026 pd_vo@RK3568_PD_VO { 1027 reg = <RK3568_PD_VO>; 1028 clocks = <&cru HCLK_VO>, 1029 <&cru PCLK_VO>, 1030 <&cru ACLK_VOP_PRE>; 1031 pm_qos = <&qos_hdcp>, 1032 <&qos_vop_m0>, 1033 <&qos_vop_m1>; 1034 }; 1035 pd_rga@RK3568_PD_RGA { 1036 reg = <RK3568_PD_RGA>; 1037 clocks = <&cru HCLK_RGA_PRE>, 1038 <&cru PCLK_RGA_PRE>; 1039 pm_qos = <&qos_ebc>, 1040 <&qos_iep>, 1041 <&qos_jpeg_dec>, 1042 <&qos_jpeg_enc>, 1043 <&qos_rga_rd>, 1044 <&qos_rga_wr>; 1045 }; 1046 pd_vpu@RK3568_PD_VPU { 1047 reg = <RK3568_PD_VPU>; 1048 clocks = <&cru HCLK_VPU_PRE>; 1049 pm_qos = <&qos_vpu>; 1050 }; 1051 pd_rkvdec@RK3568_PD_RKVDEC { 1052 clocks = <&cru HCLK_RKVDEC_PRE>; 1053 reg = <RK3568_PD_RKVDEC>; 1054 pm_qos = <&qos_rkvdec>; 1055 }; 1056 pd_rkvenc@RK3568_PD_RKVENC { 1057 reg = <RK3568_PD_RKVENC>; 1058 clocks = <&cru HCLK_RKVENC_PRE>; 1059 pm_qos = <&qos_rkvenc_rd_m0>, 1060 <&qos_rkvenc_rd_m1>, 1061 <&qos_rkvenc_wr_m0>; 1062 }; 1063 pd_pipe@RK3568_PD_PIPE { 1064 reg = <RK3568_PD_PIPE>; 1065 clocks = <&cru PCLK_PIPE>; 1066 pm_qos = <&qos_pcie2x1>, 1067 <&qos_pcie3x1>, 1068 <&qos_pcie3x2>, 1069 <&qos_sata0>, 1070 <&qos_sata1>, 1071 <&qos_sata2>, 1072 <&qos_usb3_0>, 1073 <&qos_usb3_1>; 1074 }; 1075 }; 1076 }; 1077 1078 pvtm@fde00000 { 1079 compatible = "rockchip,rk3568-core-pvtm"; 1080 reg = <0x0 0xfde00000 0x0 0x100>; 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 pvtm@0 { 1084 reg = <0>; 1085 clocks = <&cru CLK_CORE_PVTM>, <&cru PCLK_CORE_PVTM>; 1086 clock-names = "clk", "pclk"; 1087 resets = <&cru SRST_CORE_PVTM>, <&cru SRST_P_CORE_PVTM>; 1088 reset-names = "rts", "rst-p"; 1089 thermal-zone = "soc-thermal"; 1090 }; 1091 }; 1092 1093 rknpu: npu@fde40000 { 1094 compatible = "rockchip,rk3568-rknpu", "rockchip,rknpu"; 1095 reg = <0x0 0xfde40000 0x0 0x10000>; 1096 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 1097 clocks = <&scmi_clk 2>, <&cru CLK_NPU>, <&cru ACLK_NPU>, <&cru HCLK_NPU>; 1098 clock-names = "scmi_clk", "clk", "aclk", "hclk"; 1099 assigned-clocks = <&cru CLK_NPU>; 1100 assigned-clock-rates = <600000000>; 1101 resets = <&cru SRST_A_NPU>, <&cru SRST_H_NPU>; 1102 reset-names = "srst_a", "srst_h"; 1103 power-domains = <&power RK3568_PD_NPU>; 1104 operating-points-v2 = <&npu_opp_table>; 1105 iommus = <&rknpu_mmu>; 1106 status = "disabled"; 1107 }; 1108 1109 npu_opp_table: npu-opp-table { 1110 compatible = "operating-points-v2"; 1111 1112 mbist-vmin = <825000 900000 950000>; 1113 nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&npu_opp_info>; 1114 nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info"; 1115 rockchip,max-volt = <1000000>; 1116 rockchip,temp-hysteresis = <5000>; 1117 rockchip,low-temp = <0>; 1118 rockchip,low-temp-adjust-volt = < 1119 /* MHz MHz uV */ 1120 0 1000 50000 1121 >; 1122 rockchip,pvtm-voltage-sel = < 1123 0 84000 0 1124 84001 87000 1 1125 87001 91000 2 1126 91001 100000 3 1127 >; 1128 rockchip,pvtm-ch = <0 5>; 1129 1130 opp-200000000 { 1131 opp-hz = /bits/ 64 <200000000>; 1132 opp-microvolt = <850000 850000 1000000>; 1133 }; 1134 opp-300000000 { 1135 opp-hz = /bits/ 64 <297000000>; 1136 opp-microvolt = <850000 850000 1000000>; 1137 }; 1138 opp-400000000 { 1139 opp-hz = /bits/ 64 <400000000>; 1140 opp-microvolt = <850000 850000 1000000>; 1141 }; 1142 opp-600000000 { 1143 opp-hz = /bits/ 64 <600000000>; 1144 opp-microvolt = <850000 850000 1000000>; 1145 }; 1146 opp-700000000 { 1147 opp-hz = /bits/ 64 <700000000>; 1148 opp-microvolt = <875000 875000 1000000>; 1149 opp-microvolt-L0 = <875000 875000 1000000>; 1150 opp-microvolt-L1 = <850000 850000 1000000>; 1151 opp-microvolt-L2 = <850000 850000 1000000>; 1152 opp-microvolt-L3 = <850000 850000 1000000>; 1153 }; 1154 opp-800000000 { 1155 opp-hz = /bits/ 64 <800000000>; 1156 opp-microvolt = <925000 925000 1000000>; 1157 opp-microvolt-L0 = <925000 925000 1000000>; 1158 opp-microvolt-L1 = <900000 900000 1000000>; 1159 opp-microvolt-L2 = <875000 875000 1000000>; 1160 opp-microvolt-L3 = <875000 875000 1000000>; 1161 }; 1162 opp-900000000 { 1163 opp-hz = /bits/ 64 <900000000>; 1164 opp-microvolt = <975000 975000 1000000>; 1165 opp-microvolt-L0 = <975000 975000 1000000>; 1166 opp-microvolt-L1 = <950000 950000 1000000>; 1167 opp-microvolt-L2 = <925000 925000 1000000>; 1168 opp-microvolt-L3 = <900000 900000 1000000>; 1169 }; 1170 opp-1000000000 { 1171 opp-hz = /bits/ 64 <1000000000>; 1172 opp-microvolt = <1000000 1000000 1000000>; 1173 opp-microvolt-L0 = <1000000 1000000 1000000>; 1174 opp-microvolt-L1 = <975000 975000 1000000>; 1175 opp-microvolt-L2 = <950000 950000 1000000>; 1176 opp-microvolt-L3 = <925000 925000 1000000>; 1177 status = "disabled"; 1178 }; 1179 }; 1180 1181 bus_npu: bus-npu { 1182 compatible = "rockchip,rk3568-bus"; 1183 rockchip,busfreq-policy = "clkfreq"; 1184 clocks = <&scmi_clk 2>; 1185 clock-names = "bus"; 1186 operating-points-v2 = <&bus_npu_opp_table>; 1187 status = "disabled"; 1188 }; 1189 1190 bus_npu_opp_table: bus-npu-opp-table { 1191 compatible = "operating-points-v2"; 1192 opp-shared; 1193 1194 nvmem-cells = <&core_pvtm>; 1195 nvmem-cell-names = "pvtm"; 1196 rockchip,pvtm-voltage-sel = < 1197 0 84000 0 1198 84001 91000 1 1199 91001 100000 2 1200 >; 1201 rockchip,pvtm-ch = <0 5>; 1202 1203 opp-700000000 { 1204 opp-hz = /bits/ 64 <700000000>; 1205 opp-microvolt = <900000>; 1206 opp-microvolt-L0 = <900000>; 1207 opp-microvolt-L1 = <875000>; 1208 opp-microvolt-L2 = <875000>; 1209 }; 1210 opp-900000000 { 1211 opp-hz = /bits/ 64 <900000000>; 1212 opp-microvolt = <900000>; 1213 }; 1214 opp-1000000000 { 1215 opp-hz = /bits/ 64 <1000000000>; 1216 opp-microvolt = <950000>; 1217 opp-microvolt-L0 = <950000>; 1218 opp-microvolt-L1 = <925000>; 1219 opp-microvolt-L2 = <900000>; 1220 }; 1221 }; 1222 1223 rknpu_mmu: iommu@fde4b000 { 1224 compatible = "rockchip,iommu-v2"; 1225 reg = <0x0 0xfde4b000 0x0 0x40>; 1226 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 1227 interrupt-names = "rknpu_mmu"; 1228 clocks = <&cru ACLK_NPU>, <&cru HCLK_NPU>; 1229 clock-names = "aclk", "iface"; 1230 power-domains = <&power RK3568_PD_NPU>; 1231 #iommu-cells = <0>; 1232 status = "disabled"; 1233 }; 1234 1235 gpu: gpu@fde60000 { 1236 compatible = "arm,mali-bifrost"; 1237 reg = <0x0 0xfde60000 0x0 0x4000>; 1238 1239 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1242 interrupt-names = "GPU", "MMU", "JOB"; 1243 1244 upthreshold = <40>; 1245 downdifferential = <10>; 1246 1247 clocks = <&scmi_clk 1>, <&cru CLK_GPU>; 1248 clock-names = "clk_mali", "clk_gpu"; 1249 power-domains = <&power RK3568_PD_GPU>; 1250 #cooling-cells = <2>; 1251 operating-points-v2 = <&gpu_opp_table>; 1252 1253 status = "disabled"; 1254 gpu_power_model: power-model { 1255 compatible = "simple-power-model"; 1256 leakage-range= <5 15>; 1257 ls = <(-24002) 22823 0>; 1258 static-coefficient = <100000>; 1259 dynamic-coefficient = <953>; 1260 ts = <(-108890) 63610 (-1355) 20>; 1261 thermal-zone = "gpu-thermal"; 1262 }; 1263 }; 1264 1265 gpu_opp_table: opp-table2 { 1266 compatible = "operating-points-v2"; 1267 1268 mbist-vmin = <825000 900000 950000>; 1269 nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&gpu_opp_info>; 1270 nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info"; 1271 rockchip,max-volt = <1000000>; 1272 rockchip,temp-hysteresis = <5000>; 1273 rockchip,low-temp = <0>; 1274 rockchip,low-temp-adjust-volt = < 1275 /* MHz MHz uV */ 1276 0 800 50000 1277 >; 1278 rockchip,pvtm-voltage-sel = < 1279 0 84000 0 1280 84001 87000 1 1281 87001 91000 2 1282 91001 100000 3 1283 >; 1284 rockchip,pvtm-ch = <0 5>; 1285 1286 opp-200000000 { 1287 opp-hz = /bits/ 64 <200000000>; 1288 opp-microvolt = <850000 850000 1000000>; 1289 }; 1290 opp-300000000 { 1291 opp-hz = /bits/ 64 <300000000>; 1292 opp-microvolt = <850000 850000 1000000>; 1293 }; 1294 opp-400000000 { 1295 opp-hz = /bits/ 64 <400000000>; 1296 opp-microvolt = <850000 850000 1000000>; 1297 }; 1298 opp-600000000 { 1299 opp-hz = /bits/ 64 <600000000>; 1300 opp-microvolt = <900000 900000 1000000>; 1301 opp-microvolt-L0 = <900000 900000 1000000>; 1302 opp-microvolt-L1 = <875000 875000 1000000>; 1303 opp-microvolt-L2 = <850000 850000 1000000>; 1304 opp-microvolt-L3 = <850000 850000 1000000>; 1305 }; 1306 opp-700000000 { 1307 opp-hz = /bits/ 64 <700000000>; 1308 opp-microvolt = <950000 950000 1000000>; 1309 opp-microvolt-L0 = <950000 950000 1000000>; 1310 opp-microvolt-L1 = <925000 925000 1000000>; 1311 opp-microvolt-L2 = <900000 900000 1000000>; 1312 opp-microvolt-L3 = <875000 875000 1000000>; 1313 }; 1314 opp-800000000 { 1315 opp-hz = /bits/ 64 <800000000>; 1316 opp-microvolt = <1000000 1000000 1000000>; 1317 opp-microvolt-L0 = <1000000 1000000 1000000>; 1318 opp-microvolt-L1 = <975000 975000 1000000>; 1319 opp-microvolt-L2 = <950000 950000 1000000>; 1320 opp-microvolt-L3 = <925000 925000 1000000>; 1321 }; 1322 }; 1323 1324 pvtm@fde80000 { 1325 compatible = "rockchip,rk3568-gpu-pvtm"; 1326 reg = <0x0 0xfde80000 0x0 0x100>; 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 pvtm@1 { 1330 reg = <1>; 1331 clocks = <&cru CLK_GPU_PVTM>, <&cru PCLK_GPU_PVTM>; 1332 clock-names = "clk", "pclk"; 1333 resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>; 1334 reset-names = "rts", "rst-p"; 1335 thermal-zone = "gpu-thermal"; 1336 }; 1337 }; 1338 1339 pvtm@fde90000 { 1340 compatible = "rockchip,rk3568-npu-pvtm"; 1341 reg = <0x0 0xfde90000 0x0 0x100>; 1342 #address-cells = <1>; 1343 #size-cells = <0>; 1344 pvtm@2 { 1345 reg = <2>; 1346 clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>, 1347 <&cru HCLK_NPU_PRE>; 1348 clock-names = "clk", "pclk", "hclk"; 1349 resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>; 1350 reset-names = "rts", "rst-p"; 1351 thermal-zone = "soc-thermal"; 1352 }; 1353 }; 1354 1355 vdpu: vdpu@fdea0400 { 1356 compatible = "rockchip,vpu-decoder-v2"; 1357 reg = <0x0 0xfdea0400 0x0 0x400>; 1358 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 1359 interrupt-names = "irq_dec"; 1360 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1361 clock-names = "aclk_vcodec", "hclk_vcodec"; 1362 resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>; 1363 reset-names = "video_a", "video_h"; 1364 iommus = <&vdpu_mmu>; 1365 power-domains = <&power RK3568_PD_VPU>; 1366 rockchip,srv = <&mpp_srv>; 1367 rockchip,taskqueue-node = <0>; 1368 rockchip,resetgroup-node = <0>; 1369 status = "disabled"; 1370 }; 1371 1372 vdpu_mmu: iommu@fdea0800 { 1373 compatible = "rockchip,iommu-v2"; 1374 reg = <0x0 0xfdea0800 0x0 0x40>; 1375 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1376 interrupt-names = "vdpu_mmu"; 1377 clock-names = "aclk", "iface"; 1378 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1379 power-domains = <&power RK3568_PD_VPU>; 1380 #iommu-cells = <0>; 1381 status = "disabled"; 1382 }; 1383 1384 rk_rga: rk_rga@fdeb0000 { 1385 compatible = "rockchip,rga2"; 1386 reg = <0x0 0xfdeb0000 0x0 0x1000>; 1387 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1388 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; 1389 clock-names = "aclk_rga", "hclk_rga", "clk_rga"; 1390 power-domains = <&power RK3568_PD_RGA>; 1391 status = "disabled"; 1392 }; 1393 1394 ebc: ebc@fdec0000 { 1395 compatible = "rockchip,rk3568-ebc-tcon"; 1396 reg = <0x0 0xfdec0000 0x0 0x5000>; 1397 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1398 clocks = <&cru HCLK_EBC>, <&cru DCLK_EBC>; 1399 clock-names = "hclk", "dclk"; 1400 power-domains = <&power RK3568_PD_RGA>; 1401 rockchip,grf = <&grf>; 1402 pinctrl-names = "default"; 1403 pinctrl-0 = <&ebc_pins>; 1404 status = "disabled"; 1405 }; 1406 1407 jpegd: jpegd@fded0000 { 1408 compatible = "rockchip,rkv-jpeg-decoder-v1"; 1409 reg = <0x0 0xfded0000 0x0 0x400>; 1410 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1411 clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>; 1412 clock-names = "aclk_vcodec", "hclk_vcodec"; 1413 rockchip,disable-auto-freq; 1414 resets = <&cru SRST_A_JDEC>, <&cru SRST_H_JDEC>; 1415 reset-names = "video_a", "video_h"; 1416 iommus = <&jpegd_mmu>; 1417 rockchip,srv = <&mpp_srv>; 1418 rockchip,taskqueue-node = <1>; 1419 rockchip,resetgroup-node = <1>; 1420 power-domains = <&power RK3568_PD_RGA>; 1421 status = "disabled"; 1422 }; 1423 1424 jpegd_mmu: iommu@fded0480 { 1425 compatible = "rockchip,iommu-v2"; 1426 reg = <0x0 0xfded0480 0x0 0x40>; 1427 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1428 interrupt-names = "jpegd_mmu"; 1429 clock-names = "aclk", "iface"; 1430 clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>; 1431 power-domains = <&power RK3568_PD_RGA>; 1432 #iommu-cells = <0>; 1433 status = "disabled"; 1434 }; 1435 1436 vepu: vepu@fdee0000 { 1437 compatible = "rockchip,vpu-encoder-v2"; 1438 reg = <0x0 0xfdee0000 0x0 0x400>; 1439 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1440 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 1441 clock-names = "aclk_vcodec", "hclk_vcodec"; 1442 rockchip,disable-auto-freq; 1443 resets = <&cru SRST_A_JENC>, <&cru SRST_H_JENC>; 1444 reset-names = "video_a", "video_h"; 1445 iommus = <&vepu_mmu>; 1446 rockchip,srv = <&mpp_srv>; 1447 rockchip,taskqueue-node = <2>; 1448 rockchip,resetgroup-node = <2>; 1449 power-domains = <&power RK3568_PD_RGA>; 1450 status = "disabled"; 1451 }; 1452 1453 vepu_mmu: iommu@fdee0800 { 1454 compatible = "rockchip,iommu-v2"; 1455 reg = <0x0 0xfdee0800 0x0 0x40>; 1456 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1457 interrupt-names = "vepu_mmu"; 1458 clock-names = "aclk", "iface"; 1459 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 1460 power-domains = <&power RK3568_PD_RGA>; 1461 #iommu-cells = <0>; 1462 status = "disabled"; 1463 }; 1464 1465 iep: iep@fdef0000 { 1466 compatible = "rockchip,iep-v2"; 1467 reg = <0x0 0xfdef0000 0x0 0x500>; 1468 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1469 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>, <&cru CLK_IEP_CORE>; 1470 clock-names = "aclk", "hclk", "sclk"; 1471 resets = <&cru SRST_A_IEP>, <&cru SRST_H_IEP>, 1472 <&cru SRST_IEP_CORE>; 1473 reset-names = "rst_a", "rst_h", "rst_s"; 1474 power-domains = <&power RK3568_PD_RGA>; 1475 rockchip,srv = <&mpp_srv>; 1476 rockchip,taskqueue-node = <5>; 1477 rockchip,resetgroup-node = <5>; 1478 iommus = <&iep_mmu>; 1479 status = "disabled"; 1480 }; 1481 1482 iep_mmu: iommu@fdef0800 { 1483 compatible = "rockchip,iommu-v2"; 1484 reg = <0x0 0xfdef0800 0x0 0x100>; 1485 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1486 interrupt-names = "iep_mmu"; 1487 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1488 clock-names = "aclk", "iface"; 1489 #iommu-cells = <0>; 1490 power-domains = <&power RK3568_PD_RGA>; 1491 //rockchip,disable-device-link-resume; 1492 status = "disabled"; 1493 }; 1494 1495 eink: eink@fdf00000 { 1496 compatible = "rockchip,rk3568-eink-tcon"; 1497 reg = <0x0 0xfdf00000 0x0 0x74>; 1498 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 1499 clocks = <&cru PCLK_EINK>, <&cru HCLK_EINK>; 1500 clock-names = "pclk", "hclk"; 1501 status = "disabled"; 1502 }; 1503 1504 rkvenc: rkvenc@fdf40000 { 1505 compatible = "rockchip,rkv-encoder-v1"; 1506 reg = <0x0 0xfdf40000 0x0 0x400>; 1507 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1508 interrupt-names = "irq_enc"; 1509 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, 1510 <&cru CLK_RKVENC_CORE>; 1511 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 1512 rockchip,normal-rates = <297000000>, <0>, <297000000>; 1513 resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>, 1514 <&cru SRST_RKVENC_CORE>; 1515 reset-names = "video_a", "video_h", "video_core"; 1516 assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>; 1517 assigned-clock-rates = <297000000>, <297000000>; 1518 iommus = <&rkvenc_mmu>; 1519 node-name = "rkvenc"; 1520 rockchip,srv = <&mpp_srv>; 1521 rockchip,taskqueue-node = <3>; 1522 rockchip,resetgroup-node = <3>; 1523 power-domains = <&power RK3568_PD_RKVENC>; 1524 operating-points-v2 = <&rkvenc_opp_table>; 1525 status = "disabled"; 1526 }; 1527 1528 rkvenc_opp_table: rkvenc-opp-table { 1529 compatible = "operating-points-v2"; 1530 1531 nvmem-cells = <&core_pvtm>; 1532 nvmem-cell-names = "pvtm"; 1533 rockchip,pvtm-voltage-sel = < 1534 0 84000 0 1535 84001 91000 1 1536 91001 100000 2 1537 >; 1538 rockchip,pvtm-ch = <0 5>; 1539 1540 opp-297000000 { 1541 opp-hz = /bits/ 64 <297000000>; 1542 opp-microvolt = <900000>; 1543 opp-microvolt-L0 = <900000>; 1544 opp-microvolt-L1 = <875000>; 1545 opp-microvolt-L2 = <875000>; 1546 }; 1547 opp-400000000 { 1548 opp-hz = /bits/ 64 <400000000>; 1549 opp-microvolt = <950000>; 1550 opp-microvolt-L0 = <950000>; 1551 opp-microvolt-L1 = <925000>; 1552 opp-microvolt-L2 = <900000>; 1553 }; 1554 }; 1555 1556 rkvenc_mmu: iommu@fdf40f00 { 1557 compatible = "rockchip,iommu-v2"; 1558 reg = <0x0 0xfdf40f00 0x0 0x40>, <0x0 0xfdf40f40 0x0 0x40>; 1559 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1561 interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1"; 1562 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>; 1563 clock-names = "aclk", "iface"; 1564 rockchip,disable-mmu-reset; 1565 rockchip,enable-cmd-retry; 1566 #iommu-cells = <0>; 1567 power-domains = <&power RK3568_PD_RKVENC>; 1568 status = "disabled"; 1569 }; 1570 1571 rkvdec: rkvdec@fdf80200 { 1572 compatible = "rockchip,rkv-decoder-rk3568", "rockchip,rkv-decoder-v2"; 1573 reg = <0x0 0xfdf80200 0x0 0x400>, <0x0 0xfdf80100 0x0 0x100>; 1574 reg-names = "regs", "link"; 1575 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1576 interrupt-names = "irq_dec"; 1577 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, 1578 <&cru CLK_RKVDEC_CA>, <&cru CLK_RKVDEC_CORE>, 1579 <&cru CLK_RKVDEC_HEVC_CA>; 1580 clock-names = "aclk_vcodec", "hclk_vcodec","clk_cabac", 1581 "clk_core", "clk_hevc_cabac"; 1582 rockchip,normal-rates = <297000000>, <0>, <297000000>, 1583 <297000000>, <600000000>; 1584 rockchip,advanced-rates = <396000000>, <0>, <396000000>, 1585 <396000000>, <600000000>; 1586 rockchip,default-max-load = <2088960>; 1587 resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>, 1588 <&cru SRST_RKVDEC_CA>, <&cru SRST_RKVDEC_CORE>, 1589 <&cru SRST_RKVDEC_HEVC_CA>; 1590 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_CA>, 1591 <&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>; 1592 assigned-clock-rates = <297000000>, <297000000>, <297000000>, <297000000>; 1593 reset-names = "video_a", "video_h", "video_cabac", 1594 "video_core", "video_hevc_cabac"; 1595 power-domains = <&power RK3568_PD_RKVDEC>; 1596 operating-points-v2 = <&rkvdec_opp_table>; 1597 vdec-supply = <&vdd_logic>; 1598 iommus = <&rkvdec_mmu>; 1599 rockchip,srv = <&mpp_srv>; 1600 rockchip,taskqueue-node = <4>; 1601 rockchip,resetgroup-node = <4>; 1602 rockchip,sram = <&rkvdec_sram>; 1603 /* rcb_iova: start and size */ 1604 rockchip,rcb-iova = <0x10000000 65536>; 1605 rockchip,rcb-min-width = <512>; 1606 rockchip,task-capacity = <16>; 1607 status = "disabled"; 1608 }; 1609 1610 rkvdec_opp_table: rkvdec-opp-table { 1611 compatible = "operating-points-v2"; 1612 1613 nvmem-cells = <&log_leakage>, <&core_pvtm>; 1614 nvmem-cell-names = "leakage", "pvtm"; 1615 rockchip,leakage-voltage-sel = < 1616 1 80 0 1617 81 254 1 1618 >; 1619 rockchip,pvtm-voltage-sel = < 1620 0 84000 0 1621 84001 100000 1 1622 >; 1623 rockchip,pvtm-ch = <0 5>; 1624 1625 opp-297000000 { 1626 opp-hz = /bits/ 64 <297000000>; 1627 opp-microvolt = <900000>; 1628 opp-microvolt-L0 = <900000>; 1629 opp-microvolt-L1 = <875000>; 1630 }; 1631 opp-400000000 { 1632 opp-hz = /bits/ 64 <400000000>; 1633 opp-microvolt = <900000>; 1634 }; 1635 }; 1636 1637 rkvdec_mmu: iommu@fdf80800 { 1638 compatible = "rockchip,iommu-v2"; 1639 reg = <0x0 0xfdf80800 0x0 0x40>, <0x0 0xfdf80840 0x0 0x40>; 1640 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1641 interrupt-names = "rkvdec_mmu"; 1642 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 1643 clock-names = "aclk", "iface"; 1644 power-domains = <&power RK3568_PD_RKVDEC>; 1645 #iommu-cells = <0>; 1646 status = "disabled"; 1647 }; 1648 1649 mipi_csi2_hw: mipi-csi2-hw@fdfb0000 { 1650 compatible = "rockchip,rk3568-mipi-csi2-hw"; 1651 reg = <0x0 0xfdfb0000 0x0 0x10000>; 1652 reg-names = "csihost_regs"; 1653 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1655 interrupt-names = "csi-intr1", "csi-intr2"; 1656 clocks = <&cru PCLK_CSI2HOST1>; 1657 clock-names = "pclk_csi2host"; 1658 resets = <&cru SRST_P_CSI2HOST1>; 1659 reset-names = "srst_csihost_p"; 1660 status = "disabled"; 1661 }; 1662 1663 rkcif: rkcif@fdfe0000 { 1664 compatible = "rockchip,rk3568-cif"; 1665 reg = <0x0 0xfdfe0000 0x0 0x8000>; 1666 reg-names = "cif_regs"; 1667 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1668 interrupt-names = "cif-intr"; 1669 1670 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, 1671 <&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>; 1672 clock-names = "aclk_cif", "hclk_cif", 1673 "dclk_cif", "iclk_cif_g"; 1674 resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, 1675 <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>, 1676 <&cru SRST_I_VICAP>; 1677 reset-names = "rst_cif_a", "rst_cif_h", 1678 "rst_cif_d", "rst_cif_p", 1679 "rst_cif_i"; 1680 assigned-clocks = <&cru DCLK_VICAP>; 1681 assigned-clock-rates = <300000000>; 1682 power-domains = <&power RK3568_PD_VI>; 1683 rockchip,grf = <&grf>; 1684 iommus = <&rkcif_mmu>; 1685 status = "disabled"; 1686 }; 1687 1688 rkcif_mmu: iommu@fdfe0800 { 1689 compatible = "rockchip,iommu-v2"; 1690 reg = <0x0 0xfdfe0800 0x0 0x100>; 1691 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1692 interrupt-names = "cif_mmu"; 1693 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; 1694 clock-names = "aclk", "iface"; 1695 power-domains = <&power RK3568_PD_VI>; 1696 rockchip,disable-mmu-reset; 1697 #iommu-cells = <0>; 1698 status = "disabled"; 1699 }; 1700 1701 rkcif_dvp: rkcif_dvp { 1702 compatible = "rockchip,rkcif-dvp"; 1703 rockchip,hw = <&rkcif>; 1704 status = "disabled"; 1705 }; 1706 1707 rkcif_dvp_sditf: rkcif_dvp_sditf { 1708 compatible = "rockchip,rkcif-sditf"; 1709 rockchip,cif = <&rkcif_dvp>; 1710 status = "disabled"; 1711 }; 1712 1713 rkcif_mipi_lvds: rkcif_mipi_lvds { 1714 compatible = "rockchip,rkcif-mipi-lvds"; 1715 rockchip,hw = <&rkcif>; 1716 status = "disabled"; 1717 }; 1718 1719 rkcif_mipi_lvds_sditf: rkcif_mipi_lvds_sditf { 1720 compatible = "rockchip,rkcif-sditf"; 1721 rockchip,cif = <&rkcif_mipi_lvds>; 1722 status = "disabled"; 1723 }; 1724 1725 rkisp: rkisp@fdff0000 { 1726 compatible = "rockchip,rk3568-rkisp"; 1727 reg = <0x0 0xfdff0000 0x0 0x10000>; 1728 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1731 interrupt-names = "mipi_irq", "mi_irq", "isp_irq"; 1732 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru CLK_ISP>; 1733 clock-names = "aclk_isp", "hclk_isp", "clk_isp"; 1734 resets = <&cru SRST_ISP>, <&cru SRST_H_ISP>; 1735 reset-names = "isp", "isp-h"; 1736 rockchip,grf = <&grf>; 1737 power-domains = <&power RK3568_PD_VI>; 1738 iommus = <&rkisp_mmu>; 1739 rockchip,iq-feature = /bits/ 64 <0x1BFBFFFE67FF>; 1740 status = "disabled"; 1741 }; 1742 1743 rkisp_mmu: iommu@fdff1a00 { 1744 compatible = "rockchip,iommu-v2"; 1745 reg = <0x0 0xfdff1a00 0x0 0x100>; 1746 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1747 interrupt-names = "isp_mmu"; 1748 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1749 clock-names = "aclk", "iface"; 1750 power-domains = <&power RK3568_PD_VI>; 1751 #iommu-cells = <0>; 1752 rockchip,disable-mmu-reset; 1753 status = "disabled"; 1754 }; 1755 1756 rkisp_vir0: rkisp-vir0 { 1757 compatible = "rockchip,rkisp-vir"; 1758 rockchip,hw = <&rkisp>; 1759 status = "disabled"; 1760 }; 1761 1762 rkisp_vir1: rkisp-vir1 { 1763 compatible = "rockchip,rkisp-vir"; 1764 rockchip,hw = <&rkisp>; 1765 status = "disabled"; 1766 }; 1767 1768 gmac_uio1: uio@fe010000 { 1769 compatible = "rockchip,uio-gmac"; 1770 reg = <0x0 0xfe010000 0x0 0x10000>; 1771 rockchip,ethernet = <&gmac1>; 1772 status = "disabled"; 1773 }; 1774 1775 gmac0: ethernet@fe2a0000 { 1776 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 1777 reg = <0x0 0xfe2a0000 0x0 0x10000>; 1778 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1780 interrupt-names = "macirq", "eth_wake_irq"; 1781 rockchip,grf = <&grf>; 1782 clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, 1783 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, 1784 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, 1785 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>, 1786 <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>; 1787 clock-names = "stmmaceth", "mac_clk_rx", 1788 "mac_clk_tx", "clk_mac_refout", 1789 "aclk_mac", "pclk_mac", 1790 "clk_mac_speed", "ptp_ref", 1791 "pclk_xpcs", "clk_xpcs_eee"; 1792 resets = <&cru SRST_A_GMAC0>; 1793 reset-names = "stmmaceth"; 1794 1795 snps,mixed-burst; 1796 snps,tso; 1797 1798 snps,axi-config = <&gmac0_stmmac_axi_setup>; 1799 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 1800 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 1801 status = "disabled"; 1802 1803 mdio0: mdio { 1804 compatible = "snps,dwmac-mdio"; 1805 #address-cells = <0x1>; 1806 #size-cells = <0x0>; 1807 }; 1808 1809 gmac0_stmmac_axi_setup: stmmac-axi-config { 1810 snps,wr_osr_lmt = <4>; 1811 snps,rd_osr_lmt = <8>; 1812 snps,blen = <0 0 0 0 16 8 4>; 1813 }; 1814 1815 gmac0_mtl_rx_setup: rx-queues-config { 1816 snps,rx-queues-to-use = <1>; 1817 queue0 {}; 1818 }; 1819 1820 gmac0_mtl_tx_setup: tx-queues-config { 1821 snps,tx-queues-to-use = <1>; 1822 queue0 {}; 1823 }; 1824 }; 1825 1826 gmac1: ethernet@fe010000 { 1827 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 1828 reg = <0x0 0xfe010000 0x0 0x10000>; 1829 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1831 interrupt-names = "macirq", "eth_wake_irq"; 1832 rockchip,grf = <&grf>; 1833 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, 1834 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, 1835 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, 1836 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>, 1837 <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>; 1838 clock-names = "stmmaceth", "mac_clk_rx", 1839 "mac_clk_tx", "clk_mac_refout", 1840 "aclk_mac", "pclk_mac", 1841 "clk_mac_speed", "ptp_ref", 1842 "pclk_xpcs", "clk_xpcs_eee"; 1843 resets = <&cru SRST_A_GMAC1>; 1844 reset-names = "stmmaceth"; 1845 1846 snps,mixed-burst; 1847 snps,tso; 1848 1849 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1850 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1851 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1852 status = "disabled"; 1853 1854 mdio1: mdio { 1855 compatible = "snps,dwmac-mdio"; 1856 #address-cells = <0x1>; 1857 #size-cells = <0x0>; 1858 }; 1859 1860 gmac1_stmmac_axi_setup: stmmac-axi-config { 1861 snps,wr_osr_lmt = <4>; 1862 snps,rd_osr_lmt = <8>; 1863 snps,blen = <0 0 0 0 16 8 4>; 1864 }; 1865 1866 gmac1_mtl_rx_setup: rx-queues-config { 1867 snps,rx-queues-to-use = <1>; 1868 queue0 {}; 1869 }; 1870 1871 gmac1_mtl_tx_setup: tx-queues-config { 1872 snps,tx-queues-to-use = <1>; 1873 queue0 {}; 1874 }; 1875 }; 1876 1877 vop: vop@fe040000 { 1878 compatible = "rockchip,rk3568-vop"; 1879 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; 1880 reg-names = "regs", "gamma_lut"; 1881 rockchip,grf = <&grf>; 1882 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1883 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; 1884 clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2"; 1885 iommus = <&vop_mmu>; 1886 power-domains = <&power RK3568_PD_VO>; 1887 status = "disabled"; 1888 1889 vop_out: ports { 1890 #address-cells = <1>; 1891 #size-cells = <0>; 1892 1893 vp0: port@0 { 1894 #address-cells = <1>; 1895 #size-cells = <0>; 1896 reg = <0>; 1897 1898 vp0_out_dsi0: endpoint@0 { 1899 reg = <0>; 1900 remote-endpoint = <&dsi0_in_vp0>; 1901 }; 1902 1903 vp0_out_dsi1: endpoint@1 { 1904 reg = <1>; 1905 remote-endpoint = <&dsi1_in_vp0>; 1906 }; 1907 1908 vp0_out_edp: endpoint@2 { 1909 reg = <2>; 1910 remote-endpoint = <&edp_in_vp0>; 1911 }; 1912 1913 vp0_out_hdmi: endpoint@3 { 1914 reg = <3>; 1915 remote-endpoint = <&hdmi_in_vp0>; 1916 }; 1917 }; 1918 1919 vp1: port@1 { 1920 #address-cells = <1>; 1921 #size-cells = <0>; 1922 reg = <1>; 1923 1924 vp1_out_dsi0: endpoint@0 { 1925 reg = <0>; 1926 remote-endpoint = <&dsi0_in_vp1>; 1927 }; 1928 1929 vp1_out_dsi1: endpoint@1 { 1930 reg = <1>; 1931 remote-endpoint = <&dsi1_in_vp1>; 1932 }; 1933 1934 vp1_out_edp: endpoint@2 { 1935 reg = <2>; 1936 remote-endpoint = <&edp_in_vp1>; 1937 }; 1938 1939 vp1_out_hdmi: endpoint@3 { 1940 reg = <3>; 1941 remote-endpoint = <&hdmi_in_vp1>; 1942 }; 1943 1944 vp1_out_lvds: endpoint@4 { 1945 reg = <4>; 1946 remote-endpoint = <&lvds_in_vp1>; 1947 }; 1948 }; 1949 1950 vp2: port@2 { 1951 #address-cells = <1>; 1952 #size-cells = <0>; 1953 1954 reg = <2>; 1955 1956 vp2_out_lvds: endpoint@0 { 1957 reg = <0>; 1958 remote-endpoint = <&lvds_in_vp2>; 1959 }; 1960 1961 vp2_out_rgb: endpoint@1 { 1962 reg = <1>; 1963 remote-endpoint = <&rgb_in_vp2>; 1964 }; 1965 }; 1966 }; 1967 }; 1968 1969 vop_mmu: iommu@fe043e00 { 1970 compatible = "rockchip,iommu-v2"; 1971 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; 1972 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1973 interrupt-names = "vop_mmu"; 1974 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1975 clock-names = "aclk", "iface"; 1976 #iommu-cells = <0>; 1977 rockchip,disable-device-link-resume; 1978 status = "disabled"; 1979 }; 1980 1981 dsi0: dsi@fe060000 { 1982 compatible = "rockchip,rk3568-mipi-dsi"; 1983 reg = <0x0 0xfe060000 0x0 0x10000>; 1984 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1985 clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>; 1986 clock-names = "pclk", "hclk"; 1987 resets = <&cru SRST_P_DSITX_0>; 1988 reset-names = "apb"; 1989 phys = <&video_phy0>; 1990 phy-names = "dphy"; 1991 power-domains = <&power RK3568_PD_VO>; 1992 rockchip,grf = <&grf>; 1993 #address-cells = <1>; 1994 #size-cells = <0>; 1995 status = "disabled"; 1996 1997 ports { 1998 #address-cells = <1>; 1999 #size-cells = <0>; 2000 2001 dsi0_in: port@0 { 2002 reg = <0>; 2003 #address-cells = <1>; 2004 #size-cells = <0>; 2005 2006 dsi0_in_vp0: endpoint@0 { 2007 reg = <0>; 2008 remote-endpoint = <&vp0_out_dsi0>; 2009 status = "disabled"; 2010 }; 2011 2012 dsi0_in_vp1: endpoint@1 { 2013 reg = <1>; 2014 remote-endpoint = <&vp1_out_dsi0>; 2015 status = "disabled"; 2016 }; 2017 }; 2018 }; 2019 }; 2020 2021 dsi1: dsi@fe070000 { 2022 compatible = "rockchip,rk3568-mipi-dsi"; 2023 reg = <0x0 0xfe070000 0x0 0x10000>; 2024 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 2025 clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>; 2026 clock-names = "pclk", "hclk"; 2027 resets = <&cru SRST_P_DSITX_1>; 2028 reset-names = "apb"; 2029 phys = <&video_phy1>; 2030 phy-names = "dphy"; 2031 power-domains = <&power RK3568_PD_VO>; 2032 rockchip,grf = <&grf>; 2033 #address-cells = <1>; 2034 #size-cells = <0>; 2035 status = "disabled"; 2036 2037 ports { 2038 #address-cells = <1>; 2039 #size-cells = <0>; 2040 2041 dsi1_in: port@0 { 2042 reg = <0>; 2043 #address-cells = <1>; 2044 #size-cells = <0>; 2045 2046 dsi1_in_vp0: endpoint@0 { 2047 reg = <0>; 2048 remote-endpoint = <&vp0_out_dsi1>; 2049 status = "disabled"; 2050 }; 2051 2052 dsi1_in_vp1: endpoint@1 { 2053 reg = <1>; 2054 remote-endpoint = <&vp1_out_dsi1>; 2055 status = "disabled"; 2056 }; 2057 }; 2058 }; 2059 }; 2060 2061 hdmi: hdmi@fe0a0000 { 2062 compatible = "rockchip,rk3568-dw-hdmi"; 2063 reg = <0x0 0xfe0a0000 0x0 0x20000>; 2064 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2065 clocks = <&cru PCLK_HDMI_HOST>, 2066 <&cru CLK_HDMI_SFR>, 2067 <&cru CLK_HDMI_CEC>, 2068 <&pmucru PLL_HPLL>, 2069 <&cru HCLK_VOP>; 2070 clock-names = "iahb", "isfr", "cec", "ref", "hclk"; 2071 power-domains = <&power RK3568_PD_VO>; 2072 reg-io-width = <4>; 2073 rockchip,grf = <&grf>; 2074 #sound-dai-cells = <0>; 2075 pinctrl-names = "default"; 2076 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; 2077 status = "disabled"; 2078 2079 ports { 2080 #address-cells = <1>; 2081 #size-cells = <0>; 2082 2083 port@0 { 2084 reg = <0>; 2085 #address-cells = <1>; 2086 #size-cells = <0>; 2087 2088 hdmi_in_vp0: endpoint@0 { 2089 reg = <0>; 2090 remote-endpoint = <&vp0_out_hdmi>; 2091 status = "disabled"; 2092 }; 2093 2094 hdmi_in_vp1: endpoint@1 { 2095 reg = <1>; 2096 remote-endpoint = <&vp1_out_hdmi>; 2097 status = "disabled"; 2098 }; 2099 }; 2100 }; 2101 }; 2102 2103 edp: edp@fe0c0000 { 2104 compatible = "rockchip,rk3568-edp"; 2105 reg = <0x0 0xfe0c0000 0x0 0x10000>; 2106 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 2107 clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDP_CTRL>, 2108 <&cru CLK_EDP_200M>, <&cru HCLK_VO>; 2109 clock-names = "dp", "pclk", "spdif", "hclk"; 2110 resets = <&cru SRST_EDP_24M>, <&cru SRST_P_EDP_CTRL>; 2111 reset-names = "dp", "apb"; 2112 phys = <&edp_phy>; 2113 phy-names = "dp"; 2114 power-domains = <&power RK3568_PD_VO>; 2115 status = "disabled"; 2116 2117 ports { 2118 #address-cells = <1>; 2119 #size-cells = <0>; 2120 2121 edp_in: port@0 { 2122 reg = <0>; 2123 #address-cells = <1>; 2124 #size-cells = <0>; 2125 2126 edp_in_vp0: endpoint@0 { 2127 reg = <0>; 2128 remote-endpoint = <&vp0_out_edp>; 2129 status = "disabled"; 2130 }; 2131 2132 edp_in_vp1: endpoint@1 { 2133 reg = <1>; 2134 remote-endpoint = <&vp1_out_edp>; 2135 status = "disabled"; 2136 }; 2137 }; 2138 }; 2139 }; 2140 2141 nocp_cpu: nocp-cpu@fe102000 { 2142 compatible = "rockchip,rk3568-nocp"; 2143 reg = <0x0 0xfe102000 0x0 0x400>; 2144 }; 2145 2146 nocp_gpu_vpu_rga_venc: nocp-gpu-vpu-rga-venc@fe102400 { 2147 compatible = "rockchip,rk3568-nocp"; 2148 reg = <0x0 0xfe102400 0x0 0x400>; 2149 }; 2150 2151 nocp_npu_vdec: nocp-vdec@fe102800 { 2152 compatible = "rockchip,rk3568-nocp"; 2153 reg = <0x0 0xfe102800 0x0 0x400>; 2154 }; 2155 2156 nocp_vi_usb_peri_pipe: nocp-vi-usb-peri-pipe@fe102c00 { 2157 compatible = "rockchip,rk3568-nocp"; 2158 reg = <0x0 0xfe102c00 0x0 0x400>; 2159 }; 2160 2161 nocp_vo: nocp-vo@fe103000 { 2162 compatible = "rockchip,rk3568-nocp"; 2163 reg = <0x0 0xfe103000 0x0 0x400>; 2164 }; 2165 2166 qos_gpu: qos@fe128000 { 2167 compatible = "syscon"; 2168 reg = <0x0 0xfe128000 0x0 0x20>; 2169 }; 2170 2171 qos_rkvenc_rd_m0: qos@fe138080 { 2172 compatible = "syscon"; 2173 reg = <0x0 0xfe138080 0x0 0x20>; 2174 }; 2175 2176 qos_rkvenc_rd_m1: qos@fe138100 { 2177 compatible = "syscon"; 2178 reg = <0x0 0xfe138100 0x0 0x20>; 2179 }; 2180 2181 qos_rkvenc_wr_m0: qos@fe138180 { 2182 compatible = "syscon"; 2183 reg = <0x0 0xfe138180 0x0 0x20>; 2184 }; 2185 2186 qos_isp: qos@fe148000 { 2187 compatible = "syscon"; 2188 reg = <0x0 0xfe148000 0x0 0x20>; 2189 }; 2190 2191 qos_vicap0: qos@fe148080 { 2192 compatible = "syscon"; 2193 reg = <0x0 0xfe148080 0x0 0x20>; 2194 }; 2195 2196 qos_vicap1: qos@fe148100 { 2197 compatible = "syscon"; 2198 reg = <0x0 0xfe148100 0x0 0x20>; 2199 }; 2200 2201 qos_vpu: qos@fe150000 { 2202 compatible = "syscon"; 2203 reg = <0x0 0xfe150000 0x0 0x20>; 2204 }; 2205 2206 qos_ebc: qos@fe158000 { 2207 compatible = "syscon"; 2208 reg = <0x0 0xfe158000 0x0 0x20>; 2209 }; 2210 2211 qos_iep: qos@fe158100 { 2212 compatible = "syscon"; 2213 reg = <0x0 0xfe158100 0x0 0x20>; 2214 }; 2215 2216 qos_jpeg_dec: qos@fe158180 { 2217 compatible = "syscon"; 2218 reg = <0x0 0xfe158180 0x0 0x20>; 2219 }; 2220 2221 qos_jpeg_enc: qos@fe158200 { 2222 compatible = "syscon"; 2223 reg = <0x0 0xfe158200 0x0 0x20>; 2224 }; 2225 2226 qos_rga_rd: qos@fe158280 { 2227 compatible = "syscon"; 2228 reg = <0x0 0xfe158280 0x0 0x20>; 2229 }; 2230 2231 qos_rga_wr: qos@fe158300 { 2232 compatible = "syscon"; 2233 reg = <0x0 0xfe158300 0x0 0x20>; 2234 }; 2235 2236 qos_npu: qos@fe180000 { 2237 compatible = "syscon"; 2238 reg = <0x0 0xfe180000 0x0 0x20>; 2239 }; 2240 2241 qos_pcie2x1: qos@fe190000 { 2242 compatible = "syscon"; 2243 reg = <0x0 0xfe190000 0x0 0x20>; 2244 }; 2245 2246 qos_pcie3x1: qos@fe190080 { 2247 compatible = "syscon"; 2248 reg = <0x0 0xfe190080 0x0 0x20>; 2249 }; 2250 2251 qos_pcie3x2: qos@fe190100 { 2252 compatible = "syscon"; 2253 reg = <0x0 0xfe190100 0x0 0x20>; 2254 }; 2255 2256 qos_sata0: qos@fe190200 { 2257 compatible = "syscon"; 2258 reg = <0x0 0xfe190200 0x0 0x20>; 2259 }; 2260 2261 qos_sata1: qos@fe190280 { 2262 compatible = "syscon"; 2263 reg = <0x0 0xfe190280 0x0 0x20>; 2264 }; 2265 2266 qos_sata2: qos@fe190300 { 2267 compatible = "syscon"; 2268 reg = <0x0 0xfe190300 0x0 0x20>; 2269 }; 2270 2271 qos_usb3_0: qos@fe190380 { 2272 compatible = "syscon"; 2273 reg = <0x0 0xfe190380 0x0 0x20>; 2274 }; 2275 2276 qos_usb3_1: qos@fe190400 { 2277 compatible = "syscon"; 2278 reg = <0x0 0xfe190400 0x0 0x20>; 2279 }; 2280 2281 qos_rkvdec: qos@fe198000 { 2282 compatible = "syscon"; 2283 reg = <0x0 0xfe198000 0x0 0x20>; 2284 }; 2285 2286 qos_hdcp: qos@fe1a8000 { 2287 compatible = "syscon"; 2288 reg = <0x0 0xfe1a8000 0x0 0x20>; 2289 }; 2290 2291 qos_vop_m0: qos@fe1a8080 { 2292 compatible = "syscon"; 2293 reg = <0x0 0xfe1a8080 0x0 0x20>; 2294 }; 2295 2296 qos_vop_m1: qos@fe1a8100 { 2297 compatible = "syscon"; 2298 reg = <0x0 0xfe1a8100 0x0 0x20>; 2299 }; 2300 2301 sdmmc2: dwmmc@fe000000 { 2302 compatible = "rockchip,rk3568-dw-mshc", 2303 "rockchip,rk3288-dw-mshc"; 2304 reg = <0x0 0xfe000000 0x0 0x4000>; 2305 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2306 max-frequency = <150000000>; 2307 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, 2308 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; 2309 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 2310 fifo-depth = <0x100>; 2311 resets = <&cru SRST_SDMMC2>; 2312 reset-names = "reset"; 2313 status = "disabled"; 2314 }; 2315 2316 dfi: dfi@fe230000 { 2317 reg = <0x00 0xfe230000 0x00 0x400>; 2318 compatible = "rockchip,rk3568-dfi"; 2319 rockchip,pmugrf = <&pmugrf>; 2320 status = "disabled"; 2321 }; 2322 2323 dmc: dmc { 2324 compatible = "rockchip,rk3568-dmc"; 2325 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2326 interrupt-names = "complete"; 2327 devfreq-events = <&dfi>, <&nocp_cpu>; 2328 clocks = <&scmi_clk 3>; 2329 clock-names = "dmc_clk"; 2330 operating-points-v2 = <&dmc_opp_table>; 2331 vop-bw-dmc-freq = < 2332 /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ 2333 0 286 324000 2334 287 99999 528000 2335 >; 2336 vop-frame-bw-dmc-freq = < 2337 /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ 2338 0 620 324000 2339 621 99999 780000 2340 >; 2341 cpu-bw-dmc-freq = < 2342 /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ 2343 0 350 324000 2344 351 400 528000 2345 401 99999 780000 2346 >; 2347 upthreshold = <40>; 2348 downdifferential = <20>; 2349 system-status-level = < 2350 /*system status freq level*/ 2351 SYS_STATUS_NORMAL DMC_FREQ_LEVEL_MID_HIGH 2352 SYS_STATUS_REBOOT DMC_FREQ_LEVEL_HIGH 2353 SYS_STATUS_SUSPEND DMC_FREQ_LEVEL_LOW 2354 SYS_STATUS_VIDEO_4K DMC_FREQ_LEVEL_MID_HIGH 2355 SYS_STATUS_VIDEO_4K_10B DMC_FREQ_LEVEL_MID_HIGH 2356 SYS_STATUS_BOOST DMC_FREQ_LEVEL_HIGH 2357 SYS_STATUS_ISP DMC_FREQ_LEVEL_HIGH 2358 SYS_STATUS_PERFORMANCE DMC_FREQ_LEVEL_HIGH 2359 SYS_STATUS_DUALVIEW DMC_FREQ_LEVEL_HIGH 2360 >; 2361 auto-min-freq = <324000>; 2362 auto-freq-en = <1>; 2363 #cooling-cells = <2>; 2364 status = "disabled"; 2365 }; 2366 2367 dmc_fsp: dmc-fsp { 2368 compatible = "rockchip,rk3568-dmc-fsp"; 2369 2370 debug_print_level = <0>; 2371 ddr3_params = <&ddr3_params>; 2372 ddr4_params = <&ddr4_params>; 2373 lpddr3_params = <&lpddr3_params>; 2374 lpddr4_params = <&lpddr4_params>; 2375 lpddr4x_params = <&lpddr4x_params>; 2376 2377 status = "okay"; 2378 }; 2379 2380 dmc_opp_table: dmc-opp-table { 2381 compatible = "operating-points-v2"; 2382 2383 mbist-vmin = <825000 900000 950000>; 2384 nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>, <&dmc_opp_info>; 2385 nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info"; 2386 rockchip,max-volt = <1000000>; 2387 rockchip,temp-hysteresis = <5000>; 2388 rockchip,low-temp = <0>; 2389 rockchip,low-temp-adjust-volt = < 2390 /* MHz MHz uV */ 2391 0 1560 75000 2392 >; 2393 rockchip,leakage-voltage-sel = < 2394 1 80 0 2395 81 254 1 2396 >; 2397 rockchip,pvtm-voltage-sel = < 2398 0 84000 0 2399 84001 100000 1 2400 >; 2401 rockchip,pvtm-ch = <0 5>; 2402 2403 opp-1560000000 { 2404 opp-hz = /bits/ 64 <1560000000>; 2405 opp-microvolt = <900000 900000 1000000>; 2406 opp-microvolt-L0 = <900000 900000 1000000>; 2407 opp-microvolt-L1 = <875000 875000 1000000>; 2408 }; 2409 }; 2410 2411 pcie2x1: pcie@fe260000 { 2412 compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; 2413 #address-cells = <3>; 2414 #size-cells = <2>; 2415 bus-range = <0x0 0xf>; 2416 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, 2417 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, 2418 <&cru CLK_PCIE20_AUX_NDFT>; 2419 clock-names = "aclk_mst", "aclk_slv", 2420 "aclk_dbi", "pclk", "aux"; 2421 device_type = "pci"; 2422 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 2423 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 2424 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 2425 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 2426 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2427 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 2428 #interrupt-cells = <1>; 2429 interrupt-map-mask = <0 0 0 7>; 2430 interrupt-map = <0 0 0 1 &pcie2x1_intc 0>, 2431 <0 0 0 2 &pcie2x1_intc 1>, 2432 <0 0 0 3 &pcie2x1_intc 2>, 2433 <0 0 0 4 &pcie2x1_intc 3>; 2434 linux,pci-domain = <0>; 2435 num-ib-windows = <6>; 2436 num-viewport = <8>; 2437 num-ob-windows = <2>; 2438 max-link-speed = <2>; 2439 msi-map = <0x0 &its 0x0 0x1000>; 2440 num-lanes = <1>; 2441 phys = <&combphy2_psq PHY_TYPE_PCIE>; 2442 phy-names = "pcie-phy"; 2443 power-domains = <&power RK3568_PD_PIPE>; 2444 ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000 2445 0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000 2446 0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x1e00000 2447 0xc3000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>; 2448 reg = <0x3 0xc0000000 0x0 0x400000>, 2449 <0x0 0xfe260000 0x0 0x10000>; 2450 reg-names = "pcie-dbi", "pcie-apb"; 2451 resets = <&cru SRST_PCIE20_POWERUP>; 2452 reset-names = "pipe"; 2453 status = "disabled"; 2454 2455 pcie2x1_intc: legacy-interrupt-controller { 2456 interrupt-controller; 2457 #address-cells = <0>; 2458 #interrupt-cells = <1>; 2459 interrupt-parent = <&gic>; 2460 interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 2461 }; 2462 }; 2463 2464 pcie3x1: pcie@fe270000 { 2465 compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; 2466 #address-cells = <3>; 2467 #size-cells = <2>; 2468 bus-range = <0x10 0x1f>; 2469 clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, 2470 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, 2471 <&cru CLK_PCIE30X1_AUX_NDFT>; 2472 clock-names = "aclk_mst", "aclk_slv", 2473 "aclk_dbi", "pclk", "aux"; 2474 device_type = "pci"; 2475 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2476 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 2477 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 2478 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 2479 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 2480 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 2481 #interrupt-cells = <1>; 2482 interrupt-map-mask = <0 0 0 7>; 2483 interrupt-map = <0 0 0 1 &pcie3x1_intc 0>, 2484 <0 0 0 2 &pcie3x1_intc 1>, 2485 <0 0 0 3 &pcie3x1_intc 2>, 2486 <0 0 0 4 &pcie3x1_intc 3>; 2487 linux,pci-domain = <1>; 2488 num-ib-windows = <6>; 2489 num-ob-windows = <2>; 2490 num-viewport = <8>; 2491 max-link-speed = <3>; 2492 msi-map = <0x1000 &its 0x1000 0x1000>; 2493 num-lanes = <1>; 2494 phys = <&pcie30phy>; 2495 phy-names = "pcie-phy"; 2496 power-domains = <&power RK3568_PD_PIPE>; 2497 ranges = <0x00000800 0x0 0xf2000000 0x0 0xf2000000 0x0 0x100000 2498 0x81000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x100000 2499 0x82000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x1e00000 2500 0xc3000000 0x3 0x40000000 0x3 0x40000000 0x0 0x40000000>; 2501 reg = <0x3 0xc0400000 0x0 0x400000>, 2502 <0x0 0xfe270000 0x0 0x10000>; 2503 reg-names = "pcie-dbi", "pcie-apb"; 2504 resets = <&cru SRST_PCIE30X1_POWERUP>; 2505 reset-names = "pipe"; 2506 /* rockchip,bifurcation; lane1 when using 1+1 */ 2507 status = "disabled"; 2508 2509 pcie3x1_intc: legacy-interrupt-controller { 2510 interrupt-controller; 2511 #address-cells = <0>; 2512 #interrupt-cells = <1>; 2513 interrupt-parent = <&gic>; 2514 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2515 }; 2516 }; 2517 2518 pcie3x2: pcie@fe280000 { 2519 compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; 2520 #address-cells = <3>; 2521 #size-cells = <2>; 2522 bus-range = <0x20 0x2f>; 2523 clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, 2524 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, 2525 <&cru CLK_PCIE30X2_AUX_NDFT>; 2526 clock-names = "aclk_mst", "aclk_slv", 2527 "aclk_dbi", "pclk", "aux"; 2528 device_type = "pci"; 2529 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 2530 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 2531 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 2532 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 2533 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 2534 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 2535 #interrupt-cells = <1>; 2536 interrupt-map-mask = <0 0 0 7>; 2537 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, 2538 <0 0 0 2 &pcie3x2_intc 1>, 2539 <0 0 0 3 &pcie3x2_intc 2>, 2540 <0 0 0 4 &pcie3x2_intc 3>; 2541 linux,pci-domain = <2>; 2542 num-ib-windows = <6>; 2543 num-viewport = <8>; 2544 num-ob-windows = <2>; 2545 max-link-speed = <3>; 2546 msi-map = <0x2000 &its 0x2000 0x1000>; 2547 num-lanes = <2>; 2548 phys = <&pcie30phy>; 2549 phy-names = "pcie-phy"; 2550 power-domains = <&power RK3568_PD_PIPE>; 2551 ranges = <0x00000800 0x0 0xf0000000 0x0 0xf0000000 0x0 0x100000 2552 0x81000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x100000 2553 0x82000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x1e00000 2554 0xc3000000 0x3 0x80000000 0x3 0x80000000 0x0 0x40000000>; 2555 reg = <0x3 0xc0800000 0x0 0x400000>, 2556 <0x0 0xfe280000 0x0 0x10000>; 2557 reg-names = "pcie-dbi", "pcie-apb"; 2558 resets = <&cru SRST_PCIE30X2_POWERUP>; 2559 reset-names = "pipe"; 2560 /* rockchip,bifurcation; lane0 when using 1+1 */ 2561 status = "disabled"; 2562 2563 pcie3x2_intc: legacy-interrupt-controller { 2564 interrupt-controller; 2565 #address-cells = <0>; 2566 #interrupt-cells = <1>; 2567 interrupt-parent = <&gic>; 2568 interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>; 2569 }; 2570 }; 2571 2572 gmac_uio0: uio@fe2a0000 { 2573 compatible = "rockchip,uio-gmac"; 2574 reg = <0x0 0xfe2a0000 0x0 0x10000>; 2575 rockchip,ethernet = <&gmac0>; 2576 status = "disabled"; 2577 }; 2578 2579 sdmmc0: dwmmc@fe2b0000 { 2580 compatible = "rockchip,rk3568-dw-mshc", 2581 "rockchip,rk3288-dw-mshc"; 2582 reg = <0x0 0xfe2b0000 0x0 0x4000>; 2583 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2584 max-frequency = <150000000>; 2585 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, 2586 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 2587 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 2588 fifo-depth = <0x100>; 2589 resets = <&cru SRST_SDMMC0>; 2590 reset-names = "reset"; 2591 status = "disabled"; 2592 }; 2593 2594 sdmmc1: dwmmc@fe2c0000 { 2595 compatible = "rockchip,rk3568-dw-mshc", 2596 "rockchip,rk3288-dw-mshc"; 2597 reg = <0x0 0xfe2c0000 0x0 0x4000>; 2598 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2599 max-frequency = <150000000>; 2600 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, 2601 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 2602 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 2603 fifo-depth = <0x100>; 2604 resets = <&cru SRST_SDMMC1>; 2605 reset-names = "reset"; 2606 status = "disabled"; 2607 }; 2608 2609 sfc: spi@fe300000 { 2610 compatible = "rockchip,sfc"; 2611 reg = <0x0 0xfe300000 0x0 0x4000>; 2612 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2613 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 2614 clock-names = "clk_sfc", "hclk_sfc"; 2615 assigned-clocks = <&cru SCLK_SFC>; 2616 assigned-clock-rates = <100000000>; 2617 #address-cells = <1>; 2618 #size-cells = <0>; 2619 status = "disabled"; 2620 }; 2621 2622 sdhci: sdhci@fe310000 { 2623 compatible = "rockchip,rk3568-dwcmshc", "rockchip,dwcmshc-sdhci"; 2624 reg = <0x0 0xfe310000 0x0 0x10000>; 2625 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 2626 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, 2627 <&cru CCLK_EMMC>; 2628 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 2629 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 2630 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 2631 <&cru TCLK_EMMC>; 2632 clock-names = "core", "bus", "axi", "block", "timer"; 2633 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 2634 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 2635 <&cru SRST_T_EMMC>; 2636 reset-names = "core", "bus", "axi", "block", "timer"; 2637 status = "disabled"; 2638 }; 2639 2640 nandc0: nandc@fe330000 { 2641 compatible = "rockchip,rk-nandc-v9"; 2642 reg = <0x0 0xfe330000 0x0 0x4000>; 2643 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 2644 nandc_id = <0>; 2645 clocks = <&cru NCLK_NANDC>, <&cru HCLK_NANDC>; 2646 clock-names = "clk_nandc", "hclk_nandc"; 2647 status = "disabled"; 2648 }; 2649 2650 crypto: crypto@fe380000 { 2651 compatible = "rockchip,rk3568-crypto"; 2652 reg = <0x0 0xfe380000 0x0 0x4000>; 2653 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 2654 clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>, 2655 <&cru CLK_CRYPTO_NS_CORE>, <&cru CLK_CRYPTO_NS_PKA>; 2656 clock-names = "aclk", "hclk", "sclk", "apb_pclk"; 2657 assigned-clocks = <&cru CLK_CRYPTO_NS_CORE>; 2658 assigned-clock-rates = <200000000>; 2659 resets = <&cru SRST_CRYPTO_NS_CORE>; 2660 reset-names = "crypto-rst"; 2661 status = "disabled"; 2662 }; 2663 2664 rng: rng@fe388000 { 2665 compatible = "rockchip,cryptov2-rng"; 2666 reg = <0x0 0xfe388000 0x0 0x2000>; 2667 clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>; 2668 clock-names = "clk_trng", "hclk_trng"; 2669 resets = <&cru SRST_TRNG_NS>; 2670 reset-names = "reset"; 2671 status = "disabled"; 2672 }; 2673 2674 otp: otp@fe38c000 { 2675 compatible = "rockchip,rk3568-otp"; 2676 reg = <0x0 0xfe38c000 0x0 0x4000>; 2677 #address-cells = <1>; 2678 #size-cells = <1>; 2679 clocks = <&cru CLK_OTPC_NS_USR>, <&cru CLK_OTPC_NS_SBPI>, 2680 <&cru PCLK_OTPC_NS>, <&cru PCLK_OTPPHY>; 2681 clock-names = "usr", "sbpi", "apb", "phy"; 2682 resets = <&cru SRST_OTPPHY>; 2683 reset-names = "otp_phy"; 2684 2685 /* Data cells */ 2686 cpu_code: cpu-code@2 { 2687 reg = <0x02 0x2>; 2688 }; 2689 otp_cpu_version: cpu-version@8 { 2690 reg = <0x08 0x1>; 2691 bits = <3 3>; 2692 }; 2693 mbist_vmin: mbist-vmin@9 { 2694 reg = <0x09 0x1>; 2695 bits = <0 4>; 2696 }; 2697 otp_id: id@a { 2698 reg = <0x0a 0x10>; 2699 }; 2700 cpu_leakage: cpu-leakage@1a { 2701 reg = <0x1a 0x1>; 2702 }; 2703 log_leakage: log-leakage@1b { 2704 reg = <0x1b 0x1>; 2705 }; 2706 npu_leakage: npu-leakage@1c { 2707 reg = <0x1c 0x1>; 2708 }; 2709 gpu_leakage: gpu-leakage@1d { 2710 reg = <0x1d 0x1>; 2711 }; 2712 core_pvtm:core-pvtm@2a { 2713 reg = <0x2a 0x2>; 2714 }; 2715 cpu_tsadc_trim_l: cpu-tsadc-trim-l@2e { 2716 reg = <0x2e 0x1>; 2717 }; 2718 cpu_tsadc_trim_h: cpu-tsadc-trim-h@2f { 2719 reg = <0x2f 0x1>; 2720 bits = <0 4>; 2721 }; 2722 gpu_tsadc_trim_l: npu-tsadc-trim-l@30 { 2723 reg = <0x30 0x1>; 2724 }; 2725 gpu_tsadc_trim_h: npu-tsadc-trim-h@31 { 2726 reg = <0x31 0x1>; 2727 bits = <0 4>; 2728 }; 2729 tsadc_trim_base_frac: tsadc-trim-base-frac@31 { 2730 reg = <0x31 0x1>; 2731 bits = <4 4>; 2732 }; 2733 tsadc_trim_base: tsadc-trim-base@32 { 2734 reg = <0x32 0x1>; 2735 }; 2736 cpu_opp_info: cpu-opp-info@36 { 2737 reg = <0x36 0x6>; 2738 }; 2739 gpu_opp_info: gpu-opp-info@3c { 2740 reg = <0x3c 0x6>; 2741 }; 2742 npu_opp_info: npu-opp-info@42 { 2743 reg = <0x42 0x6>; 2744 }; 2745 dmc_opp_info: dmc-opp-info@48 { 2746 reg = <0x48 0x6>; 2747 }; 2748 }; 2749 2750 i2s0_8ch: i2s@fe400000 { 2751 compatible = "rockchip,rk3568-i2s-tdm"; 2752 reg = <0x0 0xfe400000 0x0 0x1000>; 2753 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 2754 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 2755 clock-names = "mclk_tx", "mclk_rx", "hclk"; 2756 dmas = <&dmac1 0>; 2757 dma-names = "tx"; 2758 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 2759 reset-names = "tx-m", "rx-m"; 2760 rockchip,cru = <&cru>; 2761 rockchip,grf = <&grf>; 2762 rockchip,playback-only; 2763 #sound-dai-cells = <0>; 2764 status = "disabled"; 2765 }; 2766 2767 i2s1_8ch: i2s@fe410000 { 2768 compatible = "rockchip,rk3568-i2s-tdm"; 2769 reg = <0x0 0xfe410000 0x0 0x1000>; 2770 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2771 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 2772 clock-names = "mclk_tx", "mclk_rx", "hclk"; 2773 dmas = <&dmac1 2>, <&dmac1 3>; 2774 dma-names = "tx", "rx"; 2775 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 2776 reset-names = "tx-m", "rx-m"; 2777 rockchip,cru = <&cru>; 2778 rockchip,grf = <&grf>; 2779 #sound-dai-cells = <0>; 2780 pinctrl-names = "default"; 2781 pinctrl-0 = <&i2s1m0_sclktx 2782 &i2s1m0_sclkrx 2783 &i2s1m0_lrcktx 2784 &i2s1m0_lrckrx 2785 &i2s1m0_sdi0 2786 &i2s1m0_sdi1 2787 &i2s1m0_sdi2 2788 &i2s1m0_sdi3 2789 &i2s1m0_sdo0 2790 &i2s1m0_sdo1 2791 &i2s1m0_sdo2 2792 &i2s1m0_sdo3>; 2793 status = "disabled"; 2794 }; 2795 2796 i2s2_2ch: i2s@fe420000 { 2797 compatible = "rockchip,rk3568-i2s-tdm"; 2798 reg = <0x0 0xfe420000 0x0 0x1000>; 2799 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 2800 clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 2801 clock-names = "mclk_tx", "mclk_rx", "hclk"; 2802 dmas = <&dmac1 4>, <&dmac1 5>; 2803 dma-names = "tx", "rx"; 2804 rockchip,cru = <&cru>; 2805 rockchip,grf = <&grf>; 2806 rockchip,clk-trcm = <1>; 2807 #sound-dai-cells = <0>; 2808 pinctrl-names = "default"; 2809 pinctrl-0 = <&i2s2m0_sclktx 2810 &i2s2m0_lrcktx 2811 &i2s2m0_sdi 2812 &i2s2m0_sdo>; 2813 status = "disabled"; 2814 }; 2815 2816 i2s3_2ch: i2s@fe430000 { 2817 compatible = "rockchip,rk3568-i2s-tdm"; 2818 reg = <0x0 0xfe430000 0x0 0x1000>; 2819 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 2820 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, <&cru HCLK_I2S3_2CH>; 2821 clock-names = "mclk_tx", "mclk_rx", "hclk"; 2822 dmas = <&dmac1 6>, <&dmac1 7>; 2823 dma-names = "tx", "rx"; 2824 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; 2825 reset-names = "tx-m", "rx-m"; 2826 rockchip,cru = <&cru>; 2827 rockchip,grf = <&grf>; 2828 rockchip,clk-trcm = <1>; 2829 #sound-dai-cells = <0>; 2830 pinctrl-names = "default"; 2831 pinctrl-0 = <&i2s3m0_sclk 2832 &i2s3m0_lrck 2833 &i2s3m0_sdi 2834 &i2s3m0_sdo>; 2835 status = "disabled"; 2836 }; 2837 2838 pdm: pdm@fe440000 { 2839 compatible = "rockchip,rk3568-pdm", "rockchip,pdm"; 2840 reg = <0x0 0xfe440000 0x0 0x1000>; 2841 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 2842 clock-names = "pdm_clk", "pdm_hclk"; 2843 dmas = <&dmac1 9>; 2844 dma-names = "rx"; 2845 pinctrl-names = "default"; 2846 pinctrl-0 = <&pdmm0_clk 2847 &pdmm0_clk1 2848 &pdmm0_sdi0 2849 &pdmm0_sdi1 2850 &pdmm0_sdi2 2851 &pdmm0_sdi3>; 2852 #sound-dai-cells = <0>; 2853 status = "disabled"; 2854 }; 2855 2856 vad: vad@fe450000 { 2857 compatible = "rockchip,rk3568-vad"; 2858 reg = <0x0 0xfe450000 0x0 0x10000>; 2859 reg-names = "vad"; 2860 clocks = <&cru HCLK_VAD>; 2861 clock-names = "hclk"; 2862 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 2863 rockchip,audio-src = <0>; 2864 rockchip,det-channel = <0>; 2865 rockchip,mode = <0>; 2866 #sound-dai-cells = <0>; 2867 status = "disabled"; 2868 }; 2869 2870 spdif_8ch: spdif@fe460000 { 2871 compatible = "rockchip,rk3568-spdif"; 2872 reg = <0x0 0xfe460000 0x0 0x1000>; 2873 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2874 dmas = <&dmac1 1>; 2875 dma-names = "tx"; 2876 clock-names = "mclk", "hclk"; 2877 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; 2878 #sound-dai-cells = <0>; 2879 pinctrl-names = "default"; 2880 pinctrl-0 = <&spdifm0_tx>; 2881 status = "disabled"; 2882 }; 2883 2884 audpwm: audpwm@fe470000 { 2885 compatible = "rockchip,rk3568-audio-pwm", "rockchip,audio-pwm-v1"; 2886 reg = <0x0 0xfe470000 0x0 0x1000>; 2887 clocks = <&cru SCLK_AUDPWM>, <&cru HCLK_AUDPWM>; 2888 clock-names = "clk", "hclk"; 2889 dmas = <&dmac1 8>; 2890 dma-names = "tx"; 2891 #sound-dai-cells = <0>; 2892 rockchip,sample-width-bits = <11>; 2893 rockchip,interpolat-points = <1>; 2894 status = "disabled"; 2895 }; 2896 2897 dig_acodec: codec-digital@fe478000 { 2898 compatible = "rockchip,rk3568-codec-digital", "rockchip,codec-digital-v1"; 2899 reg = <0x0 0xfe478000 0x0 0x1000>; 2900 clocks = <&cru CLK_ACDCDIG_ADC>, <&cru CLK_ACDCDIG_DAC>, 2901 <&cru CLK_ACDCDIG_I2C>, <&cru HCLK_ACDCDIG>; 2902 clock-names = "adc", "dac", "i2c", "pclk"; 2903 pinctrl-names = "default"; 2904 pinctrl-0 = <&acodec_pins>; 2905 resets = <&cru SRST_ACDCDIG>; 2906 reset-names = "reset" ; 2907 rockchip,grf = <&grf>; 2908 #sound-dai-cells = <0>; 2909 status = "disabled"; 2910 }; 2911 2912 dmac0: dmac@fe530000 { 2913 compatible = "arm,pl330", "arm,primecell"; 2914 reg = <0x0 0xfe530000 0x0 0x4000>; 2915 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 2916 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2917 clocks = <&cru ACLK_BUS>; 2918 clock-names = "apb_pclk"; 2919 #dma-cells = <1>; 2920 arm,pl330-periph-burst; 2921 }; 2922 2923 dmac1: dmac@fe550000 { 2924 compatible = "arm,pl330", "arm,primecell"; 2925 reg = <0x0 0xfe550000 0x0 0x4000>; 2926 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 2927 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 2928 clocks = <&cru ACLK_BUS>; 2929 clock-names = "apb_pclk"; 2930 #dma-cells = <1>; 2931 arm,pl330-periph-burst; 2932 }; 2933 2934 scr: rkscr@fe560000 { 2935 compatible = "rockchip-scr"; 2936 reg = <0x0 0xfe560000 0x0 0x10000>; 2937 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2938 pinctrl-names = "default"; 2939 pinctrl-0 = <&scr_pins>; 2940 clocks = <&cru PCLK_SCR>; 2941 clock-names = "g_pclk_sim_card"; 2942 status = "disabled"; 2943 }; 2944 2945 can0: can@fe570000 { 2946 compatible = "forlinx,rk3568-can-2.0"; // Can also use rockchip,rk3568-can-2.0 with rockchip_canfd.o 2947 reg = <0x0 0xfe570000 0x0 0x1000>; // Default uses forlinx,rk3568-can-2.0 with forlinx_canfd.lo 2948 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; // Forlinx optimized the problem of ID and data mismatch 2949 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; // by manic 2950 clock-names = "baudclk", "apb_pclk"; 2951 resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>; 2952 reset-names = "can", "can-apb"; 2953 tx-fifo-depth = <1>; 2954 rx-fifo-depth = <6>; 2955 rockchip,tx-invalid-info = <0x40 0x0 0x0 0x0>; 2956 status = "disabled"; 2957 }; 2958 2959 can1: can@fe580000 { 2960 compatible = "forlinx,rk3568-can-2.0"; 2961 reg = <0x0 0xfe580000 0x0 0x1000>; 2962 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 2963 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; 2964 clock-names = "baudclk", "apb_pclk"; 2965 resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>; 2966 reset-names = "can", "can-apb"; 2967 tx-fifo-depth = <1>; 2968 rx-fifo-depth = <6>; 2969 rockchip,tx-invalid-info = <0x40 0x0 0x0 0x0>; 2970 status = "disabled"; 2971 }; 2972 2973 can2: can@fe590000 { 2974 compatible = "forlinx,rk3568-can-2.0"; 2975 reg = <0x0 0xfe590000 0x0 0x1000>; 2976 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 2977 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>; 2978 clock-names = "baudclk", "apb_pclk"; 2979 resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>; 2980 reset-names = "can", "can-apb"; 2981 tx-fifo-depth = <1>; 2982 rx-fifo-depth = <6>; 2983 rockchip,tx-invalid-info = <0x40 0x0 0x0 0x0>; 2984 status = "disabled"; 2985 }; 2986 2987 i2c1: i2c@fe5a0000 { 2988 compatible = "rockchip,rk3399-i2c"; 2989 reg = <0x0 0xfe5a0000 0x0 0x1000>; 2990 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 2991 clock-names = "i2c", "pclk"; 2992 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2993 pinctrl-names = "default"; 2994 pinctrl-0 = <&i2c1_xfer>; 2995 #address-cells = <1>; 2996 #size-cells = <0>; 2997 status = "disabled"; 2998 }; 2999 3000 i2c2: i2c@fe5b0000 { 3001 compatible = "rockchip,rk3399-i2c"; 3002 reg = <0x0 0xfe5b0000 0x0 0x1000>; 3003 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 3004 clock-names = "i2c", "pclk"; 3005 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 3006 pinctrl-names = "default"; 3007 pinctrl-0 = <&i2c2m0_xfer>; 3008 #address-cells = <1>; 3009 #size-cells = <0>; 3010 status = "disabled"; 3011 }; 3012 3013 i2c3: i2c@fe5c0000 { 3014 compatible = "rockchip,rk3399-i2c"; 3015 reg = <0x0 0xfe5c0000 0x0 0x1000>; 3016 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 3017 clock-names = "i2c", "pclk"; 3018 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 3019 pinctrl-names = "default"; 3020 pinctrl-0 = <&i2c3m0_xfer>; 3021 #address-cells = <1>; 3022 #size-cells = <0>; 3023 status = "disabled"; 3024 }; 3025 3026 i2c4: i2c@fe5d0000 { 3027 compatible = "rockchip,rk3399-i2c"; 3028 reg = <0x0 0xfe5d0000 0x0 0x1000>; 3029 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 3030 clock-names = "i2c", "pclk"; 3031 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 3032 pinctrl-names = "default"; 3033 pinctrl-0 = <&i2c4m0_xfer>; 3034 #address-cells = <1>; 3035 #size-cells = <0>; 3036 status = "disabled"; 3037 }; 3038 3039 i2c5: i2c@fe5e0000 { 3040 compatible = "rockchip,rk3399-i2c"; 3041 reg = <0x0 0xfe5e0000 0x0 0x1000>; 3042 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 3043 clock-names = "i2c", "pclk"; 3044 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 3045 pinctrl-names = "default"; 3046 pinctrl-0 = <&i2c5m0_xfer>; 3047 #address-cells = <1>; 3048 #size-cells = <0>; 3049 status = "disabled"; 3050 }; 3051 3052 rktimer: timer@fe5f0000 { 3053 compatible = "rockchip,rk3568-timer", "rockchip,rk3288-timer"; 3054 reg = <0x0 0xfe5f0000 0x0 0x1000>; 3055 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 3056 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; 3057 clock-names = "pclk", "timer"; 3058 }; 3059 3060 wdt: watchdog@fe600000 { 3061 compatible = "snps,dw-wdt"; 3062 reg = <0x0 0xfe600000 0x0 0x100>; 3063 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 3064 clock-names = "tclk", "pclk"; 3065 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 3066 status = "okay"; 3067 }; 3068 3069 spi0: spi@fe610000 { 3070 compatible = "rockchip,rk3066-spi"; 3071 reg = <0x0 0xfe610000 0x0 0x1000>; 3072 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 3073 #address-cells = <1>; 3074 #size-cells = <0>; 3075 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 3076 clock-names = "spiclk", "apb_pclk"; 3077 dmas = <&dmac0 20>, <&dmac0 21>; 3078 dma-names = "tx", "rx"; 3079 pinctrl-names = "default", "high_speed"; 3080 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 3081 pinctrl-1 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins_hs>; 3082 num-cs = <2>; 3083 status = "disabled"; 3084 }; 3085 3086 spi1: spi@fe620000 { 3087 compatible = "rockchip,rk3066-spi"; 3088 reg = <0x0 0xfe620000 0x0 0x1000>; 3089 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 3090 #address-cells = <1>; 3091 #size-cells = <0>; 3092 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 3093 clock-names = "spiclk", "apb_pclk"; 3094 dmas = <&dmac0 22>, <&dmac0 23>; 3095 dma-names = "tx", "rx"; 3096 pinctrl-names = "default", "high_speed"; 3097 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; 3098 pinctrl-1 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins_hs>; 3099 num-cs = <2>; 3100 status = "disabled"; 3101 }; 3102 3103 spi2: spi@fe630000 { 3104 compatible = "rockchip,rk3066-spi"; 3105 reg = <0x0 0xfe630000 0x0 0x1000>; 3106 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 3107 #address-cells = <1>; 3108 #size-cells = <0>; 3109 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 3110 clock-names = "spiclk", "apb_pclk"; 3111 dmas = <&dmac0 24>, <&dmac0 25>; 3112 dma-names = "tx", "rx"; 3113 pinctrl-names = "default", "high_speed"; 3114 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; 3115 pinctrl-1 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins_hs>; 3116 num-cs = <2>; 3117 status = "disabled"; 3118 }; 3119 3120 spi3: spi@fe640000 { 3121 compatible = "rockchip,rk3066-spi"; 3122 reg = <0x0 0xfe640000 0x0 0x1000>; 3123 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3124 #address-cells = <1>; 3125 #size-cells = <0>; 3126 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 3127 clock-names = "spiclk", "apb_pclk"; 3128 dmas = <&dmac0 26>, <&dmac0 27>; 3129 dma-names = "tx", "rx"; 3130 pinctrl-names = "default", "high_speed"; 3131 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; 3132 pinctrl-1 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins_hs>; 3133 num-cs = <2>; 3134 status = "disabled"; 3135 }; 3136 3137 uart1: serial@fe650000 { 3138 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 3139 reg = <0x0 0xfe650000 0x0 0x100>; 3140 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 3141 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 3142 clock-names = "baudclk", "apb_pclk"; 3143 reg-shift = <2>; 3144 reg-io-width = <4>; 3145 dmas = <&dmac0 2>, <&dmac0 3>; 3146 pinctrl-names = "default"; 3147 pinctrl-0 = <&uart1m0_xfer>; 3148 status = "disabled"; 3149 }; 3150 3151 uart2: serial@fe660000 { 3152 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 3153 reg = <0x0 0xfe660000 0x0 0x100>; 3154 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 3155 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 3156 clock-names = "baudclk", "apb_pclk"; 3157 reg-shift = <2>; 3158 reg-io-width = <4>; 3159 dmas = <&dmac0 4>, <&dmac0 5>; 3160 pinctrl-names = "default"; 3161 pinctrl-0 = <&uart2m0_xfer>; 3162 status = "disabled"; 3163 }; 3164 3165 uart3: serial@fe670000 { 3166 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 3167 reg = <0x0 0xfe670000 0x0 0x100>; 3168 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 3169 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 3170 clock-names = "baudclk", "apb_pclk"; 3171 reg-shift = <2>; 3172 reg-io-width = <4>; 3173 dmas = <&dmac0 6>, <&dmac0 7>; 3174 pinctrl-names = "default"; 3175 pinctrl-0 = <&uart3m0_xfer>; 3176 status = "disabled"; 3177 }; 3178 3179 uart4: serial@fe680000 { 3180 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 3181 reg = <0x0 0xfe680000 0x0 0x100>; 3182 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 3183 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 3184 clock-names = "baudclk", "apb_pclk"; 3185 reg-shift = <2>; 3186 reg-io-width = <4>; 3187 dmas = <&dmac0 8>, <&dmac0 9>; 3188 pinctrl-names = "default"; 3189 pinctrl-0 = <&uart4m0_xfer>; 3190 status = "disabled"; 3191 }; 3192 3193 uart5: serial@fe690000 { 3194 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 3195 reg = <0x0 0xfe690000 0x0 0x100>; 3196 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 3197 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 3198 clock-names = "baudclk", "apb_pclk"; 3199 reg-shift = <2>; 3200 reg-io-width = <4>; 3201 dmas = <&dmac0 10>, <&dmac0 11>; 3202 pinctrl-names = "default"; 3203 pinctrl-0 = <&uart5m0_xfer>; 3204 status = "disabled"; 3205 }; 3206 3207 uart6: serial@fe6a0000 { 3208 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 3209 reg = <0x0 0xfe6a0000 0x0 0x100>; 3210 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 3211 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 3212 clock-names = "baudclk", "apb_pclk"; 3213 reg-shift = <2>; 3214 reg-io-width = <4>; 3215 dmas = <&dmac0 12>, <&dmac0 13>; 3216 pinctrl-names = "default"; 3217 pinctrl-0 = <&uart6m0_xfer>; 3218 status = "disabled"; 3219 }; 3220 3221 uart7: serial@fe6b0000 { 3222 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 3223 reg = <0x0 0xfe6b0000 0x0 0x100>; 3224 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 3225 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 3226 clock-names = "baudclk", "apb_pclk"; 3227 reg-shift = <2>; 3228 reg-io-width = <4>; 3229 dmas = <&dmac0 14>, <&dmac0 15>; 3230 pinctrl-names = "default"; 3231 pinctrl-0 = <&uart7m0_xfer>; 3232 status = "disabled"; 3233 }; 3234 3235 uart8: serial@fe6c0000 { 3236 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 3237 reg = <0x0 0xfe6c0000 0x0 0x100>; 3238 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 3239 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 3240 clock-names = "baudclk", "apb_pclk"; 3241 reg-shift = <2>; 3242 reg-io-width = <4>; 3243 dmas = <&dmac0 16>, <&dmac0 17>; 3244 pinctrl-names = "default"; 3245 pinctrl-0 = <&uart8m0_xfer>; 3246 status = "disabled"; 3247 }; 3248 3249 uart9: serial@fe6d0000 { 3250 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 3251 reg = <0x0 0xfe6d0000 0x0 0x100>; 3252 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 3253 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 3254 clock-names = "baudclk", "apb_pclk"; 3255 reg-shift = <2>; 3256 reg-io-width = <4>; 3257 dmas = <&dmac0 18>, <&dmac0 19>; 3258 pinctrl-names = "default"; 3259 pinctrl-0 = <&uart9m0_xfer>; 3260 status = "disabled"; 3261 }; 3262 3263 pwm4: pwm@fe6e0000 { 3264 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 3265 reg = <0x0 0xfe6e0000 0x0 0x10>; 3266 #pwm-cells = <3>; 3267 pinctrl-names = "active"; 3268 pinctrl-0 = <&pwm4_pins>; 3269 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 3270 clock-names = "pwm", "pclk"; 3271 status = "disabled"; 3272 }; 3273 3274 pwm5: pwm@fe6e0010 { 3275 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 3276 reg = <0x0 0xfe6e0010 0x0 0x10>; 3277 #pwm-cells = <3>; 3278 pinctrl-names = "active"; 3279 pinctrl-0 = <&pwm5_pins>; 3280 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 3281 clock-names = "pwm", "pclk"; 3282 status = "disabled"; 3283 }; 3284 3285 pwm6: pwm@fe6e0020 { 3286 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 3287 reg = <0x0 0xfe6e0020 0x0 0x10>; 3288 #pwm-cells = <3>; 3289 pinctrl-names = "active"; 3290 pinctrl-0 = <&pwm6_pins>; 3291 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 3292 clock-names = "pwm", "pclk"; 3293 status = "disabled"; 3294 }; 3295 3296 pwm7: pwm@fe6e0030 { 3297 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 3298 reg = <0x0 0xfe6e0030 0x0 0x10>; 3299 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 3300 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 3301 #pwm-cells = <3>; 3302 pinctrl-names = "active"; 3303 pinctrl-0 = <&pwm7_pins>; 3304 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 3305 clock-names = "pwm", "pclk"; 3306 status = "disabled"; 3307 }; 3308 3309 pwm8: pwm@fe6f0000 { 3310 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 3311 reg = <0x0 0xfe6f0000 0x0 0x10>; 3312 #pwm-cells = <3>; 3313 pinctrl-names = "active"; 3314 pinctrl-0 = <&pwm8m0_pins>; 3315 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 3316 clock-names = "pwm", "pclk"; 3317 status = "disabled"; 3318 }; 3319 3320 pwm9: pwm@fe6f0010 { 3321 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 3322 reg = <0x0 0xfe6f0010 0x0 0x10>; 3323 #pwm-cells = <3>; 3324 pinctrl-names = "active"; 3325 pinctrl-0 = <&pwm9m0_pins>; 3326 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 3327 clock-names = "pwm", "pclk"; 3328 status = "disabled"; 3329 }; 3330 3331 pwm10: pwm@fe6f0020 { 3332 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 3333 reg = <0x0 0xfe6f0020 0x0 0x10>; 3334 #pwm-cells = <3>; 3335 pinctrl-names = "active"; 3336 pinctrl-0 = <&pwm10m0_pins>; 3337 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 3338 clock-names = "pwm", "pclk"; 3339 status = "disabled"; 3340 }; 3341 3342 pwm11: pwm@fe6f0030 { 3343 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 3344 reg = <0x0 0xfe6f0030 0x0 0x10>; 3345 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 3346 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 3347 #pwm-cells = <3>; 3348 pinctrl-names = "active"; 3349 pinctrl-0 = <&pwm11m0_pins>; 3350 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 3351 clock-names = "pwm", "pclk"; 3352 status = "disabled"; 3353 }; 3354 3355 pwm12: pwm@fe700000 { 3356 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 3357 reg = <0x0 0xfe700000 0x0 0x10>; 3358 #pwm-cells = <3>; 3359 pinctrl-names = "active"; 3360 pinctrl-0 = <&pwm12m0_pins>; 3361 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 3362 clock-names = "pwm", "pclk"; 3363 status = "disabled"; 3364 }; 3365 3366 pwm13: pwm@fe700010 { 3367 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 3368 reg = <0x0 0xfe700010 0x0 0x10>; 3369 #pwm-cells = <3>; 3370 pinctrl-names = "active"; 3371 pinctrl-0 = <&pwm13m0_pins>; 3372 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 3373 clock-names = "pwm", "pclk"; 3374 status = "disabled"; 3375 }; 3376 3377 pwm14: pwm@fe700020 { 3378 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 3379 reg = <0x0 0xfe700020 0x0 0x10>; 3380 #pwm-cells = <3>; 3381 pinctrl-names = "active"; 3382 pinctrl-0 = <&pwm14m0_pins>; 3383 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 3384 clock-names = "pwm", "pclk"; 3385 status = "disabled"; 3386 }; 3387 3388 pwm15: pwm@fe700030 { 3389 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 3390 reg = <0x0 0xfe700030 0x0 0x10>; 3391 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 3392 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 3393 #pwm-cells = <3>; 3394 pinctrl-names = "active"; 3395 pinctrl-0 = <&pwm15m0_pins>; 3396 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 3397 clock-names = "pwm", "pclk"; 3398 status = "disabled"; 3399 }; 3400 3401 tsadc: tsadc@fe710000 { 3402 compatible = "rockchip,rk3568-tsadc"; 3403 reg = <0x0 0xfe710000 0x0 0x100>; 3404 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 3405 rockchip,grf = <&grf>; 3406 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 3407 clock-names = "tsadc", "apb_pclk"; 3408 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; 3409 assigned-clock-rates = <17000000>, <700000>; 3410 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, 3411 <&cru SRST_TSADCPHY>; 3412 reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; 3413 #thermal-sensor-cells = <1>; 3414 nvmem-cells = <&tsadc_trim_base>, <&tsadc_trim_base_frac>; 3415 nvmem-cell-names = "trim_base", "trim_base_frac"; 3416 rockchip,hw-tshut-temp = <125000>; 3417 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 3418 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 3419 pinctrl-names = "gpio", "otpout"; 3420 pinctrl-0 = <&tsadc_gpio_func>; 3421 pinctrl-1 = <&tsadc_shutorg>; 3422 #address-cells = <1>; 3423 #size-cells = <0>; 3424 status = "disabled"; 3425 3426 tsadc@0 { 3427 reg = <0>; 3428 nvmem-cells = <&cpu_tsadc_trim_l>, <&cpu_tsadc_trim_h>; 3429 nvmem-cell-names = "trim_l", "trim_h"; 3430 }; 3431 tsadc@1 { 3432 reg = <1>; 3433 nvmem-cells = <&gpu_tsadc_trim_l>, <&gpu_tsadc_trim_h>; 3434 nvmem-cell-names = "trim_l", "trim_h"; 3435 }; 3436 }; 3437 3438 saradc: saradc@fe720000 { 3439 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; 3440 reg = <0x0 0xfe720000 0x0 0x100>; 3441 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 3442 #io-channel-cells = <1>; 3443 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 3444 clock-names = "saradc", "apb_pclk"; 3445 resets = <&cru SRST_P_SARADC>; 3446 reset-names = "saradc-apb"; 3447 status = "disabled"; 3448 }; 3449 3450 mailbox: mailbox@fe780000 { 3451 compatible = "rockchip,rk3568-mailbox", 3452 "rockchip,rk3368-mailbox"; 3453 reg = <0x0 0xfe780000 0x0 0x1000>; 3454 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3455 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3456 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3457 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 3458 clocks = <&cru PCLK_MAILBOX>; 3459 clock-names = "pclk_mailbox"; 3460 #mbox-cells = <1>; 3461 status = "disabled"; 3462 }; 3463 3464 combphy0_us: phy@fe820000 { 3465 compatible = "rockchip,rk3568-naneng-combphy"; 3466 reg = <0x0 0xfe820000 0x0 0x100>; 3467 #phy-cells = <1>; 3468 clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>, 3469 <&cru PCLK_PIPE>; 3470 clock-names = "refclk", "apbclk", "pipe_clk"; 3471 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; 3472 assigned-clock-rates = <100000000>; 3473 resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; 3474 reset-names = "combphy-apb", "combphy"; 3475 rockchip,pipe-grf = <&pipegrf>; 3476 rockchip,pipe-phy-grf = <&pipe_phy_grf0>; 3477 status = "disabled"; 3478 }; 3479 3480 combphy1_usq: phy@fe830000 { 3481 compatible = "rockchip,rk3568-naneng-combphy"; 3482 reg = <0x0 0xfe830000 0x0 0x100>; 3483 #phy-cells = <1>; 3484 clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>, 3485 <&cru PCLK_PIPE>; 3486 clock-names = "refclk", "apbclk", "pipe_clk"; 3487 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; 3488 assigned-clock-rates = <100000000>; 3489 resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>; 3490 reset-names = "combphy-apb", "combphy"; 3491 rockchip,pipe-grf = <&pipegrf>; 3492 rockchip,pipe-phy-grf = <&pipe_phy_grf1>; 3493 status = "disabled"; 3494 }; 3495 3496 combphy2_psq: phy@fe840000 { 3497 compatible = "rockchip,rk3568-naneng-combphy"; 3498 reg = <0x0 0xfe840000 0x0 0x100>; 3499 #phy-cells = <1>; 3500 clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>, 3501 <&cru PCLK_PIPE>; 3502 clock-names = "refclk", "apbclk", "pipe_clk"; 3503 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; 3504 assigned-clock-rates = <100000000>; 3505 resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>; 3506 reset-names = "combphy-apb", "combphy"; 3507 rockchip,pipe-grf = <&pipegrf>; 3508 rockchip,pipe-phy-grf = <&pipe_phy_grf2>; 3509 status = "disabled"; 3510 }; 3511 3512 video_phy0: phy@fe850000 { 3513 compatible = "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy"; 3514 reg = <0x0 0xfe850000 0x0 0x10000>, 3515 <0x0 0xfe060000 0x0 0x10000>; 3516 reg-names = "phy", "host"; 3517 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, 3518 <&cru PCLK_MIPIDSIPHY0>, <&cru PCLK_DSITX_0>; 3519 clock-names = "ref", "pclk", "pclk_host"; 3520 #clock-cells = <0>; 3521 resets = <&cru SRST_P_MIPIDSIPHY0>; 3522 reset-names = "apb"; 3523 power-domains = <&power RK3568_PD_VO>; 3524 #phy-cells = <0>; 3525 status = "disabled"; 3526 }; 3527 3528 video_phy1: phy@fe860000 { 3529 compatible = "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy"; 3530 reg = <0x0 0xfe860000 0x0 0x10000>, 3531 <0x0 0xfe070000 0x0 0x10000>; 3532 reg-names = "phy", "host"; 3533 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, 3534 <&cru PCLK_MIPIDSIPHY1>, <&cru PCLK_DSITX_1>; 3535 clock-names = "ref", "pclk", "pclk_host"; 3536 #clock-cells = <0>; 3537 resets = <&cru SRST_P_MIPIDSIPHY1>; 3538 reset-names = "apb"; 3539 power-domains = <&power RK3568_PD_VO>; 3540 #phy-cells = <0>; 3541 status = "disabled"; 3542 }; 3543 3544 csi2_dphy_hw: csi2-dphy-hw@fe870000 { 3545 compatible = "rockchip,rk3568-csi2-dphy-hw"; 3546 reg = <0x0 0xfe870000 0x0 0x1000>; 3547 clocks = <&cru PCLK_MIPICSIPHY>; 3548 clock-names = "pclk"; 3549 rockchip,grf = <&grf>; 3550 status = "disabled"; 3551 }; 3552 3553 /* 3554 * csi2_dphy0: used for csi2 dphy full mode, 3555 is mutually exclusive with 3556 csi2_dphy1 and csi2_dphy2 3557 * csi2_dphy1: used for csi2 dphy split mode, 3558 physical lanes use lane0 and lane1, 3559 can be used with csi2_dphy2 parallel 3560 * csi2_dphy2: used for csi2 dphy split mode, 3561 physical lanes use lane2 and lane3, 3562 can be used with csi2_dphy1 parallel 3563 */ 3564 csi2_dphy0: csi2-dphy0 { 3565 compatible = "rockchip,rk3568-csi2-dphy"; 3566 rockchip,hw = <&csi2_dphy_hw>; 3567 status = "disabled"; 3568 }; 3569 3570 csi2_dphy1: csi2-dphy1 { 3571 compatible = "rockchip,rk3568-csi2-dphy"; 3572 rockchip,hw = <&csi2_dphy_hw>; 3573 status = "disabled"; 3574 }; 3575 3576 csi2_dphy2: csi2-dphy2 { 3577 compatible = "rockchip,rk3568-csi2-dphy"; 3578 rockchip,hw = <&csi2_dphy_hw>; 3579 status = "disabled"; 3580 }; 3581 3582 usb2phy0: usb2-phy@fe8a0000 { 3583 compatible = "rockchip,rk3568-usb2phy"; 3584 reg = <0x0 0xfe8a0000 0x0 0x10000>; 3585 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 3586 clocks = <&pmucru CLK_USBPHY0_REF>; 3587 clock-names = "phyclk"; 3588 #clock-cells = <0>; 3589 assigned-clocks = <&cru USB480M>; 3590 assigned-clock-parents = <&usb2phy0>; 3591 clock-output-names = "usb480m_phy"; 3592 rockchip,usbgrf = <&usb2phy0_grf>; 3593 status = "disabled"; 3594 3595 u2phy0_host: host-port { 3596 #phy-cells = <0>; 3597 status = "disabled"; 3598 }; 3599 3600 u2phy0_otg: otg-port { 3601 #phy-cells = <0>; 3602 status = "disabled"; 3603 }; 3604 }; 3605 3606 usb2phy1: usb2-phy@fe8b0000 { 3607 compatible = "rockchip,rk3568-usb2phy"; 3608 reg = <0x0 0xfe8b0000 0x0 0x10000>; 3609 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 3610 clocks = <&pmucru CLK_USBPHY1_REF>; 3611 clock-names = "phyclk"; 3612 #clock-cells = <0>; 3613 rockchip,usbgrf = <&usb2phy1_grf>; 3614 status = "disabled"; 3615 3616 u2phy1_host: host-port { 3617 #phy-cells = <0>; 3618 status = "disabled"; 3619 }; 3620 3621 u2phy1_otg: otg-port { 3622 #phy-cells = <0>; 3623 status = "disabled"; 3624 }; 3625 }; 3626 3627 pcie30phy: phy@fe8c0000 { 3628 compatible = "rockchip,rk3568-pcie3-phy"; 3629 reg = <0x0 0xfe8c0000 0x0 0x20000>; 3630 #phy-cells = <0>; 3631 clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, 3632 <&cru PCLK_PCIE30PHY>; 3633 clock-names = "refclk_m", "refclk_n", "pclk"; 3634 resets = <&cru SRST_PCIE30PHY>; 3635 reset-names = "phy"; 3636 rockchip,phy-grf = <&pcie30_phy_grf>; 3637 status = "disabled"; 3638 }; 3639 3640 pinctrl: pinctrl { 3641 compatible = "rockchip,rk3568-pinctrl"; 3642 rockchip,grf = <&grf>; 3643 rockchip,pmu = <&pmugrf>; 3644 #address-cells = <2>; 3645 #size-cells = <2>; 3646 ranges; 3647 3648 gpio0: gpio0@fdd60000 { 3649 compatible = "rockchip,gpio-bank"; 3650 reg = <0x0 0xfdd60000 0x0 0x100>; 3651 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3652 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 3653 3654 gpio-controller; 3655 #gpio-cells = <2>; 3656 interrupt-controller; 3657 #interrupt-cells = <2>; 3658 }; 3659 3660 gpio1: gpio1@fe740000 { 3661 compatible = "rockchip,gpio-bank"; 3662 reg = <0x0 0xfe740000 0x0 0x100>; 3663 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 3664 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 3665 3666 gpio-controller; 3667 #gpio-cells = <2>; 3668 interrupt-controller; 3669 #interrupt-cells = <2>; 3670 }; 3671 3672 gpio2: gpio2@fe750000 { 3673 compatible = "rockchip,gpio-bank"; 3674 reg = <0x0 0xfe750000 0x0 0x100>; 3675 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 3676 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 3677 3678 gpio-controller; 3679 #gpio-cells = <2>; 3680 interrupt-controller; 3681 #interrupt-cells = <2>; 3682 }; 3683 3684 gpio3: gpio3@fe760000 { 3685 compatible = "rockchip,gpio-bank"; 3686 reg = <0x0 0xfe760000 0x0 0x100>; 3687 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3688 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 3689 3690 gpio-controller; 3691 #gpio-cells = <2>; 3692 interrupt-controller; 3693 #interrupt-cells = <2>; 3694 }; 3695 3696 gpio4: gpio4@fe770000 { 3697 compatible = "rockchip,gpio-bank"; 3698 reg = <0x0 0xfe770000 0x0 0x100>; 3699 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3700 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 3701 3702 gpio-controller; 3703 #gpio-cells = <2>; 3704 interrupt-controller; 3705 #interrupt-cells = <2>; 3706 }; 3707 }; 3708}; 3709 3710#include "rk3568-pinctrl.dtsi" 3711
