xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3568-nvr-demo-v10.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
4 *
5 */
6
7/dts-v1/;
8
9#include "rk3568-nvr.dtsi"
10#include <dt-bindings/clock/rk618-cru.h>
11
12/ {
13	model = "Rockchip RK3568 NVR DEMO V10 Board";
14	compatible = "rockchip,rk3568-nvr-demo-v10", "rockchip,rk3568";
15
16	gpio-leds {
17		compatible = "gpio-leds";
18
19		hdd-led {
20			gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
21			default-state = "off";
22		};
23		net-led {
24			gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
25			default-state = "off";
26		};
27		work-led {
28			gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
29			linux,default-trigger = "timer";
30		};
31	};
32
33	i2s1_sound: i2s1-sound {
34		status = "okay";
35		compatible = "simple-audio-card";
36		simple-audio-card,format = "i2s";
37		simple-audio-card,mclk-fs = <256>;
38		simple-audio-card,name = "rockchip,i2s1-sound";
39		simple-audio-card,cpu {
40			sound-dai = <&i2s1_8ch>;
41		};
42		simple-audio-card,codec {
43			sound-dai = <&es8311>;
44		};
45	};
46
47	vcc2v5_sys: vcc2v5-ddr {
48		compatible = "regulator-fixed";
49		regulator-name = "vcc2v5-sys";
50		regulator-always-on;
51		regulator-boot-on;
52		regulator-min-microvolt = <2500000>;
53		regulator-max-microvolt = <2500000>;
54		vin-supply = <&vcc3v3_sys>;
55	};
56
57	vcc3v3_pcie: gpio-regulator {
58		compatible = "regulator-fixed";
59		regulator-name = "vcc3v3_pcie";
60		regulator-min-microvolt = <3300000>;
61		regulator-max-microvolt = <3300000>;
62		gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
63		startup-delay-us = <5000>;
64		vin-supply = <&dc_12v>;
65	};
66
67	pcie30_avdd0v9: pcie30-avdd0v9 {
68		compatible = "regulator-fixed";
69		regulator-name = "pcie30_avdd0v9";
70		regulator-always-on;
71		regulator-boot-on;
72		regulator-min-microvolt = <900000>;
73		regulator-max-microvolt = <900000>;
74		vin-supply = <&vcc3v3_sys>;
75	};
76
77	pcie30_avdd1v8: pcie30-avdd1v8 {
78		compatible = "regulator-fixed";
79		regulator-name = "pcie30_avdd1v8";
80		regulator-always-on;
81		regulator-boot-on;
82		regulator-min-microvolt = <1800000>;
83		regulator-max-microvolt = <1800000>;
84		vin-supply = <&vcc3v3_sys>;
85	};
86
87	vcc3v3_bu: vcc3v3-bu {
88		compatible = "regulator-fixed";
89		regulator-name = "vcc3v3_bu";
90		regulator-always-on;
91		regulator-boot-on;
92		regulator-min-microvolt = <3300000>;
93		regulator-max-microvolt = <3300000>;
94		vin-supply = <&vcc5v0_sys>;
95	};
96};
97
98&combphy1_usq {
99	pinctrl-names = "default";
100	pinctrl-0 = <&sata_pm_reset>;
101	rockchip,dis-u3otg1-port;
102	status = "okay";
103};
104
105&combphy2_psq{
106	status = "okay";
107};
108
109&gmac0 {
110	phy-mode = "rgmii";
111	clock_in_out = "output";
112
113	snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
114	snps,reset-active-low;
115	/* Reset time is 20ms, 100ms for rtl8211f */
116	snps,reset-delays-us = <0 20000 100000>;
117
118	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
119	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
120	assigned-clock-rates = <0>, <125000000>;
121
122	pinctrl-names = "default";
123	pinctrl-0 = <&gmac0_miim
124		     &gmac0_tx_bus2
125		     &gmac0_rx_bus2
126		     &gmac0_rgmii_clk
127		     &gmac0_rgmii_bus>;
128
129	tx_delay = <0x43>;
130	rx_delay = <0x33>;
131
132	phy-handle = <&rgmii_phy0>;
133	status = "okay";
134};
135
136&gmac1 {
137	phy-mode = "rgmii";
138	clock_in_out = "output";
139
140	snps,reset-gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
141	snps,reset-active-low;
142	/* Reset time is 20ms, 100ms for rtl8211f */
143	snps,reset-delays-us = <0 20000 100000>;
144
145	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
146	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
147	assigned-clock-rates = <0>, <125000000>;
148
149	pinctrl-names = "default";
150	pinctrl-0 = <&gmac1m1_miim
151		     &gmac1m1_tx_bus2
152		     &gmac1m1_rx_bus2
153		     &gmac1m1_rgmii_clk
154		     &gmac1m1_rgmii_bus>;
155
156	tx_delay = <0x4f>;
157	rx_delay = <0x2d>;
158
159	phy-handle = <&rgmii_phy1>;
160	status = "okay";
161};
162
163&i2c1 {
164	status = "okay";
165	hym8563: hym8563@51 {
166		compatible = "haoyu,hym8563";
167		reg = <0x51>;
168
169		pinctrl-names = "default";
170		pinctrl-0 = <&rtc_int>;
171
172		interrupt-parent = <&gpio0>;
173		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
174	};
175};
176
177&i2c3 {
178	status = "okay";
179	clock-frequency = <400000>;
180
181	es8311: es8311@18 {
182		compatible = "everest,es8311";
183		reg = <0x18>;
184		clocks = <&cru I2S1_MCLKOUT>;
185		clock-names = "mclk";
186		adc-pga-gain = <6>;	/* 18dB */
187		adc-volume = <0xbf>;	/* 0dB */
188		dac-volume = <0xbf>;	/* 0dB */
189		aec-mode = "dac left, adc right";
190		pinctrl-names = "default";
191		pinctrl-0 = <&i2s1m0_mclk>;
192		assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>;
193		assigned-clock-rates = <12288000>;
194		assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>;
195		spk-ctl-gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>;
196		#sound-dai-cells = <0>;
197	};
198
199	rk618@50 {
200		compatible = "rockchip,rk618";
201		reg = <0x50>;
202		pinctrl-names = "default";
203		pinctrl-0 = <&i2s3m1_mclk &rk618_int>;
204		clocks = <&cru I2S3_MCLKOUT>;
205		clock-names = "clkin";
206		assigned-clocks =<&cru I2S3_MCLKOUT>, <&cru I2S3_MCLK_IOE>;
207		assigned-clock-parents = <&cru I2S3_MCLKOUT_TX>, <&cru I2S3_MCLKOUT>;
208		assigned-clock-rates = <11289600>;
209		reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>;
210		status = "okay";
211
212		clock: cru {
213			compatible = "rockchip,rk618-cru";
214			clocks = <&cru I2S3_MCLKOUT>, <&cru DCLK_VOP2>;
215			clock-names = "clkin", "lcdc0_dclkp";
216			assigned-clocks = <&clock SCALER_PLLIN_CLK>,
217			<&clock VIF_PLLIN_CLK>,
218			<&clock SCALER_CLK>,
219			<&clock VIF0_PRE_CLK>,
220			<&clock CODEC_CLK>,
221			<&clock DITHER_CLK>;
222			assigned-clock-parents = <&cru I2S3_MCLKOUT_TX>,
223			<&clock LCDC0_CLK>,
224			<&clock SCALER_PLL_CLK>,
225			<&clock VIF_PLL_CLK>,
226			<&cru I2S3_MCLKOUT>,
227			<&clock VIF0_CLK>;
228			#clock-cells = <1>;
229			status = "okay";
230		};
231
232		hdmi {
233			compatible = "rockchip,rk618-hdmi";
234			clocks = <&clock HDMI_CLK>;
235			clock-names = "hdmi";
236			assigned-clocks = <&clock HDMI_CLK>;
237			assigned-clock-parents = <&clock VIF0_CLK>;
238			interrupt-parent = <&gpio0>;
239			interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
240			status = "okay";
241
242			ports {
243				#address-cells = <1>;
244				#size-cells = <0>;
245
246				port@0 {
247					reg = <0>;
248
249					hdmi_in_rgb: endpoint {
250						remote-endpoint = <&rgb_out_hdmi>;
251					};
252				};
253			};
254		};
255	};
256};
257
258&mdio0 {
259	rgmii_phy0: phy@0 {
260		compatible = "ethernet-phy-ieee802.3-c22";
261		reg = <0x0>;
262	};
263};
264
265&mdio1 {
266	rgmii_phy1: phy@0 {
267		compatible = "ethernet-phy-ieee802.3-c22";
268		reg = <0x0>;
269	};
270};
271
272&pcie30phy {
273	status = "okay";
274};
275
276&pcie3x1 {
277	reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
278	vpcie3v3-supply = <&vcc3v3_pcie>;
279	status = "okay";
280};
281
282&pcie3x2 {
283	reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
284	vpcie3v3-supply = <&vcc3v3_pcie>;
285	status = "okay";
286};
287
288&pwm15 {
289	compatible = "rockchip,remotectl-pwm";
290	pinctrl-names = "default";
291	pinctrl-0 = <&pwm15m1_pins>;
292	remote_pwm_id = <3>;
293	handle_cpu_id = <1>;
294	remote_support_psci = <0>;
295	status = "okay";
296
297	ir_key1 {
298		rockchip,usercode = <0x4040>;
299		rockchip,key_table =
300			<0xf2	KEY_REPLY>,
301			<0xba	KEY_BACK>,
302			<0xf4	KEY_UP>,
303			<0xf1	KEY_DOWN>,
304			<0xef	KEY_LEFT>,
305			<0xee	KEY_RIGHT>,
306			<0xbd	KEY_HOME>,
307			<0xea	KEY_VOLUMEUP>,
308			<0xe3	KEY_VOLUMEDOWN>,
309			<0xe2	KEY_SEARCH>,
310			<0xb2	KEY_POWER>,
311			<0xbc	KEY_MUTE>,
312			<0xec	KEY_MENU>,
313			<0xbf	0x190>,
314			<0xe0	0x191>,
315			<0xe1	0x192>,
316			<0xe9	183>,
317			<0xe6	248>,
318			<0xe8	185>,
319			<0xe7	186>,
320			<0xf0	388>,
321			<0xbe	0x175>;
322	};
323
324	ir_key2 {
325		rockchip,usercode = <0xff00>;
326		rockchip,key_table =
327			<0xf9	KEY_HOME>,
328			<0xbf	KEY_BACK>,
329			<0xfb	KEY_MENU>,
330			<0xaa	KEY_REPLY>,
331			<0xb9	KEY_UP>,
332			<0xe9	KEY_DOWN>,
333			<0xb8	KEY_LEFT>,
334			<0xea	KEY_RIGHT>,
335			<0xeb	KEY_VOLUMEDOWN>,
336			<0xef	KEY_VOLUMEUP>,
337			<0xf7	KEY_MUTE>,
338			<0xe7	KEY_POWER>,
339			<0xfc	KEY_POWER>,
340			<0xa9	KEY_VOLUMEDOWN>,
341			<0xa8	KEY_PLAYPAUSE>,
342			<0xe0	KEY_VOLUMEDOWN>,
343			<0xa5	KEY_VOLUMEDOWN>,
344			<0xab	183>,
345			<0xb7	388>,
346			<0xe8	388>,
347			<0xf8	184>,
348			<0xaf	185>,
349			<0xed	KEY_VOLUMEDOWN>,
350			<0xee	186>,
351			<0xb3	KEY_VOLUMEDOWN>,
352			<0xf1	KEY_VOLUMEDOWN>,
353			<0xf2	KEY_VOLUMEDOWN>,
354			<0xf3	KEY_SEARCH>,
355			<0xb4	KEY_VOLUMEDOWN>,
356			<0xa4	KEY_SETUP>,
357			<0xbe	KEY_SEARCH>;
358	};
359
360	ir_key3 {
361		rockchip,usercode = <0x1dcc>;
362		rockchip,key_table =
363			<0xee	KEY_REPLY>,
364			<0xf0	KEY_BACK>,
365			<0xf8	KEY_UP>,
366			<0xbb	KEY_DOWN>,
367			<0xef	KEY_LEFT>,
368			<0xed	KEY_RIGHT>,
369			<0xfc	KEY_HOME>,
370			<0xf1	KEY_VOLUMEUP>,
371			<0xfd	KEY_VOLUMEDOWN>,
372			<0xb7	KEY_SEARCH>,
373			<0xff	KEY_POWER>,
374			<0xf3	KEY_MUTE>,
375			<0xbf	KEY_MENU>,
376			<0xf9	0x191>,
377			<0xf5	0x192>,
378			<0xb3	388>,
379			<0xbe	KEY_1>,
380			<0xba	KEY_2>,
381			<0xb2	KEY_3>,
382			<0xbd	KEY_4>,
383			<0xf9	KEY_5>,
384			<0xb1	KEY_6>,
385			<0xfc	KEY_7>,
386			<0xf8	KEY_8>,
387			<0xb0	KEY_9>,
388			<0xb6	KEY_0>,
389			<0xb5	KEY_BACKSPACE>;
390	};
391};
392
393&rgb {
394	status = "okay";
395	pinctrl-names = "default";
396	pinctrl-0 = <&lcdc_ctl>;
397	ports {
398		port@1 {
399			reg = <1>;
400
401			rgb_out_hdmi: endpoint {
402				remote-endpoint = <&hdmi_in_rgb>;
403			};
404		};
405	};
406};
407
408&rgb_in_vp2 {
409	status = "okay";
410};
411
412&sata1 {
413	status = "okay";
414};
415
416&sata2 {
417	status = "okay";
418};
419
420&pinctrl {
421	rk618 {
422		rk618_reset: rk618-reeset {
423			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_output_high>;
424		};
425		rk618_int: rk618-int {
426			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
427		};
428	};
429
430	rtc {
431		rtc_int: rtc-int {
432			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
433		};
434	};
435
436	sata {
437		sata_pm_reset: sata-pm-reset {
438			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>;
439		};
440	};
441};
442