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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_atombios.c569 struct amdgpu_pll *ppll = &adev->clock.ppll[0]; in amdgpu_atombios_get_clock_info() local
576 ppll->reference_freq = in amdgpu_atombios_get_clock_info()
578 ppll->reference_div = 0; in amdgpu_atombios_get_clock_info()
580 ppll->pll_out_min = in amdgpu_atombios_get_clock_info()
582 ppll->pll_out_max = in amdgpu_atombios_get_clock_info()
585 ppll->lcd_pll_out_min = in amdgpu_atombios_get_clock_info()
587 if (ppll->lcd_pll_out_min == 0) in amdgpu_atombios_get_clock_info()
588 ppll->lcd_pll_out_min = ppll->pll_out_min; in amdgpu_atombios_get_clock_info()
589 ppll->lcd_pll_out_max = in amdgpu_atombios_get_clock_info()
591 if (ppll->lcd_pll_out_max == 0) in amdgpu_atombios_get_clock_info()
[all …]
H A Damdgpu_pll.c279 * amdgpu_pll_get_shared_dp_ppll - return the PPLL used by another crtc for DP
283 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
284 * also in DP mode. For DP, a single PPLL can be used for all DP
308 * amdgpu_pll_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
313 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
H A Ddce_v8_0.c2118 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2122 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2123 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2124 * monitors a dedicated PPLL must be used. If a particular board has
2149 /* skip PPLL programming if using ext clock */ in dce_v8_0_pick_pll()
2152 /* use the same PPLL for all DP monitors */ in dce_v8_0_pick_pll()
2158 /* use the same PPLL for all monitors with the same clock */ in dce_v8_0_pick_pll()
2172 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v8_0_pick_pll()
2183 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v8_0_pick_pll()
2499 /* disable the ppll */ in dce_v8_0_crtc_disable()
[all …]
H A Ddce_v11_0.c2261 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2265 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2266 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2267 * monitors a dedicated PPLL must be used. If a particular board has
2328 /* skip PPLL programming if using ext clock */ in dce_v11_0_pick_pll()
2331 /* use the same PPLL for all DP monitors */ in dce_v11_0_pick_pll()
2337 /* use the same PPLL for all monitors with the same clock */ in dce_v11_0_pick_pll()
2350 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v11_0_pick_pll()
2359 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v11_0_pick_pll()
2678 /* disable the ppll */ in dce_v11_0_crtc_disable()
[all …]
H A Datombios_crtc.c837 pll = &adev->clock.ppll[0]; in amdgpu_atombios_crtc_set_pll()
840 pll = &adev->clock.ppll[1]; in amdgpu_atombios_crtc_set_pll()
845 pll = &adev->clock.ppll[2]; in amdgpu_atombios_crtc_set_pll()
H A Ddce_v10_0.c2228 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2232 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2233 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2234 * monitors a dedicated PPLL must be used. If a particular board has
2259 /* skip PPLL programming if using ext clock */ in dce_v10_0_pick_pll()
2262 /* use the same PPLL for all DP monitors */ in dce_v10_0_pick_pll()
2268 /* use the same PPLL for all monitors with the same clock */ in dce_v10_0_pick_pll()
2282 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v10_0_pick_pll()
2599 /* disable the ppll */ in dce_v10_0_crtc_disable()
2662 /* if we can't get a PPLL for a non-DP encoder, fail */ in dce_v10_0_crtc_mode_fixup()
H A Ddce_v6_0.c2133 * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc.
2137 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2138 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2139 * monitors a dedicated PPLL must be used. If a particular board has
2157 /* skip PPLL programming if using ext clock */ in dce_v6_0_pick_pll()
2162 /* use the same PPLL for all monitors with the same clock */ in dce_v6_0_pick_pll()
2174 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v6_0_pick_pll()
2488 /* disable the ppll */ in dce_v6_0_crtc_disable()
2552 /* if we can't get a PPLL for a non-DP encoder, fail */ in dce_v6_0_crtc_mode_fixup()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Datombios_crtc.c1753 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1757 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1758 * also in DP mode. For DP, a single PPLL can be used for all DP
1787 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1792 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1838 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1842 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1843 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1844 * monitors a dedicated PPLL must be used. If a particular board has
1887 /* skip PPLL programming if using ext clock */ in radeon_atom_pick_pll()
[all …]
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3528.c26 * [FRAC PLL]: GPLL, PPLL, DPLL
35 * [PPLL]: normal mode only.
51 RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), /* PPLL */
75 [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3528_PCIE_PLL_CON(32),
127 RK3528_CLK_DUMP(PLL_PPLL, "ppll"),
1359 rate = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], priv->cru, in rk3528_clk_get_rate()
1360 PPLL); in rk3528_clk_get_rate()
1481 ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru, in rk3528_clk_set_rate()
1482 PPLL, rate); in rk3528_clk_set_rate()
1483 priv->ppll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], in rk3528_clk_set_rate()
[all …]
H A Dclk_rk3588.c65 [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128),
86 RK3588_CLK_DUMP(PLL_PPLL, "ppll", true),
1516 priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], in rk3588_clk_get_rate()
1517 priv->cru, PPLL); in rk3588_clk_get_rate()
1554 rate = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], priv->cru, in rk3588_clk_get_rate()
1555 PPLL); in rk3588_clk_get_rate()
1667 priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], in rk3588_clk_set_rate()
1668 priv->cru, PPLL); in rk3588_clk_set_rate()
1701 ret = rockchip_pll_set_rate(&rk3588_pll_clks[PPLL], priv->cru, in rk3588_clk_set_rate()
1702 PPLL, rate); in rk3588_clk_set_rate()
[all …]
H A Dclk_rk3568.c80 [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3568_PMU_PLL_CON(0),
102 RK3568_CLK_DUMP(PLL_PPLL, "ppll", false),
375 printf("%s ppll=%lu\n", __func__, priv->ppll_hz); in rk3568_pmuclk_get_rate()
382 rate = rockchip_pll_get_rate(&rk3568_pll_clks[PPLL], in rk3568_pmuclk_get_rate()
383 priv->pmucru, PPLL); in rk3568_pmuclk_get_rate()
415 printf("%s ppll=%lu\n", __func__, priv->ppll_hz); in rk3568_pmuclk_set_rate()
422 ret = rockchip_pll_set_rate(&rk3568_pll_clks[PPLL], in rk3568_pmuclk_set_rate()
423 priv->pmucru, PPLL, rate); in rk3568_pmuclk_set_rate()
424 priv->ppll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[PPLL], in rk3568_pmuclk_set_rate()
425 priv->pmucru, PPLL); in rk3568_pmuclk_set_rate()
[all …]
H A Dclk_rk1808.c63 RK1808_CLK_DUMP(PLL_PPLL, "ppll", true),
90 [PPLL] = PLL(pll_rk3036, PLL_PPLL, RK1808_PMU_PLL_CON(0),
606 pll_rate = rockchip_pll_get_rate(&rk1808_pll_clks[PPLL], in rk1808_mac_set_clk()
607 priv->cru, PPLL); in rk1808_mac_set_clk()
1005 ret = rockchip_pll_set_rate(&rk1808_pll_clks[PPLL], in rk1808_clk_set_rate()
1006 priv->cru, PPLL, rate); in rk1808_clk_set_rate()
/OK3568_Linux_fs/u-boot/drivers/video/
H A Dati_radeon_fb.c218 /* We still have to force a switch to selected PPLL div thanks to in radeon_write_pll_regs()
232 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ in radeon_write_pll_regs()
235 /* Reset PPLL & enable atomic update */ in radeon_write_pll_regs()
240 /* Switch to selected PPLL divider */ in radeon_write_pll_regs()
245 /* Set PPLL ref. div */ in radeon_write_pll_regs()
264 /* Set PPLL divider 3 & post divider*/ in radeon_write_pll_regs()
290 /* Switch back VCLK source to PPLL */ in radeon_write_pll_regs()
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-rk3399.c23 ppll, enumerator
152 PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "dummy_cpll", "gpll", "ppll" };
156 "ppll" };
161 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "dummy_cpll", "gpll",
166 "ppll", "upll", "xin24m" };
206 PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" };
210 "ppll" };
215 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll",
220 "ppll", "upll", "xin24m" };
283 PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" };
[all …]
H A Dclk-rk3528.c20 apll, cpll, gpll, ppll, dpll, enumerator
26 * [FRAC PLL]: GPLL, PPLL, DPLL
35 * [PPLL]: normal mode only.
57 RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), /* PPLL */
186 [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p,
971 COMPOSITE_NOMUX(CLK_GMAC1_VPU_25M, "clk_gmac1_25m", "ppll", 0,
974 COMPOSITE_NOMUX(CLK_PPLL_125M_MATRIX, "clk_ppll_125m_src", "ppll", 0,
1046 COMPOSITE_NOMUX(CLK_PPLL_100M_MATRIX, "clk_ppll_100m_src", "ppll", CLK_IS_CRITICAL,
1049 COMPOSITE_NOMUX(CLK_PPLL_50M_MATRIX, "clk_ppll_50m_src", "ppll", CLK_IS_CRITICAL,
H A Dclk-rk1808.c24 apll, dpll, cpll, gpll, npll, ppll, enumerator
148 PNAME(mux_cpll_npll_ppll_p) = { "cpll", "npll", "ppll" };
175 PNAME(mux_gpll_usb480m_cpll_ppll_p) = { "gpll", "usb480m", "cpll", "ppll" };
180 PNAME(mux_ppll_xin24m_p) = { "ppll", "xin24m" };
200 [ppll] = PLL(pll_rk3036, PLL_PPLL, "ppll", mux_pll_p,
1083 COMPOSITE_NOMUX(0, "clk_wifi_pmu_src", "ppll", 0,
1114 COMPOSITE_NOMUX(SCLK_REF24M_PMU, "clk_ref24m_pmu", "ppll", 0,
1124 FACTOR(0, "clk_ppll_ph0", "ppll", 0, 1, 2),
1132 COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "ppll", CLK_IS_CRITICAL,
H A Dclk-rk3588.c22 b0pll, b1pll, lpll, v0pll, aupll, cpll, gpll, npll, ppll, enumerator
512 PNAME(mux_24m_ppll_spll_p) = { "xin24m", "ppll", "spll" };
513 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
671 [ppll] = PLL(pll_rk3588_core, PLL_PPLL, "ppll", mux_pll_p,
2114 COMPOSITE_NOMUX(CLK_REF_PIPE_PHY0_PLL_SRC, "clk_ref_pipe_phy0_pll_src", "ppll", 0,
2117 COMPOSITE_NOMUX(CLK_REF_PIPE_PHY1_PLL_SRC, "clk_ref_pipe_phy1_pll_src", "ppll", 0,
2120 COMPOSITE_NOMUX(CLK_REF_PIPE_PHY2_PLL_SRC, "clk_ref_pipe_phy2_pll_src", "ppll", 0,
2257 GATE(CLK_PHY0_REF_ALT_P, "clk_phy0_ref_alt_p", "ppll", 0,
2259 GATE(CLK_PHY0_REF_ALT_M, "clk_phy0_ref_alt_m", "ppll", 0,
2261 GATE(CLK_PHY1_REF_ALT_P, "clk_phy1_ref_alt_p", "ppll", 0,
[all …]
H A Dclk-rk3568.c27 ppll, hpll, enumerator
288 PNAME(ppll_usb480m_cpll_gpll_p) = { "ppll", "usb480m", "cpll", "gpll"};
306 PNAME(clk_pdpmu_p) = { "ppll", "gpll" };
307 PNAME(clk_mac_2top_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" };
320 [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p,
1484 FACTOR(0, "ppll_ph0", "ppll", 0, 1, 2),
1485 FACTOR(0, "ppll_ph180", "ppll", 0, 1, 2),
/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk-imx35.c61 static const char *std_sel[] = {"ppll", "arm"};
65 /* 0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, enumerator
110 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); in _mx35_clocks_init()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/include/
H A Dbios_parser_types.h206 * other ppll params */
209 * other ppll params */
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dimx35-clock.yaml21 ppll 2
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dxlnx-versal-clk.h19 #define PPLL 10 macro
/OK3568_Linux_fs/kernel/drivers/video/fbdev/aty/
H A Dradeon_base.c1364 /* We still have to force a switch to selected PPLL div thanks to in radeon_write_pll_regs()
1376 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ in radeon_write_pll_regs()
1379 /* Reset PPLL & enable atomic update */ in radeon_write_pll_regs()
1384 /* Switch to selected PPLL divider */ in radeon_write_pll_regs()
1391 /* Set PPLL ref. div */ in radeon_write_pll_regs()
1410 /* Set PPLL divider 3 & post divider*/ in radeon_write_pll_regs()
1436 /* Switch back VCLK source to PPLL */ in radeon_write_pll_regs()
1825 /* Calculate PPLL value if necessary */ in radeonfb_set_par()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk1808.h25 PPLL, enumerator
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/
H A Datombios.h1820 // 0 means disable PPLL
1827 UCHAR ucCRTC; // Which CRTC uses this Ppll
1840 // 0 means disable PPLL
1847 UCHAR ucCRTC; // Which CRTC uses this Ppll
1887 … // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
1900 … // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
1917 // 0 means disable PPLL/DCPLL.
1925 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1928 // bit[4]= RefClock source for PPLL.
1951 … // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
[all …]

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