Lines Matching full:ppll
26 * [FRAC PLL]: GPLL, PPLL, DPLL
35 * [PPLL]: normal mode only.
51 RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), /* PPLL */
75 [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3528_PCIE_PLL_CON(32),
127 RK3528_CLK_DUMP(PLL_PPLL, "ppll"),
1359 rate = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], priv->cru, in rk3528_clk_get_rate()
1360 PPLL); in rk3528_clk_get_rate()
1481 ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru, in rk3528_clk_set_rate()
1482 PPLL, rate); in rk3528_clk_set_rate()
1483 priv->ppll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], in rk3528_clk_set_rate()
1484 priv->cru, PPLL); in rk3528_clk_set_rate()
1907 ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru, in rk3528_clk_init()
1908 PPLL, PPLL_HZ); in rk3528_clk_init()