1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/imx35-clock.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Clock bindings for Freescale i.MX35 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Steffen Trumtrar <s.trumtrar@pengutronix.de> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun The clock consumer should specify the desired clock by having the clock 14*4882a593Smuzhiyun ID in its "clocks" phandle cell. The following is a full list of i.MX35 15*4882a593Smuzhiyun clocks and IDs. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun Clock ID 18*4882a593Smuzhiyun --------------------------- 19*4882a593Smuzhiyun ckih 0 20*4882a593Smuzhiyun mpll 1 21*4882a593Smuzhiyun ppll 2 22*4882a593Smuzhiyun mpll_075 3 23*4882a593Smuzhiyun arm 4 24*4882a593Smuzhiyun hsp 5 25*4882a593Smuzhiyun hsp_div 6 26*4882a593Smuzhiyun hsp_sel 7 27*4882a593Smuzhiyun ahb 8 28*4882a593Smuzhiyun ipg 9 29*4882a593Smuzhiyun arm_per_div 10 30*4882a593Smuzhiyun ahb_per_div 11 31*4882a593Smuzhiyun ipg_per 12 32*4882a593Smuzhiyun uart_sel 13 33*4882a593Smuzhiyun uart_div 14 34*4882a593Smuzhiyun esdhc_sel 15 35*4882a593Smuzhiyun esdhc1_div 16 36*4882a593Smuzhiyun esdhc2_div 17 37*4882a593Smuzhiyun esdhc3_div 18 38*4882a593Smuzhiyun spdif_sel 19 39*4882a593Smuzhiyun spdif_div_pre 20 40*4882a593Smuzhiyun spdif_div_post 21 41*4882a593Smuzhiyun ssi_sel 22 42*4882a593Smuzhiyun ssi1_div_pre 23 43*4882a593Smuzhiyun ssi1_div_post 24 44*4882a593Smuzhiyun ssi2_div_pre 25 45*4882a593Smuzhiyun ssi2_div_post 26 46*4882a593Smuzhiyun usb_sel 27 47*4882a593Smuzhiyun usb_div 28 48*4882a593Smuzhiyun nfc_div 29 49*4882a593Smuzhiyun asrc_gate 30 50*4882a593Smuzhiyun pata_gate 31 51*4882a593Smuzhiyun audmux_gate 32 52*4882a593Smuzhiyun can1_gate 33 53*4882a593Smuzhiyun can2_gate 34 54*4882a593Smuzhiyun cspi1_gate 35 55*4882a593Smuzhiyun cspi2_gate 36 56*4882a593Smuzhiyun ect_gate 37 57*4882a593Smuzhiyun edio_gate 38 58*4882a593Smuzhiyun emi_gate 39 59*4882a593Smuzhiyun epit1_gate 40 60*4882a593Smuzhiyun epit2_gate 41 61*4882a593Smuzhiyun esai_gate 42 62*4882a593Smuzhiyun esdhc1_gate 43 63*4882a593Smuzhiyun esdhc2_gate 44 64*4882a593Smuzhiyun esdhc3_gate 45 65*4882a593Smuzhiyun fec_gate 46 66*4882a593Smuzhiyun gpio1_gate 47 67*4882a593Smuzhiyun gpio2_gate 48 68*4882a593Smuzhiyun gpio3_gate 49 69*4882a593Smuzhiyun gpt_gate 50 70*4882a593Smuzhiyun i2c1_gate 51 71*4882a593Smuzhiyun i2c2_gate 52 72*4882a593Smuzhiyun i2c3_gate 53 73*4882a593Smuzhiyun iomuxc_gate 54 74*4882a593Smuzhiyun ipu_gate 55 75*4882a593Smuzhiyun kpp_gate 56 76*4882a593Smuzhiyun mlb_gate 57 77*4882a593Smuzhiyun mshc_gate 58 78*4882a593Smuzhiyun owire_gate 59 79*4882a593Smuzhiyun pwm_gate 60 80*4882a593Smuzhiyun rngc_gate 61 81*4882a593Smuzhiyun rtc_gate 62 82*4882a593Smuzhiyun rtic_gate 63 83*4882a593Smuzhiyun scc_gate 64 84*4882a593Smuzhiyun sdma_gate 65 85*4882a593Smuzhiyun spba_gate 66 86*4882a593Smuzhiyun spdif_gate 67 87*4882a593Smuzhiyun ssi1_gate 68 88*4882a593Smuzhiyun ssi2_gate 69 89*4882a593Smuzhiyun uart1_gate 70 90*4882a593Smuzhiyun uart2_gate 71 91*4882a593Smuzhiyun uart3_gate 72 92*4882a593Smuzhiyun usbotg_gate 73 93*4882a593Smuzhiyun wdog_gate 74 94*4882a593Smuzhiyun max_gate 75 95*4882a593Smuzhiyun admux_gate 76 96*4882a593Smuzhiyun csi_gate 77 97*4882a593Smuzhiyun csi_div 78 98*4882a593Smuzhiyun csi_sel 79 99*4882a593Smuzhiyun iim_gate 80 100*4882a593Smuzhiyun gpu2d_gate 81 101*4882a593Smuzhiyun ckli_gate 82 102*4882a593Smuzhiyun 103*4882a593Smuzhiyunproperties: 104*4882a593Smuzhiyun compatible: 105*4882a593Smuzhiyun const: fsl,imx35-ccm 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun reg: 108*4882a593Smuzhiyun maxItems: 1 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun interrupts: 111*4882a593Smuzhiyun maxItems: 1 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun '#clock-cells': 114*4882a593Smuzhiyun const: 1 115*4882a593Smuzhiyun 116*4882a593Smuzhiyunrequired: 117*4882a593Smuzhiyun - compatible 118*4882a593Smuzhiyun - reg 119*4882a593Smuzhiyun - interrupts 120*4882a593Smuzhiyun - '#clock-cells' 121*4882a593Smuzhiyun 122*4882a593SmuzhiyunadditionalProperties: false 123*4882a593Smuzhiyun 124*4882a593Smuzhiyunexamples: 125*4882a593Smuzhiyun - | 126*4882a593Smuzhiyun clock-controller@53f80000 { 127*4882a593Smuzhiyun compatible = "fsl,imx35-ccm"; 128*4882a593Smuzhiyun reg = <0x53f80000 0x4000>; 129*4882a593Smuzhiyun interrupts = <31>; 130*4882a593Smuzhiyun #clock-cells = <1>; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun mmc@53fb4000 { 134*4882a593Smuzhiyun compatible = "fsl,imx35-esdhc"; 135*4882a593Smuzhiyun reg = <0x53fb4000 0x4000>; 136*4882a593Smuzhiyun interrupts = <7>; 137*4882a593Smuzhiyun clocks = <&clks 9>, <&clks 8>, <&clks 43>; 138*4882a593Smuzhiyun clock-names = "ipg", "ahb", "per"; 139*4882a593Smuzhiyun }; 140