clk/rockchip/clk_rk3568.c

80 	[PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3568_PMU_PLL_CON(0),
102 	RK3568_CLK_DUMP(PLL_PPLL, "ppll", false),
375 		printf("%s ppll=%lu\n", __func__, priv->ppll_hz);  in rk3568_pmuclk_get_rate()
382 		rate = rockchip_pll_get_rate(&rk3568_pll_clks[PPLL],  in rk3568_pmuclk_get_rate()
383 					     priv->pmucru, PPLL);  in rk3568_pmuclk_get_rate()
415 		printf("%s ppll=%lu\n", __func__, priv->ppll_hz);  in rk3568_pmuclk_set_rate()
422 		ret = rockchip_pll_set_rate(&rk3568_pll_clks[PPLL],  in rk3568_pmuclk_set_rate()
423 					    priv->pmucru, PPLL, rate);  in rk3568_pmuclk_set_rate()
424 		priv->ppll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[PPLL],  in rk3568_pmuclk_set_rate()
425 						      priv->pmucru, PPLL);  in rk3568_pmuclk_set_rate()
490 		ret = rockchip_pll_set_rate(&rk3568_pll_clks[PPLL],  in rk3568_pmuclk_probe()
492 					    PPLL, PPLL_HZ);  in rk3568_pmuclk_probe()
3267 	priv->ppll_hz = rk3568_pmu_pll_get_rate(priv, PPLL);  in rk3568_clk_init()