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Searched +full:mipi +full:- +full:bias (Results 1 – 25 of 55) sorted by relevance

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/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun6i.h4 * (C) Copyright 2007-2011
8 * SPDX-License-Identifier: GPL-2.0+
31 u32 mipi_pll_cfg; /* 0x40 MIPI pll control */
108 u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */
109 u32 mipi_csi_clk_cfg; /* 0x16c MIPI CSI clock control */
123 u32 pll1_bias_cfg; /* 0x220 PLL1 Bias config */
124 u32 pll2_bias_cfg; /* 0x224 PLL2 Bias config */
125 u32 pll3_bias_cfg; /* 0x228 PLL3 Bias config */
126 u32 pll4_bias_cfg; /* 0x22c PLL4 Bias config */
127 u32 pll5_bias_cfg; /* 0x230 PLL5 Bias config */
[all …]
H A Dclock_sun8i_a83t.h4 * (C) Copyright 2007-2011
10 * SPDX-License-Identifier: GPL-2.0+
72 u32 mipi_csi_clk_cfg; /* 0x130 MIPI CSI module clock */
84 u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */
95 u32 pll1_c0_bias_cfg; /* 0x220 PLL1 c0cpu# Bias config */
96 u32 pll2_bias_cfg; /* 0x224 PLL2 audio Bias config */
97 u32 pll3_bias_cfg; /* 0x228 PLL3 video Bias config */
98 u32 pll4_bias_cfg; /* 0x22c PLL4 ve Bias config */
99 u32 pll5_bias_cfg; /* 0x230 PLL5 ddr Bias config */
100 u32 pll6_bias_cfg; /* 0x234 PLL6 periph Bias config */
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra20-pmc
18 - nvidia,tegra30-pmc
19 - nvidia,tegra114-pmc
[all …]
H A Dnvidia,tegra186-pmc.txt4 - compatible: Should contain one of the following:
5 - "nvidia,tegra186-pmc": for Tegra186
6 - "nvidia,tegra194-pmc": for Tegra194
7 - "nvidia,tegra234-pmc": for Tegra234
8 - reg: Must contain an (offset, length) pair of the register set for each
9 entry in reg-names.
10 - reg-names: Must include the following entries:
11 - "pmc"
12 - "wake"
13 - "aotag"
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drv1108.dtsi4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/rv1108-cru.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/media/rockchip_mipi_dsi.h>
13 #include <linux/media-bus-format.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
[all …]
H A D.OK3568-C.dtb.dts.tmp
H A D.rv1108-evb.dtb.dts.tmp
H A Drk1808.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <dt-bindings/clock/rk1808-cru.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/power/rk1808-power.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
38 #address-cells = <2>;
[all …]
H A Drk3288.dtsi2 * SPDX-License-Identifier: GPL-2.0+
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3288-cru.h>
10 #include <dt-bindings/power-domain/rk3288.h>
11 #include <dt-bindings/thermal/thermal.h>
12 #include <dt-bindings/video/rk3288.h>
18 interrupt-parent = <&gic>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dqcom-apq8064-ifc6410.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include "qcom-apq8064-v2.0.dtsi"
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
8 compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
21 stdout-path = "serial0:115200n8";
25 compatible = "simple-bus";
28 pinctrl-names = "default";
29 pinctrl-0 = <&wlan_default_gpios>;
30 compatible = "mmc-pwrseq-simple";
[all …]
H A Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
[all …]
H A Dsun6i-a31s-primo81.dts4 * Copyright 2015 Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 /dts-v1/;
46 #include "sun6i-a31s.dtsi"
47 #include "sunxi-common-regulators.dtsi"
49 #include <dt-bindings/gpio/gpio.h>
50 #include <dt-bindings/input/input.h>
54 compatible = "msi,primo81", "allwinner,sun6i-a31s";
56 hdmi-connector {
57 compatible = "hdmi-connector";
[all …]
H A Drk3288-th804-avb.dts4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include "rk3288-th804.dtsi"
12 compatible = "rockchip,rk3288-th804", "rockchip,rk3288";
16 vcc_camera: vcc-camera-regulator {
17 compatible = "regulator-fixed";
19 pinctrl-names = "default";
20 pinctrl-0 = <&camera_pwr>;
21 regulator-name = "vcc_camera";
22 enable-active-high;
[all …]
H A Dimx6dl-riotboard.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
12 compatible = "riot,imx6s-riotboard", "fsl,imx6dl";
20 stdout-path = "serial1:115200n8";
24 compatible = "gpio-leds";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_led>;
31 default-state = "on";
32 linux,default-trigger = "heartbeat";
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/host1x/
H A Dmipi.c102 /* bias pad configuration settings */
131 struct tegra_mipi *mipi; member
136 static inline u32 tegra_mipi_readl(struct tegra_mipi *mipi, in tegra_mipi_readl() argument
139 return readl(mipi->regs + (offset << 2)); in tegra_mipi_readl()
142 static inline void tegra_mipi_writel(struct tegra_mipi *mipi, u32 value, in tegra_mipi_writel() argument
145 writel(value, mipi->regs + (offset << 2)); in tegra_mipi_writel()
148 static int tegra_mipi_power_up(struct tegra_mipi *mipi) in tegra_mipi_power_up() argument
153 err = clk_enable(mipi->clk); in tegra_mipi_power_up()
157 value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG0); in tegra_mipi_power_up()
160 if (mipi->soc->needs_vclamp_ref) in tegra_mipi_power_up()
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk1808.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <dt-bindings/clock/rk1808-cru.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/power/rk1808-power.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
11 #include <dt-bindings/soc/rockchip-system-status.h>
12 #include <dt-bindings/suspend/rockchip-rk1808.h>
[all …]
H A Drk3399.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/soc/rockchip-system-status.h>
14 #include <dt-bindings/suspend/rockchip-rk3399.h>
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi14 #include <dt-bindings/clock/mt8173-clk.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/memory/mt8173-larb-port.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/power/mt8173-power.h>
20 #include <dt-bindings/reset/mt8173-resets.h>
21 #include <dt-bindings/gce/mt8173-gce.h>
22 #include <dt-bindings/thermal/thermal.h>
23 #include "mt8173-pinfunc.h"
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/panel/
H A Dpanel-raydium-rm68200.c1 // SPDX-License-Identifier: GPL-2.0
30 #define MCS_STBCTR 0x12 /* TE1 Output Setting Zig-Zag Connection */
31 #define MCS_SGOPCTR 0x16 /* Source Bias Current */
43 #define MCS_SW_CTRL 0x5F /* Interface Control for PFM and MIPI */
45 /* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */
107 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); in rm68200_dcs_write_buf()
112 dev_err_ratelimited(ctx->dev, "MIPI DSI DCS write buffer failed: %d\n", err); in rm68200_dcs_write_buf()
117 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); in rm68200_dcs_write_cmd()
122 dev_err_ratelimited(ctx->dev, "MIPI DSI DCS write failed: %d\n", err); in rm68200_dcs_write_cmd()
133 * This panel is not able to auto-increment all cmd addresses so for some of
[all …]
H A Dpanel-sitronix-st7701.c1 // SPDX-License-Identifier: GPL-2.0+
39 #define DSI_CMD2_BK1_MIPISET1 0xD0 /* MIPI Setting 1 */
64 #define DSI_CMD2_BK0_PORCTRL_B0(m) ((m)->vtotal - (m)->vsync_end)
65 #define DSI_CMD2_BK0_PORCTRL_B1(m) ((m)->vsync_start - (m)->vdisplay)
75 #define DSI_PWCTLR1_AP BIT(7) /* Gamma OP bias, max */
76 #define DSI_PWCTLR1_APIS BIT(2) /* Source OP input bias, min */
77 #define DSI_PWCTLR1_APOS BIT(0) /* Source OP output bias, min */
81 #define DSI_PWCTLR2_AVCL 0x0 /* AVCL -4.4v */
117 return mipi_dsi_dcs_write_buffer(st7701->dsi, seq, len); in st7701_dsi_write()
128 const struct drm_display_mode *mode = st7701->desc->mode; in st7701_init_sequence()
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64-pine64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 /dts-v1/;
6 #include "sun50i-a64.dtsi"
7 #include "sun50i-a64-cpu-opp.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
13 compatible = "pine64,pine64", "allwinner,sun50i-a64";
25 stdout-path = "serial0:115200n8";
28 hdmi-connector {
29 compatible = "hdmi-connector";
34 remote-endpoint = <&hdmi_out_con>;
[all …]
H A Dsun50i-a64.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun8i-de2.h>
8 #include <dt-bindings/clock/sun8i-r-ccu.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/reset/sun50i-a64-ccu.h>
11 #include <dt-bindings/reset/sun8i-de2.h>
12 #include <dt-bindings/reset/sun8i-r-ccu.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
[all …]
H A Dsun50i-a64-amarula-relic.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 /dts-v1/;
7 #include "sun50i-a64.dtsi"
8 #include "sun50i-a64-cpu-opp.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
13 model = "Amarula A64-Relic";
14 compatible = "amarula,a64-relic", "allwinner,sun50i-a64";
21 stdout-path = "serial0:115200n8";
25 compatible = "i2c-gpio";
26 sda-gpios = <&pio 4 13 GPIO_ACTIVE_HIGH>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/nvidia/
H A Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
[all …]
/OK3568_Linux_fs/kernel/drivers/soc/tegra/
H A Dpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
36 #include <linux/pinctrl/pinconf-generic.h>
51 #include <dt-bindings/interrupt-controller/arm-gic.h>
52 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
53 #include <dt-bindings/gpio/tegra186-gpio.h>
[all …]

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