1/* 2 * SPDX-License-Identifier: GPL-2.0+ 3 */ 4 5#include <dt-bindings/gpio/gpio.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/clock/rk3288-cru.h> 10#include <dt-bindings/power-domain/rk3288.h> 11#include <dt-bindings/thermal/thermal.h> 12#include <dt-bindings/video/rk3288.h> 13#include "skeleton.dtsi" 14 15/ { 16 compatible = "rockchip,rk3288"; 17 18 interrupt-parent = <&gic>; 19 aliases { 20 gpio0 = &gpio0; 21 gpio1 = &gpio1; 22 gpio2 = &gpio2; 23 gpio3 = &gpio3; 24 gpio4 = &gpio4; 25 gpio5 = &gpio5; 26 gpio6 = &gpio6; 27 gpio7 = &gpio7; 28 gpio8 = &gpio8; 29 i2c0 = &i2c0; 30 i2c1 = &i2c1; 31 i2c2 = &i2c2; 32 i2c3 = &i2c3; 33 i2c4 = &i2c4; 34 i2c5 = &i2c5; 35 mmc0 = &emmc; 36 mmc1 = &sdmmc; 37 mmc2 = &sdio0; 38 mmc3 = &sdio1; 39 mshc0 = &emmc; 40 mshc1 = &sdmmc; 41 mshc2 = &sdio0; 42 mshc3 = &sdio1; 43 serial0 = &uart0; 44 serial1 = &uart1; 45 serial2 = &uart2; 46 serial3 = &uart3; 47 serial4 = &uart4; 48 spi0 = &spi0; 49 spi1 = &spi1; 50 spi2 = &spi2; 51 }; 52 53 cpus { 54 #address-cells = <1>; 55 #size-cells = <0>; 56 enable-method = "rockchip,rk3066-smp"; 57 rockchip,pmu = <&pmu>; 58 59 cpu0: cpu@500 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a12"; 62 reg = <0x500>; 63 operating-points = < 64 /* KHz uV */ 65 1800000 1400000 66 1704000 1350000 67 1608000 1300000 68 1512000 1250000 69 1416000 1200000 70 1200000 1100000 71 1008000 1050000 72 816000 1000000 73 696000 950000 74 600000 900000 75 408000 900000 76 216000 900000 77 126000 900000 78 >; 79 #cooling-cells = <2>; /* min followed by max */ 80 clock-latency = <40000>; 81 clocks = <&cru ARMCLK>; 82 resets = <&cru SRST_CORE0>; 83 }; 84 cpu@501 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a12"; 87 reg = <0x501>; 88 resets = <&cru SRST_CORE1>; 89 }; 90 cpu@502 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a12"; 93 reg = <0x502>; 94 resets = <&cru SRST_CORE2>; 95 }; 96 cpu@503 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a12"; 99 reg = <0x503>; 100 resets = <&cru SRST_CORE3>; 101 }; 102 }; 103 104 amba { 105 compatible = "arm,amba-bus"; 106 #address-cells = <1>; 107 #size-cells = <1>; 108 ranges; 109 110 dmac_peri: dma-controller@ff250000 { 111 compatible = "arm,pl330", "arm,primecell"; 112 broken-no-flushp; 113 reg = <0xff250000 0x4000>; 114 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 116 #dma-cells = <1>; 117 clocks = <&cru ACLK_DMAC2>; 118 clock-names = "apb_pclk"; 119 }; 120 121 dmac_bus_ns: dma-controller@ff600000 { 122 compatible = "arm,pl330", "arm,primecell"; 123 broken-no-flushp; 124 reg = <0xff600000 0x4000>; 125 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 127 #dma-cells = <1>; 128 clocks = <&cru ACLK_DMAC1>; 129 clock-names = "apb_pclk"; 130 status = "disabled"; 131 }; 132 133 dmac_bus_s: dma-controller@ffb20000 { 134 compatible = "arm,pl330", "arm,primecell"; 135 broken-no-flushp; 136 reg = <0xffb20000 0x4000>; 137 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 139 #dma-cells = <1>; 140 clocks = <&cru ACLK_DMAC1>; 141 clock-names = "apb_pclk"; 142 }; 143 }; 144 145 xin24m: oscillator { 146 compatible = "fixed-clock"; 147 clock-frequency = <24000000>; 148 clock-output-names = "xin24m"; 149 #clock-cells = <0>; 150 }; 151 152 psci: psci { 153 compatible = "arm,psci-1.0"; 154 method = "smc"; 155 }; 156 157 timer { 158 arm,use-physical-timer; 159 compatible = "arm,armv7-timer"; 160 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 161 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 162 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 163 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 164 clock-frequency = <24000000>; 165 always-on; 166 }; 167 168 display_subsystem: display-subsystem { 169 compatible = "rockchip,display-subsystem"; 170 ports = <&vopl_out>, <&vopb_out>; 171 status = "disabled"; 172 173 route { 174 route_hdmi: route-hdmi { 175 status = "disabled"; 176 logo,uboot = "logo.bmp"; 177 logo,kernel = "logo_kernel.bmp"; 178 logo,mode = "center"; 179 charge_logo,mode = "center"; 180 connect = <&vopb_out_hdmi>; 181 }; 182 183 route_edp: route-edp { 184 status = "disabled"; 185 logo,uboot = "logo.bmp"; 186 logo,kernel = "logo_kernel.bmp"; 187 logo,mode = "center"; 188 charge_logo,mode = "center"; 189 connect = <&vopl_out_edp>; 190 }; 191 192 route_dsi0: route-dsi0 { 193 status = "disabled"; 194 logo,uboot = "logo.bmp"; 195 logo,kernel = "logo_kernel.bmp"; 196 logo,mode = "center"; 197 charge_logo,mode = "center"; 198 connect = <&vopl_out_dsi0>; 199 }; 200 201 route_lvds: route-lvds { 202 status = "disabled"; 203 logo,uboot = "logo.bmp"; 204 logo,kernel = "logo_kernel.bmp"; 205 logo,mode = "center"; 206 charge_logo,mode = "center"; 207 connect = <&vopl_out_lvds>; 208 }; 209 }; 210 }; 211 212 sdmmc: dwmmc@ff0c0000 { 213 compatible = "rockchip,rk3288-dw-mshc"; 214 max-frequency = <150000000>; 215 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 216 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 217 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 218 fifo-depth = <0x100>; 219 cd-gpios = <&gpio6 RK_PC6 GPIO_ACTIVE_HIGH>; 220 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 221 reg = <0xff0c0000 0x4000>; 222 status = "disabled"; 223 }; 224 225 sdio0: dwmmc@ff0d0000 { 226 compatible = "rockchip,rk3288-dw-mshc"; 227 max-frequency = <150000000>; 228 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 229 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 230 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 231 fifo-depth = <0x100>; 232 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 233 reg = <0xff0d0000 0x4000>; 234 status = "disabled"; 235 }; 236 237 sdio1: dwmmc@ff0e0000 { 238 compatible = "rockchip,rk3288-dw-mshc"; 239 max-frequency = <150000000>; 240 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, 241 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; 242 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 243 fifo-depth = <0x100>; 244 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 245 reg = <0xff0e0000 0x4000>; 246 status = "disabled"; 247 }; 248 249 emmc: dwmmc@ff0f0000 { 250 compatible = "rockchip,rk3288-dw-mshc"; 251 max-frequency = <150000000>; 252 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 253 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 254 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 255 fifo-depth = <0x100>; 256 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 257 reg = <0xff0f0000 0x4000>; 258 status = "disabled"; 259 }; 260 261 saradc: saradc@ff100000 { 262 compatible = "rockchip,saradc"; 263 reg = <0xff100000 0x100>; 264 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 265 #io-channel-cells = <1>; 266 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 267 clock-names = "saradc", "apb_pclk"; 268 status = "disabled"; 269 }; 270 271 spi0: spi@ff110000 { 272 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 273 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 274 clock-names = "spiclk", "apb_pclk"; 275 dmas = <&dmac_peri 11>, <&dmac_peri 12>; 276 dma-names = "tx", "rx"; 277 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 278 pinctrl-names = "default"; 279 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 280 reg = <0xff110000 0x1000>; 281 #address-cells = <1>; 282 #size-cells = <0>; 283 status = "disabled"; 284 }; 285 286 spi1: spi@ff120000 { 287 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 288 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 289 clock-names = "spiclk", "apb_pclk"; 290 dmas = <&dmac_peri 13>, <&dmac_peri 14>; 291 dma-names = "tx", "rx"; 292 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 293 pinctrl-names = "default"; 294 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 295 reg = <0xff120000 0x1000>; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 status = "disabled"; 299 }; 300 301 spi2: spi@ff130000 { 302 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 303 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 304 clock-names = "spiclk", "apb_pclk"; 305 dmas = <&dmac_peri 15>, <&dmac_peri 16>; 306 dma-names = "tx", "rx"; 307 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 308 pinctrl-names = "default"; 309 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 310 reg = <0xff130000 0x1000>; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 status = "disabled"; 314 }; 315 316 i2c1: i2c@ff140000 { 317 compatible = "rockchip,rk3288-i2c"; 318 reg = <0xff140000 0x1000>; 319 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 clock-names = "i2c"; 323 clocks = <&cru PCLK_I2C1>; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&i2c1_xfer>; 326 status = "disabled"; 327 }; 328 329 i2c3: i2c@ff150000 { 330 compatible = "rockchip,rk3288-i2c"; 331 reg = <0xff150000 0x1000>; 332 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 333 #address-cells = <1>; 334 #size-cells = <0>; 335 clock-names = "i2c"; 336 clocks = <&cru PCLK_I2C3>; 337 pinctrl-names = "default"; 338 pinctrl-0 = <&i2c3_xfer>; 339 status = "disabled"; 340 }; 341 342 i2c4: i2c@ff160000 { 343 compatible = "rockchip,rk3288-i2c"; 344 reg = <0xff160000 0x1000>; 345 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 346 #address-cells = <1>; 347 #size-cells = <0>; 348 clock-names = "i2c"; 349 clocks = <&cru PCLK_I2C4>; 350 pinctrl-names = "default"; 351 pinctrl-0 = <&i2c4_xfer>; 352 status = "disabled"; 353 }; 354 355 i2c5: i2c@ff170000 { 356 compatible = "rockchip,rk3288-i2c"; 357 reg = <0xff170000 0x1000>; 358 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 clock-names = "i2c"; 362 clocks = <&cru PCLK_I2C5>; 363 pinctrl-names = "default"; 364 pinctrl-0 = <&i2c5_xfer>; 365 status = "disabled"; 366 }; 367 368 uart0: serial@ff180000 { 369 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 370 reg = <0xff180000 0x100>; 371 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 372 reg-shift = <2>; 373 reg-io-width = <4>; 374 clock-frequency = <24000000>; 375 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 376 clock-names = "baudclk", "apb_pclk"; 377 pinctrl-names = "default"; 378 pinctrl-0 = <&uart0_xfer>; 379 status = "disabled"; 380 }; 381 382 uart1: serial@ff190000 { 383 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 384 reg = <0xff190000 0x100>; 385 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 386 reg-shift = <2>; 387 reg-io-width = <4>; 388 clock-frequency = <24000000>; 389 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 390 clock-names = "baudclk", "apb_pclk"; 391 pinctrl-names = "default"; 392 pinctrl-0 = <&uart1_xfer>; 393 status = "disabled"; 394 }; 395 396 uart2: serial@ff690000 { 397 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 398 reg = <0xff690000 0x100>; 399 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 400 reg-shift = <2>; 401 reg-io-width = <4>; 402 clock-frequency = <24000000>; 403 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 404 clock-names = "baudclk", "apb_pclk"; 405 pinctrl-names = "default"; 406 pinctrl-0 = <&uart2_xfer>; 407 status = "disabled"; 408 }; 409 uart3: serial@ff1b0000 { 410 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 411 reg = <0xff1b0000 0x100>; 412 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 413 reg-shift = <2>; 414 reg-io-width = <4>; 415 clock-frequency = <24000000>; 416 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 417 clock-names = "baudclk", "apb_pclk"; 418 pinctrl-names = "default"; 419 pinctrl-0 = <&uart3_xfer>; 420 status = "disabled"; 421 }; 422 423 uart4: serial@ff1c0000 { 424 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 425 reg = <0xff1c0000 0x100>; 426 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 427 reg-shift = <2>; 428 reg-io-width = <4>; 429 clock-frequency = <24000000>; 430 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 431 clock-names = "baudclk", "apb_pclk"; 432 pinctrl-names = "default"; 433 pinctrl-0 = <&uart4_xfer>; 434 status = "disabled"; 435 }; 436 437 thermal: thermal-zones { 438 #include "rk3288-thermal.dtsi" 439 }; 440 441 tsadc: tsadc@ff280000 { 442 compatible = "rockchip,rk3288-tsadc"; 443 reg = <0xff280000 0x100>; 444 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 446 clock-names = "tsadc", "apb_pclk"; 447 resets = <&cru SRST_TSADC>; 448 reset-names = "tsadc-apb"; 449 pinctrl-names = "otp_out"; 450 pinctrl-0 = <&otp_out>; 451 #thermal-sensor-cells = <1>; 452 hw-shut-temp = <125000>; 453 status = "disabled"; 454 }; 455 456 gmac: ethernet@ff290000 { 457 compatible = "rockchip,rk3288-gmac"; 458 reg = <0xff290000 0x10000>; 459 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 460 interrupt-names = "macirq"; 461 rockchip,grf = <&grf>; 462 clocks = <&cru SCLK_MAC>, 463 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 464 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 465 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 466 clock-names = "stmmaceth", 467 "mac_clk_rx", "mac_clk_tx", 468 "clk_mac_ref", "clk_mac_refout", 469 "aclk_mac", "pclk_mac"; 470 }; 471 472 usb_host0_ehci: usb@ff500000 { 473 compatible = "generic-ehci"; 474 reg = <0xff500000 0x100>; 475 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&cru HCLK_USBHOST0>; 477 clock-names = "usbhost"; 478 phys = <&usbphy1>; 479 phy-names = "usb"; 480 status = "disabled"; 481 }; 482 483 /* NOTE: ohci@ff520000 doesn't actually work on hardware */ 484 485 usb_host1: usb@ff540000 { 486 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 487 "snps,dwc2"; 488 reg = <0xff540000 0x40000>; 489 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&cru HCLK_USBHOST1>; 491 clock-names = "otg"; 492 phys = <&usbphy2>; 493 phy-names = "usb2-phy"; 494 status = "disabled"; 495 }; 496 497 usb_otg: usb@ff580000 { 498 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 499 "snps,dwc2"; 500 reg = <0xff580000 0x40000>; 501 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&cru HCLK_OTG0>; 503 clock-names = "otg"; 504 dr_mode = "otg"; 505 phys = <&usbphy0>; 506 phy-names = "usb2-phy"; 507 status = "disabled"; 508 }; 509 510 usb_hsic: usb@ff5c0000 { 511 compatible = "generic-ehci"; 512 reg = <0xff5c0000 0x100>; 513 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&cru HCLK_HSIC>; 515 clock-names = "usbhost"; 516 status = "disabled"; 517 }; 518 519 dmc: dmc@ff610000 { 520 compatible = "rockchip,rk3288-dmc", "syscon"; 521 rockchip,cru = <&cru>; 522 rockchip,grf = <&grf>; 523 rockchip,pmu = <&pmu>; 524 rockchip,sgrf = <&sgrf>; 525 rockchip,noc = <&noc>; 526 reg = <0xff610000 0x3fc 527 0xff620000 0x294 528 0xff630000 0x3fc 529 0xff640000 0x294>; 530 rockchip,sram = <&ddr_sram>; 531 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>, 532 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>, 533 <&cru ARMCLK>; 534 clock-names = "pclk_ddrupctl0", "pclk_publ0", 535 "pclk_ddrupctl1", "pclk_publ1", 536 "arm_clk"; 537 }; 538 539 i2c0: i2c@ff650000 { 540 compatible = "rockchip,rk3288-i2c"; 541 reg = <0xff650000 0x1000>; 542 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 clock-names = "i2c"; 546 clocks = <&cru PCLK_I2C0>; 547 pinctrl-names = "default"; 548 pinctrl-0 = <&i2c0_xfer>; 549 status = "disabled"; 550 }; 551 552 i2c2: i2c@ff660000 { 553 compatible = "rockchip,rk3288-i2c"; 554 reg = <0xff660000 0x1000>; 555 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 clock-names = "i2c"; 559 clocks = <&cru PCLK_I2C2>; 560 pinctrl-names = "default"; 561 pinctrl-0 = <&i2c2_xfer>; 562 status = "disabled"; 563 }; 564 565 pwm0: pwm@ff680000 { 566 compatible = "rockchip,rk3288-pwm"; 567 reg = <0xff680000 0x10>; 568 #pwm-cells = <3>; 569 pinctrl-names = "active"; 570 pinctrl-0 = <&pwm0_pin>; 571 clocks = <&cru PCLK_PWM>; 572 clock-names = "pwm"; 573 rockchip,grf = <&grf>; 574 status = "disabled"; 575 }; 576 577 pwm1: pwm@ff680010 { 578 compatible = "rockchip,rk3288-pwm"; 579 reg = <0xff680010 0x10>; 580 #pwm-cells = <3>; 581 pinctrl-names = "active"; 582 pinctrl-0 = <&pwm1_pin>; 583 clocks = <&cru PCLK_PWM>; 584 clock-names = "pwm"; 585 rockchip,grf = <&grf>; 586 status = "disabled"; 587 }; 588 589 pwm2: pwm@ff680020 { 590 compatible = "rockchip,rk3288-pwm"; 591 reg = <0xff680020 0x10>; 592 #pwm-cells = <3>; 593 pinctrl-names = "active"; 594 pinctrl-0 = <&pwm2_pin>; 595 clocks = <&cru PCLK_PWM>; 596 clock-names = "pwm"; 597 rockchip,grf = <&grf>; 598 status = "disabled"; 599 }; 600 601 pwm3: pwm@ff680030 { 602 compatible = "rockchip,rk3288-pwm"; 603 reg = <0xff680030 0x10>; 604 #pwm-cells = <2>; 605 pinctrl-names = "active"; 606 pinctrl-0 = <&pwm3_pin>; 607 clocks = <&cru PCLK_PWM>; 608 clock-names = "pwm"; 609 rockchip,grf = <&grf>; 610 status = "disabled"; 611 }; 612 613 bus_intmem@ff700000 { 614 compatible = "mmio-sram"; 615 reg = <0xff700000 0x18000>; 616 #address-cells = <1>; 617 #size-cells = <1>; 618 ranges = <0 0xff700000 0x18000>; 619 smp-sram@0 { 620 compatible = "rockchip,rk3066-smp-sram"; 621 reg = <0x00 0x10>; 622 }; 623 ddr_sram: ddr-sram@1000 { 624 compatible = "rockchip,rk3288-ddr-sram"; 625 reg = <0x1000 0x4000>; 626 }; 627 }; 628 629 sram@ff720000 { 630 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 631 reg = <0xff720000 0x1000>; 632 }; 633 634 pmu: power-management@ff730000 { 635 compatible = "rockchip,rk3288-pmu", "syscon"; 636 reg = <0xff730000 0x100>; 637 }; 638 639 sgrf: syscon@ff740000 { 640 compatible = "rockchip,rk3288-sgrf", "syscon"; 641 reg = <0xff740000 0x1000>; 642 }; 643 644 cru: clock-controller@ff760000 { 645 compatible = "rockchip,rk3288-cru"; 646 reg = <0xff760000 0x1000>; 647 rockchip,grf = <&grf>; 648 #clock-cells = <1>; 649 #reset-cells = <1>; 650 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, 651 <&cru PLL_NPLL>, <&cru ACLK_CPU>, 652 <&cru HCLK_CPU>, <&cru PCLK_CPU>, 653 <&cru ACLK_PERI>, <&cru HCLK_PERI>, 654 <&cru PCLK_PERI>; 655 assigned-clock-rates = <594000000>, <400000000>, 656 <500000000>, <300000000>, 657 <150000000>, <75000000>, 658 <300000000>, <150000000>, 659 <75000000>; 660 }; 661 662 grf: syscon@ff770000 { 663 compatible = "rockchip,rk3288-grf", "syscon"; 664 reg = <0xff770000 0x1000>; 665 }; 666 667 wdt: watchdog@ff800000 { 668 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; 669 reg = <0xff800000 0x100>; 670 clocks = <&cru PCLK_WDT>; 671 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 672 status = "disabled"; 673 }; 674 675 spdif: sound@ff88b0000 { 676 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; 677 reg = <0xff8b0000 0x10000>; 678 #sound-dai-cells = <0>; 679 clock-names = "hclk", "mclk"; 680 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; 681 dmas = <&dmac_bus_s 3>; 682 dma-names = "tx"; 683 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 684 pinctrl-names = "default"; 685 pinctrl-0 = <&spdif_tx>; 686 rockchip,grf = <&grf>; 687 status = "disabled"; 688 }; 689 690 i2s: i2s@ff890000 { 691 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; 692 reg = <0xff890000 0x10000>; 693 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 694 #address-cells = <1>; 695 #size-cells = <0>; 696 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; 697 dma-names = "tx", "rx"; 698 clock-names = "i2s_hclk", "i2s_clk"; 699 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; 700 pinctrl-names = "default"; 701 pinctrl-0 = <&i2s0_bus>; 702 status = "disabled"; 703 }; 704 705 crypto: crypto@ff8a0000 { 706 compatible = "rockchip,rk3288-crypto"; 707 reg = <0xff8a0000 0x10000>; 708 clock-names = "sclk_crypto"; 709 clocks = <&cru SCLK_CRYPTO>; 710 resets = <&cru SRST_CRYPTO>; 711 reset-names = "reset"; 712 status = "disabled"; 713 }; 714 715 vopb: vop@ff930000 { 716 compatible = "rockchip,rk3288-vop-big"; 717 reg = <0xff930000 0x19c>; 718 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 720 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 721 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 722 reset-names = "axi", "ahb", "dclk"; 723 iommus = <&vopb_mmu>; 724 power-domains = <&power RK3288_PD_VIO>; 725 status = "disabled"; 726 vopb_out: port { 727 #address-cells = <1>; 728 #size-cells = <0>; 729 vopb_out_edp: endpoint@0 { 730 reg = <0>; 731 remote-endpoint = <&edp_in_vopb>; 732 }; 733 vopb_out_hdmi: endpoint@1 { 734 reg = <1>; 735 remote-endpoint = <&hdmi_in_vopb>; 736 }; 737 vopb_out_lvds: endpoint@2 { 738 reg = <2>; 739 remote-endpoint = <&lvds_in_vopb>; 740 }; 741 vopb_out_dsi0: endpoint@3 { 742 reg = <3>; 743 remote-endpoint = <&dsi0_in_vopb>; 744 }; 745 746 }; 747 }; 748 749 vopb_mmu: iommu@ff930300 { 750 compatible = "rockchip,iommu"; 751 reg = <0xff930300 0x100>; 752 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 753 interrupt-names = "vopb_mmu"; 754 power-domains = <&power RK3288_PD_VIO>; 755 #iommu-cells = <0>; 756 status = "disabled"; 757 }; 758 759 vopl: vop@ff940000 { 760 compatible = "rockchip,rk3288-vop-lit"; 761 reg = <0xff940000 0x19c>; 762 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 764 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 765 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; 766 reset-names = "axi", "ahb", "dclk"; 767 iommus = <&vopl_mmu>; 768 power-domains = <&power RK3288_PD_VIO>; 769 status = "disabled"; 770 vopl_out: port { 771 #address-cells = <1>; 772 #size-cells = <0>; 773 vopl_out_edp: endpoint@0 { 774 reg = <0>; 775 remote-endpoint = <&edp_in_vopl>; 776 }; 777 vopl_out_hdmi: endpoint@1 { 778 reg = <1>; 779 remote-endpoint = <&hdmi_in_vopl>; 780 }; 781 vopl_out_lvds: endpoint@2 { 782 reg = <2>; 783 remote-endpoint = <&lvds_in_vopl>; 784 }; 785 vopl_out_dsi0: endpoint@3 { 786 reg = <3>; 787 remote-endpoint = <&dsi0_in_vopl>; 788 }; 789 790 }; 791 }; 792 793 vopl_mmu: iommu@ff940300 { 794 compatible = "rockchip,iommu"; 795 reg = <0xff940300 0x100>; 796 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 797 interrupt-names = "vopl_mmu"; 798 power-domains = <&power RK3288_PD_VIO>; 799 #iommu-cells = <0>; 800 status = "disabled"; 801 }; 802 803 edp: edp@ff970000 { 804 compatible = "rockchip,rk3288-dp"; 805 reg = <0xff970000 0x4000>; 806 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 807 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>; 808 rockchip,grf = <&grf>; 809 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; 810 resets = <&cru 111>; 811 reset-names = "edp"; 812 power-domains = <&power RK3288_PD_VIO>; 813 status = "disabled"; 814 ports { 815 #address-cells = <1>; 816 #size-cells = <0>; 817 818 edp_in: port { 819 #address-cells = <1>; 820 #size-cells = <0>; 821 edp_in_vopb: endpoint@0 { 822 reg = <0>; 823 remote-endpoint = <&vopb_out_edp>; 824 }; 825 edp_in_vopl: endpoint@1 { 826 reg = <1>; 827 remote-endpoint = <&vopl_out_edp>; 828 }; 829 }; 830 }; 831 }; 832 833 hdmi: hdmi@ff980000 { 834 compatible = "rockchip,rk3288-dw-hdmi"; 835 reg = <0xff980000 0x20000>; 836 reg-io-width = <4>; 837 rockchip,grf = <&grf>; 838 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; 840 clock-names = "iahb", "isfr"; 841 pinctrl-names = "default"; 842 pinctrl-0 = <&hdmi_ddc>; 843 status = "disabled"; 844 ports { 845 hdmi_in: port { 846 #address-cells = <1>; 847 #size-cells = <0>; 848 hdmi_in_vopb: endpoint@0 { 849 reg = <0>; 850 remote-endpoint = <&vopb_out_hdmi>; 851 }; 852 hdmi_in_vopl: endpoint@1 { 853 reg = <1>; 854 remote-endpoint = <&vopl_out_hdmi>; 855 }; 856 }; 857 }; 858 }; 859 860 lvds: lvds@ff96c000 { 861 compatible = "rockchip,rk3288-lvds"; 862 reg = <0xff96c000 0x4000>; 863 clocks = <&cru PCLK_LVDS_PHY>; 864 clock-names = "pclk_lvds"; 865 pinctrl-names = "default"; 866 pinctrl-0 = <&lcdc0_ctl>; 867 rockchip,grf = <&grf>; 868 status = "disabled"; 869 ports { 870 #address-cells = <1>; 871 #size-cells = <0>; 872 lvds_in: port@0 { 873 reg = <0>; 874 #address-cells = <1>; 875 #size-cells = <0>; 876 lvds_in_vopb: endpoint@0 { 877 reg = <0>; 878 remote-endpoint = <&vopb_out_lvds>; 879 }; 880 lvds_in_vopl: endpoint@1 { 881 reg = <1>; 882 remote-endpoint = <&vopl_out_lvds>; 883 }; 884 }; 885 }; 886 }; 887 888 dsi0: mipi@ff960000 { 889 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; 890 reg = <0xff960000 0x4000>; 891 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; 893 clock-names = "ref", "pclk"; 894 resets = <&cru SRST_MIPIDSI0>; 895 reset-names = "apb"; 896 power-domains = <&power RK3288_PD_VIO>; 897 rockchip,grf = <&grf>; 898 #address-cells = <1>; 899 #size-cells = <0>; 900 status = "disabled"; 901 ports { 902 #address-cells = <1>; 903 #size-cells = <0>; 904 reg = <1>; 905 mipi_in: port { 906 #address-cells = <1>; 907 #size-cells = <0>; 908 dsi0_in_vopb: endpoint@0 { 909 reg = <0>; 910 remote-endpoint = <&vopb_out_dsi0>; 911 }; 912 dsi0_in_vopl: endpoint@1 { 913 reg = <1>; 914 remote-endpoint = <&vopl_out_dsi0>; 915 }; 916 }; 917 }; 918 }; 919 920 hdmi_audio: hdmi_audio { 921 compatible = "rockchip,rk3288-hdmi-audio"; 922 i2s-controller = <&i2s>; 923 status = "disable"; 924 }; 925 926 vpu: video-codec@ff9a0000 { 927 compatible = "rockchip,rk3288-vpu"; 928 reg = <0xff9a0000 0x800>; 929 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 931 interrupt-names = "vepu", "vdpu"; 932 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 933 clock-names = "aclk_vcodec", "hclk_vcodec"; 934 power-domains = <&power RK3288_PD_VIDEO>; 935 iommus = <&vpu_mmu>; 936 }; 937 938 vpu_mmu: iommu@ff9a0800 { 939 compatible = "rockchip,iommu"; 940 reg = <0xff9a0800 0x100>; 941 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 942 interrupt-names = "vpu_mmu"; 943 power-domains = <&power RK3288_PD_VIDEO>; 944 #iommu-cells = <0>; 945 }; 946 947 gpu: gpu@ffa30000 { 948 compatible = "arm,malit764", 949 "arm,malit76x", 950 "arm,malit7xx", 951 "arm,mali-midgard"; 952 reg = <0xffa30000 0x10000>; 953 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 956 interrupt-names = "JOB", "MMU", "GPU"; 957 clocks = <&cru ACLK_GPU>; 958 clock-names = "aclk_gpu"; 959 operating-points = < 960 /* KHz uV */ 961 100000 950000 962 200000 950000 963 300000 1000000 964 400000 1100000 965 /* 500000 1200000 - See crosbug.com/p/33857 */ 966 600000 1250000 967 >; 968 power-domains = <&power RK3288_PD_GPU>; 969 status = "disabled"; 970 }; 971 972 noc: syscon@ffac0000 { 973 compatible = "rockchip,rk3288-noc", "syscon"; 974 reg = <0xffac0000 0x2000>; 975 }; 976 977 efuse: efuse@ffb40000 { 978 compatible = "rockchip,rk3288-efuse"; 979 reg = <0xffb40000 0x10000>; 980 status = "disabled"; 981 }; 982 983 gic: interrupt-controller@ffc01000 { 984 compatible = "arm,gic-400"; 985 interrupt-controller; 986 #interrupt-cells = <3>; 987 #address-cells = <0>; 988 989 reg = <0xffc01000 0x1000>, 990 <0xffc02000 0x1000>, 991 <0xffc04000 0x2000>, 992 <0xffc06000 0x2000>; 993 interrupts = <GIC_PPI 9 0xf04>; 994 }; 995 996 cpuidle: cpuidle { 997 compatible = "rockchip,rk3288-cpuidle"; 998 }; 999 1000 usbphy: phy { 1001 compatible = "rockchip,rk3288-usb-phy"; 1002 rockchip,grf = <&grf>; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 status = "disabled"; 1006 1007 usbphy0: usb-phy0 { 1008 #phy-cells = <0>; 1009 reg = <0x320>; 1010 clocks = <&cru SCLK_OTGPHY0>; 1011 clock-names = "phyclk"; 1012 }; 1013 1014 usbphy1: usb-phy1 { 1015 #phy-cells = <0>; 1016 reg = <0x334>; 1017 clocks = <&cru SCLK_OTGPHY1>; 1018 clock-names = "phyclk"; 1019 }; 1020 1021 usbphy2: usb-phy2 { 1022 #phy-cells = <0>; 1023 reg = <0x348>; 1024 clocks = <&cru SCLK_OTGPHY2>; 1025 clock-names = "phyclk"; 1026 }; 1027 }; 1028 1029 pinctrl: pinctrl { 1030 compatible = "rockchip,rk3288-pinctrl"; 1031 rockchip,grf = <&grf>; 1032 rockchip,pmu = <&pmu>; 1033 #address-cells = <1>; 1034 #size-cells = <1>; 1035 ranges; 1036 1037 gpio0: gpio0@ff750000 { 1038 compatible = "rockchip,gpio-bank"; 1039 reg = <0xff750000 0x100>; 1040 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1041 clocks = <&cru PCLK_GPIO0>; 1042 1043 gpio-controller; 1044 #gpio-cells = <2>; 1045 1046 interrupt-controller; 1047 #interrupt-cells = <2>; 1048 }; 1049 1050 gpio1: gpio1@ff780000 { 1051 compatible = "rockchip,gpio-bank"; 1052 reg = <0xff780000 0x100>; 1053 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1054 clocks = <&cru PCLK_GPIO1>; 1055 1056 gpio-controller; 1057 #gpio-cells = <2>; 1058 1059 interrupt-controller; 1060 #interrupt-cells = <2>; 1061 }; 1062 1063 gpio2: gpio2@ff790000 { 1064 compatible = "rockchip,gpio-bank"; 1065 reg = <0xff790000 0x100>; 1066 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1067 clocks = <&cru PCLK_GPIO2>; 1068 1069 gpio-controller; 1070 #gpio-cells = <2>; 1071 1072 interrupt-controller; 1073 #interrupt-cells = <2>; 1074 }; 1075 1076 gpio3: gpio3@ff7a0000 { 1077 compatible = "rockchip,gpio-bank"; 1078 reg = <0xff7a0000 0x100>; 1079 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1080 clocks = <&cru PCLK_GPIO3>; 1081 1082 gpio-controller; 1083 #gpio-cells = <2>; 1084 1085 interrupt-controller; 1086 #interrupt-cells = <2>; 1087 }; 1088 1089 gpio4: gpio4@ff7b0000 { 1090 compatible = "rockchip,gpio-bank"; 1091 reg = <0xff7b0000 0x100>; 1092 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1093 clocks = <&cru PCLK_GPIO4>; 1094 1095 gpio-controller; 1096 #gpio-cells = <2>; 1097 1098 interrupt-controller; 1099 #interrupt-cells = <2>; 1100 }; 1101 1102 gpio5: gpio5@ff7c0000 { 1103 compatible = "rockchip,gpio-bank"; 1104 reg = <0xff7c0000 0x100>; 1105 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1106 clocks = <&cru PCLK_GPIO5>; 1107 1108 gpio-controller; 1109 #gpio-cells = <2>; 1110 1111 interrupt-controller; 1112 #interrupt-cells = <2>; 1113 }; 1114 1115 gpio6: gpio6@ff7d0000 { 1116 compatible = "rockchip,gpio-bank"; 1117 reg = <0xff7d0000 0x100>; 1118 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1119 clocks = <&cru PCLK_GPIO6>; 1120 1121 gpio-controller; 1122 #gpio-cells = <2>; 1123 1124 interrupt-controller; 1125 #interrupt-cells = <2>; 1126 }; 1127 1128 gpio7: gpio7@ff7e0000 { 1129 compatible = "rockchip,gpio-bank"; 1130 reg = <0xff7e0000 0x100>; 1131 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1132 clocks = <&cru PCLK_GPIO7>; 1133 1134 gpio-controller; 1135 #gpio-cells = <2>; 1136 1137 interrupt-controller; 1138 #interrupt-cells = <2>; 1139 }; 1140 1141 gpio8: gpio8@ff7f0000 { 1142 compatible = "rockchip,gpio-bank"; 1143 reg = <0xff7f0000 0x100>; 1144 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1145 clocks = <&cru PCLK_GPIO8>; 1146 1147 gpio-controller; 1148 #gpio-cells = <2>; 1149 1150 interrupt-controller; 1151 #interrupt-cells = <2>; 1152 }; 1153 1154 hdmi { 1155 hdmi_ddc: hdmi-ddc { 1156 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>, 1157 <7 20 RK_FUNC_2 &pcfg_pull_none>; 1158 }; 1159 }; 1160 1161 pcfg_pull_up: pcfg-pull-up { 1162 bias-pull-up; 1163 }; 1164 1165 pcfg_pull_down: pcfg-pull-down { 1166 bias-pull-down; 1167 }; 1168 1169 pcfg_pull_none: pcfg-pull-none { 1170 bias-disable; 1171 }; 1172 1173 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1174 bias-disable; 1175 drive-strength = <12>; 1176 }; 1177 1178 sleep { 1179 global_pwroff: global-pwroff { 1180 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>; 1181 }; 1182 1183 ddrio_pwroff: ddrio-pwroff { 1184 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; 1185 }; 1186 1187 ddr0_retention: ddr0-retention { 1188 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>; 1189 }; 1190 1191 ddr1_retention: ddr1-retention { 1192 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>; 1193 }; 1194 }; 1195 1196 i2c0 { 1197 i2c0_xfer: i2c0-xfer { 1198 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, 1199 <0 16 RK_FUNC_1 &pcfg_pull_none>; 1200 }; 1201 }; 1202 1203 i2c1 { 1204 i2c1_xfer: i2c1-xfer { 1205 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>, 1206 <8 5 RK_FUNC_1 &pcfg_pull_none>; 1207 }; 1208 }; 1209 1210 i2c2 { 1211 i2c2_xfer: i2c2-xfer { 1212 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>, 1213 <6 10 RK_FUNC_1 &pcfg_pull_none>; 1214 }; 1215 }; 1216 1217 i2c3 { 1218 i2c3_xfer: i2c3-xfer { 1219 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>, 1220 <2 17 RK_FUNC_1 &pcfg_pull_none>; 1221 }; 1222 }; 1223 1224 i2c4 { 1225 i2c4_xfer: i2c4-xfer { 1226 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>, 1227 <7 18 RK_FUNC_1 &pcfg_pull_none>; 1228 }; 1229 }; 1230 1231 i2c5 { 1232 i2c5_xfer: i2c5-xfer { 1233 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>, 1234 <7 20 RK_FUNC_1 &pcfg_pull_none>; 1235 }; 1236 }; 1237 1238 i2s0 { 1239 i2s0_bus: i2s0-bus { 1240 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>, 1241 <6 1 RK_FUNC_1 &pcfg_pull_none>, 1242 <6 2 RK_FUNC_1 &pcfg_pull_none>, 1243 <6 3 RK_FUNC_1 &pcfg_pull_none>, 1244 <6 4 RK_FUNC_1 &pcfg_pull_none>, 1245 <6 8 RK_FUNC_1 &pcfg_pull_none>; 1246 }; 1247 }; 1248 1249 lcdc0 { 1250 lcdc0_ctl: lcdc0-ctl { 1251 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>, 1252 <1 25 RK_FUNC_1 &pcfg_pull_none>, 1253 <1 26 RK_FUNC_1 &pcfg_pull_none>, 1254 <1 27 RK_FUNC_1 &pcfg_pull_none>; 1255 }; 1256 }; 1257 1258 sdmmc { 1259 sdmmc_clk: sdmmc-clk { 1260 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; 1261 }; 1262 1263 sdmmc_cmd: sdmmc-cmd { 1264 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>; 1265 }; 1266 1267 sdmmc_cd: sdmcc-cd { 1268 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>; 1269 }; 1270 1271 sdmmc_bus1: sdmmc-bus1 { 1272 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>; 1273 }; 1274 1275 sdmmc_bus4: sdmmc-bus4 { 1276 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>, 1277 <6 17 RK_FUNC_1 &pcfg_pull_up>, 1278 <6 18 RK_FUNC_1 &pcfg_pull_up>, 1279 <6 19 RK_FUNC_1 &pcfg_pull_up>; 1280 }; 1281 }; 1282 1283 sdio0 { 1284 sdio0_bus1: sdio0-bus1 { 1285 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>; 1286 }; 1287 1288 sdio0_bus4: sdio0-bus4 { 1289 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>, 1290 <4 21 RK_FUNC_1 &pcfg_pull_up>, 1291 <4 22 RK_FUNC_1 &pcfg_pull_up>, 1292 <4 23 RK_FUNC_1 &pcfg_pull_up>; 1293 }; 1294 1295 sdio0_cmd: sdio0-cmd { 1296 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>; 1297 }; 1298 1299 sdio0_clk: sdio0-clk { 1300 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>; 1301 }; 1302 1303 sdio0_cd: sdio0-cd { 1304 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>; 1305 }; 1306 1307 sdio0_wp: sdio0-wp { 1308 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>; 1309 }; 1310 1311 sdio0_pwr: sdio0-pwr { 1312 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>; 1313 }; 1314 1315 sdio0_bkpwr: sdio0-bkpwr { 1316 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>; 1317 }; 1318 1319 sdio0_int: sdio0-int { 1320 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>; 1321 }; 1322 }; 1323 1324 sdio1 { 1325 sdio1_bus1: sdio1-bus1 { 1326 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>; 1327 }; 1328 1329 sdio1_bus4: sdio1-bus4 { 1330 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>, 1331 <3 25 RK_FUNC_4 &pcfg_pull_up>, 1332 <3 26 RK_FUNC_4 &pcfg_pull_up>, 1333 <3 27 RK_FUNC_4 &pcfg_pull_up>; 1334 }; 1335 1336 sdio1_cd: sdio1-cd { 1337 rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>; 1338 }; 1339 1340 sdio1_wp: sdio1-wp { 1341 rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>; 1342 }; 1343 1344 sdio1_bkpwr: sdio1-bkpwr { 1345 rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>; 1346 }; 1347 1348 sdio1_int: sdio1-int { 1349 rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>; 1350 }; 1351 1352 sdio1_cmd: sdio1-cmd { 1353 rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>; 1354 }; 1355 1356 sdio1_clk: sdio1-clk { 1357 rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>; 1358 }; 1359 1360 sdio1_pwr: sdio1-pwr { 1361 rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>; 1362 }; 1363 }; 1364 1365 emmc { 1366 emmc_clk: emmc-clk { 1367 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; 1368 }; 1369 1370 emmc_cmd: emmc-cmd { 1371 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>; 1372 }; 1373 1374 emmc_pwr: emmc-pwr { 1375 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>; 1376 }; 1377 1378 emmc_bus1: emmc-bus1 { 1379 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>; 1380 }; 1381 1382 emmc_bus4: emmc-bus4 { 1383 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, 1384 <3 1 RK_FUNC_2 &pcfg_pull_up>, 1385 <3 2 RK_FUNC_2 &pcfg_pull_up>, 1386 <3 3 RK_FUNC_2 &pcfg_pull_up>; 1387 }; 1388 1389 emmc_bus8: emmc-bus8 { 1390 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, 1391 <3 1 RK_FUNC_2 &pcfg_pull_up>, 1392 <3 2 RK_FUNC_2 &pcfg_pull_up>, 1393 <3 3 RK_FUNC_2 &pcfg_pull_up>, 1394 <3 4 RK_FUNC_2 &pcfg_pull_up>, 1395 <3 5 RK_FUNC_2 &pcfg_pull_up>, 1396 <3 6 RK_FUNC_2 &pcfg_pull_up>, 1397 <3 7 RK_FUNC_2 &pcfg_pull_up>; 1398 }; 1399 }; 1400 1401 spi0 { 1402 spi0_clk: spi0-clk { 1403 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>; 1404 }; 1405 spi0_cs0: spi0-cs0 { 1406 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>; 1407 }; 1408 spi0_tx: spi0-tx { 1409 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>; 1410 }; 1411 spi0_rx: spi0-rx { 1412 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>; 1413 }; 1414 spi0_cs1: spi0-cs1 { 1415 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>; 1416 }; 1417 }; 1418 spi1 { 1419 spi1_clk: spi1-clk { 1420 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>; 1421 }; 1422 spi1_cs0: spi1-cs0 { 1423 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>; 1424 }; 1425 spi1_rx: spi1-rx { 1426 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>; 1427 }; 1428 spi1_tx: spi1-tx { 1429 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>; 1430 }; 1431 }; 1432 1433 spi2 { 1434 spi2_cs1: spi2-cs1 { 1435 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>; 1436 }; 1437 spi2_clk: spi2-clk { 1438 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>; 1439 }; 1440 spi2_cs0: spi2-cs0 { 1441 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>; 1442 }; 1443 spi2_rx: spi2-rx { 1444 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>; 1445 }; 1446 spi2_tx: spi2-tx { 1447 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>; 1448 }; 1449 }; 1450 1451 uart0 { 1452 uart0_xfer: uart0-xfer { 1453 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, 1454 <4 17 RK_FUNC_1 &pcfg_pull_none>; 1455 }; 1456 1457 uart0_cts: uart0-cts { 1458 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>; 1459 }; 1460 1461 uart0_rts: uart0-rts { 1462 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>; 1463 }; 1464 }; 1465 1466 uart1 { 1467 uart1_xfer: uart1-xfer { 1468 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>, 1469 <5 9 RK_FUNC_1 &pcfg_pull_none>; 1470 }; 1471 1472 uart1_cts: uart1-cts { 1473 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>; 1474 }; 1475 1476 uart1_rts: uart1-rts { 1477 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>; 1478 }; 1479 }; 1480 1481 uart2 { 1482 uart2_xfer: uart2-xfer { 1483 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>, 1484 <7 23 RK_FUNC_1 &pcfg_pull_none>; 1485 }; 1486 /* no rts / cts for uart2 */ 1487 }; 1488 1489 uart3 { 1490 uart3_xfer: uart3-xfer { 1491 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>, 1492 <7 8 RK_FUNC_1 &pcfg_pull_none>; 1493 }; 1494 1495 uart3_cts: uart3-cts { 1496 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>; 1497 }; 1498 1499 uart3_rts: uart3-rts { 1500 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>; 1501 }; 1502 }; 1503 1504 uart4 { 1505 uart4_xfer: uart4-xfer { 1506 rockchip,pins = <5 12 3 &pcfg_pull_up>, 1507 <5 13 3 &pcfg_pull_none>; 1508 }; 1509 1510 uart4_cts: uart4-cts { 1511 rockchip,pins = <5 14 3 &pcfg_pull_none>; 1512 }; 1513 1514 uart4_rts: uart4-rts { 1515 rockchip,pins = <5 15 3 &pcfg_pull_none>; 1516 }; 1517 }; 1518 1519 tsadc { 1520 otp_out: otp-out { 1521 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>; 1522 }; 1523 }; 1524 1525 pwm0 { 1526 pwm0_pin: pwm0-pin { 1527 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; 1528 }; 1529 }; 1530 1531 pwm1 { 1532 pwm1_pin: pwm1-pin { 1533 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>; 1534 }; 1535 }; 1536 1537 pwm2 { 1538 pwm2_pin: pwm2-pin { 1539 rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>; 1540 }; 1541 }; 1542 1543 pwm3 { 1544 pwm3_pin: pwm3-pin { 1545 rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>; 1546 }; 1547 }; 1548 1549 gmac { 1550 rgmii_pins: rgmii-pins { 1551 rockchip,pins = <3 30 3 &pcfg_pull_none>, 1552 <3 31 3 &pcfg_pull_none>, 1553 <3 26 3 &pcfg_pull_none>, 1554 <3 27 3 &pcfg_pull_none>, 1555 <3 28 3 &pcfg_pull_none_12ma>, 1556 <3 29 3 &pcfg_pull_none_12ma>, 1557 <3 24 3 &pcfg_pull_none_12ma>, 1558 <3 25 3 &pcfg_pull_none_12ma>, 1559 <4 0 3 &pcfg_pull_none>, 1560 <4 5 3 &pcfg_pull_none>, 1561 <4 6 3 &pcfg_pull_none>, 1562 <4 9 3 &pcfg_pull_none_12ma>, 1563 <4 4 3 &pcfg_pull_none_12ma>, 1564 <4 1 3 &pcfg_pull_none>, 1565 <4 3 3 &pcfg_pull_none>; 1566 }; 1567 1568 rmii_pins: rmii-pins { 1569 rockchip,pins = <3 30 3 &pcfg_pull_none>, 1570 <3 31 3 &pcfg_pull_none>, 1571 <3 28 3 &pcfg_pull_none>, 1572 <3 29 3 &pcfg_pull_none>, 1573 <4 0 3 &pcfg_pull_none>, 1574 <4 5 3 &pcfg_pull_none>, 1575 <4 4 3 &pcfg_pull_none>, 1576 <4 1 3 &pcfg_pull_none>, 1577 <4 2 3 &pcfg_pull_none>, 1578 <4 3 3 &pcfg_pull_none>; 1579 }; 1580 }; 1581 1582 spdif { 1583 spdif_tx: spdif-tx { 1584 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>; 1585 }; 1586 }; 1587 }; 1588 1589 power: power-controller { 1590 compatible = "rockchip,rk3288-power-controller"; 1591 #power-domain-cells = <1>; 1592 rockchip,pmu = <&pmu>; 1593 #address-cells = <1>; 1594 #size-cells = <0>; 1595 1596 pd_gpu { 1597 reg = <RK3288_PD_GPU>; 1598 clocks = <&cru ACLK_GPU>; 1599 }; 1600 1601 pd_hevc { 1602 reg = <RK3288_PD_HEVC>; 1603 clocks = <&cru ACLK_HEVC>, 1604 <&cru SCLK_HEVC_CABAC>, 1605 <&cru SCLK_HEVC_CORE>, 1606 <&cru HCLK_HEVC>; 1607 }; 1608 1609 pd_vio { 1610 reg = <RK3288_PD_VIO>; 1611 clocks = <&cru ACLK_IEP>, 1612 <&cru ACLK_ISP>, 1613 <&cru ACLK_RGA>, 1614 <&cru ACLK_VIP>, 1615 <&cru ACLK_VOP0>, 1616 <&cru ACLK_VOP1>, 1617 <&cru DCLK_VOP0>, 1618 <&cru DCLK_VOP1>, 1619 <&cru HCLK_IEP>, 1620 <&cru HCLK_ISP>, 1621 <&cru HCLK_RGA>, 1622 <&cru HCLK_VIP>, 1623 <&cru HCLK_VOP0>, 1624 <&cru HCLK_VOP1>, 1625 <&cru PCLK_EDP_CTRL>, 1626 <&cru PCLK_HDMI_CTRL>, 1627 <&cru PCLK_LVDS_PHY>, 1628 <&cru PCLK_MIPI_CSI>, 1629 <&cru PCLK_MIPI_DSI0>, 1630 <&cru PCLK_MIPI_DSI1>, 1631 <&cru SCLK_EDP_24M>, 1632 <&cru SCLK_EDP>, 1633 <&cru SCLK_HDMI_CEC>, 1634 <&cru SCLK_HDMI_HDCP>, 1635 <&cru SCLK_ISP_JPE>, 1636 <&cru SCLK_ISP>, 1637 <&cru SCLK_RGA>; 1638 }; 1639 1640 pd_video { 1641 reg = <RK3288_PD_VIDEO>; 1642 clocks = <&cru ACLK_VCODEC>, 1643 <&cru HCLK_VCODEC>; 1644 }; 1645 }; 1646}; 1647
