1/* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7/dts-v1/; 8#include "rk3288-th804.dtsi" 9 10/ { 11 model = "Rockchip RK3288 TH804 avb"; 12 compatible = "rockchip,rk3288-th804", "rockchip,rk3288"; 13 chosen { 14 bootargs = "earlycon=uart8250,mmio32,0xff690000 vmalloc=496M console=ttyFIQ0 androidboot.baseband=N/A androidboot.veritymode=enforcing androidboot.hardware=rk30board androidboot.console=ttyFIQ0 init=/init kpti=0"; 15 }; 16 vcc_camera: vcc-camera-regulator { 17 compatible = "regulator-fixed"; 18 gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; 19 pinctrl-names = "default"; 20 pinctrl-0 = <&camera_pwr>; 21 regulator-name = "vcc_camera"; 22 enable-active-high; 23 regulator-always-on; 24 regulator-boot-on; 25 }; 26}; 27 28&io_domains { 29 status = "okay"; 30 31 dvp-supply = <&vcc_18>; 32 sdcard-supply = <&vccio_sd>; 33 wifi-supply = <&vccio_wl>; 34}; 35 36&isp { 37 status = "disabled"; 38}; 39 40&i2c3 { 41 status = "okay"; 42 43 gc2145: gc2145@3c { 44 compatible = "galaxycore,gc2145"; 45 reg = <0x3c>; 46 clocks = <&cru SCLK_VIP_OUT>; 47 clock-names = "xvclk"; 48 49 /*power-gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; */ 50 pwdn-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; 51 52 rockchip,camera-module-index = <1>; 53 rockchip,camera-module-facing = "front"; 54 rockchip,camera-module-name = "CameraKing"; 55 rockchip,camera-module-lens-name = "Largan"; 56 port { 57 gc2145_out: endpoint { 58 remote-endpoint = <&isp_dvp_in>; 59 }; 60 }; 61 }; 62 63 ov8858: ov8858@36 { 64 compatible = "ovti,ov8858"; 65 reg = <0x36>; 66 clocks = <&cru SCLK_VIP_OUT>; 67 clock-names = "xvclk"; 68 69 rockchip,camera-module-index = <0>; 70 rockchip,camera-module-facing = "back"; 71 rockchip,camera-module-name = "CameraKing"; 72 rockchip,camera-module-lens-name = "Largan-9569A2"; 73 /*power-gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; */ 74 pwdn-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; 75 port { 76 ov8858_out: endpoint { 77 remote-endpoint = <&th_mipi_in>; 78 data-lanes = <1 2>; 79 }; 80 }; 81 }; 82 83}; 84 85&mipi_phy_rx0 { 86 status = "okay"; 87 88 ports { 89 #address-cells = <1>; 90 #size-cells = <0>; 91 92 port@0 { 93 reg = <0>; 94 #address-cells = <1>; 95 #size-cells = <0>; 96 97 th_mipi_in: endpoint@1 { 98 reg = <1>; 99 remote-endpoint = <&ov8858_out>; 100 data-lanes = <1 2>; 101 }; 102 }; 103 104 port@1 { 105 reg = <1>; 106 #address-cells = <1>; 107 #size-cells = <0>; 108 109 dphy_rx_out: endpoint@0 { 110 reg = <0>; 111 remote-endpoint = <&isp_mipi_in>; 112 }; 113 }; 114 }; 115}; 116 117&pinctrl { 118 camera { 119 camera_pwr: camera-pwr { 120 rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 121 }; 122 }; 123 124 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 125 bias-disable; 126 drive-strength = <4>; 127 }; 128 129 isp_pin { 130 isp_mipi: isp-mipi { 131 rockchip,pins = 132 /* cif_clkout */ 133 <2 RK_PB3 1 &pcfg_pull_none_4ma>; 134 }; 135 136 isp_dvp_d2d9: isp-d2d9 { 137 rockchip,pins = 138 /* cif_data2 ... cif_data9 */ 139 <2 RK_PA0 1 &pcfg_pull_down>, 140 <2 RK_PA1 1 &pcfg_pull_down>, 141 <2 RK_PA2 1 &pcfg_pull_down>, 142 <2 RK_PA3 1 &pcfg_pull_down>, 143 <2 RK_PA4 1 &pcfg_pull_down>, 144 <2 RK_PA5 1 &pcfg_pull_down>, 145 /* cif_sync, cif_href */ 146 <2 RK_PB0 1 &pcfg_pull_down>, 147 <2 RK_PB1 1 &pcfg_pull_down>, 148 /* cif_clkin */ 149 <2 RK_PB2 1 &pcfg_pull_down>; 150 }; 151 152 isp_dvp_d0d1: isp-d0d1 { 153 rockchip,pins = 154 /* cif_data0, cif_data1 */ 155 <2 RK_PB4 1 &pcfg_pull_down>, 156 <2 RK_PB5 1 &pcfg_pull_down>; 157 }; 158 }; 159}; 160 161&rkisp1 { 162 status = "okay"; 163 pinctrl-names = "default"; 164 pinctrl-0 = <&isp_dvp_d2d9 &isp_dvp_d0d1 &isp_mipi>; 165 port { 166 #address-cells = <1>; 167 #size-cells = <0>; 168 169 isp_dvp_in: endpoint@1 { 170 reg = <1>; 171 remote-endpoint = <&gc2145_out>; 172 }; 173 174 isp_mipi_in: endpoint@0 { 175 reg = <0>; 176 remote-endpoint = <&dphy_rx_out>; 177 }; 178 179 }; 180}; 181 182&vopb { 183 assigned-clocks = <&cru DCLK_VOP0>; 184 assigned-clock-parents = <&cru PLL_CPLL>; 185}; 186 187&vopl { 188 assigned-clocks = <&cru DCLK_VOP1>; 189 assigned-clock-parents = <&cru PLL_GPLL>; 190}; 191