xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx6dl-riotboard.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright 2014 Iain Paton <ipaton0@gmail.com>
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun#include "imx6dl.dtsi"
8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/ {
11*4882a593Smuzhiyun	model = "RIoTboard i.MX6S";
12*4882a593Smuzhiyun	compatible = "riot,imx6s-riotboard", "fsl,imx6dl";
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun	memory@10000000 {
15*4882a593Smuzhiyun		device_type = "memory";
16*4882a593Smuzhiyun		reg = <0x10000000 0x40000000>;
17*4882a593Smuzhiyun	};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	chosen {
20*4882a593Smuzhiyun		stdout-path = "serial1:115200n8";
21*4882a593Smuzhiyun	};
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun	leds {
24*4882a593Smuzhiyun		compatible = "gpio-leds";
25*4882a593Smuzhiyun		pinctrl-names = "default";
26*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_led>;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun		led0: user1 {
29*4882a593Smuzhiyun			label = "user1";
30*4882a593Smuzhiyun			gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
31*4882a593Smuzhiyun			default-state = "on";
32*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
33*4882a593Smuzhiyun		};
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun		led1: user2 {
36*4882a593Smuzhiyun			label = "user2";
37*4882a593Smuzhiyun			gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
38*4882a593Smuzhiyun			default-state = "off";
39*4882a593Smuzhiyun		};
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun	sound {
43*4882a593Smuzhiyun		compatible = "fsl,imx-audio-sgtl5000";
44*4882a593Smuzhiyun		model = "imx6-riotboard-sgtl5000";
45*4882a593Smuzhiyun		ssi-controller = <&ssi1>;
46*4882a593Smuzhiyun		audio-codec = <&codec>;
47*4882a593Smuzhiyun		audio-routing =
48*4882a593Smuzhiyun			"MIC_IN", "Mic Jack",
49*4882a593Smuzhiyun			"Mic Jack", "Mic Bias",
50*4882a593Smuzhiyun			"Headphone Jack", "HP_OUT";
51*4882a593Smuzhiyun			mux-int-port = <1>;
52*4882a593Smuzhiyun			mux-ext-port = <3>;
53*4882a593Smuzhiyun	};
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun	reg_2p5v: regulator-2p5v {
56*4882a593Smuzhiyun		compatible = "regulator-fixed";
57*4882a593Smuzhiyun		regulator-name = "2P5V";
58*4882a593Smuzhiyun		regulator-min-microvolt = <2500000>;
59*4882a593Smuzhiyun		regulator-max-microvolt = <2500000>;
60*4882a593Smuzhiyun	};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun	reg_3p3v: regulator-3p3v {
63*4882a593Smuzhiyun		compatible = "regulator-fixed";
64*4882a593Smuzhiyun		regulator-name = "3P3V";
65*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
66*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
67*4882a593Smuzhiyun	};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun	reg_usb_otg_vbus: regulator-usbotgvbus {
70*4882a593Smuzhiyun		compatible = "regulator-fixed";
71*4882a593Smuzhiyun		regulator-name = "usb_otg_vbus";
72*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
73*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
74*4882a593Smuzhiyun		gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
75*4882a593Smuzhiyun	};
76*4882a593Smuzhiyun};
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun&audmux {
79*4882a593Smuzhiyun	pinctrl-names = "default";
80*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_audmux>;
81*4882a593Smuzhiyun	status = "okay";
82*4882a593Smuzhiyun};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun&clks {
85*4882a593Smuzhiyun	fsl,pmic-stby-poweroff;
86*4882a593Smuzhiyun};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun&fec {
89*4882a593Smuzhiyun	pinctrl-names = "default";
90*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet>;
91*4882a593Smuzhiyun	phy-mode = "rgmii-id";
92*4882a593Smuzhiyun	phy-handle = <&rgmii_phy>;
93*4882a593Smuzhiyun	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
94*4882a593Smuzhiyun			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
95*4882a593Smuzhiyun	fsl,err006687-workaround-present;
96*4882a593Smuzhiyun	status = "okay";
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun	mdio {
99*4882a593Smuzhiyun		#address-cells = <1>;
100*4882a593Smuzhiyun		#size-cells = <0>;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun		/* Atheros AR8035 PHY */
103*4882a593Smuzhiyun		rgmii_phy: ethernet-phy@4 {
104*4882a593Smuzhiyun			reg = <4>;
105*4882a593Smuzhiyun			interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
106*4882a593Smuzhiyun			reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
107*4882a593Smuzhiyun			reset-assert-us = <10000>;
108*4882a593Smuzhiyun			reset-deassert-us = <1000>;
109*4882a593Smuzhiyun			qca,smarteee-tw-us-1g = <24>;
110*4882a593Smuzhiyun			qca,clk-out-frequency = <125000000>;
111*4882a593Smuzhiyun		};
112*4882a593Smuzhiyun	};
113*4882a593Smuzhiyun};
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun&gpio1 {
116*4882a593Smuzhiyun	gpio-line-names =
117*4882a593Smuzhiyun		"", "", "SD2_WP", "", "SD2_CD", "I2C3_SCL",
118*4882a593Smuzhiyun			"I2C3_SDA", "I2C4_SCL",
119*4882a593Smuzhiyun		"I2C4_SDA", "", "", "", "", "", "", "",
120*4882a593Smuzhiyun		"", "PWM3", "", "", "", "", "", "",
121*4882a593Smuzhiyun		"", "", "", "", "", "", "", "";
122*4882a593Smuzhiyun};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun&gpio3 {
125*4882a593Smuzhiyun	gpio-line-names =
126*4882a593Smuzhiyun		"", "", "", "", "", "", "", "",
127*4882a593Smuzhiyun		"", "", "", "", "", "", "", "",
128*4882a593Smuzhiyun		"", "", "", "", "", "", "USB_OTG_VBUS", "",
129*4882a593Smuzhiyun		"UART3_TXD", "UART3_RXD", "", "", "EIM_D28", "", "", "";
130*4882a593Smuzhiyun};
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun&gpio4 {
133*4882a593Smuzhiyun	gpio-line-names =
134*4882a593Smuzhiyun		"", "", "", "", "", "", "UART4_TXD", "UART4_RXD",
135*4882a593Smuzhiyun		"UART5_TXD", "UART5_RXD", "", "", "", "", "", "",
136*4882a593Smuzhiyun		"GPIO4_16", "GPIO4_17", "GPIO4_18", "GPIO4_19", "",
137*4882a593Smuzhiyun			"CSPI3_CLK", "CSPI3_MOSI", "CSPI3_MISO",
138*4882a593Smuzhiyun		"CSPI3_CS0", "CSPI3_CS1", "GPIO4_26", "GPIO4_27",
139*4882a593Smuzhiyun			"CSPI3_RDY", "PWM1", "PWM2", "GPIO4_31";
140*4882a593Smuzhiyun};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun&gpio5 {
143*4882a593Smuzhiyun	gpio-line-names =
144*4882a593Smuzhiyun		"", "", "EIM_A25", "", "", "GPIO5_05", "GPIO5_06",
145*4882a593Smuzhiyun			"GPIO5_07",
146*4882a593Smuzhiyun		"GPIO5_08", "CSPI2_CS1", "CSPI2_MOSI", "CSPI2_MISO",
147*4882a593Smuzhiyun			"CSPI2_CS0", "CSPI2_CLK", "", "",
148*4882a593Smuzhiyun		"", "", "", "", "", "", "", "",
149*4882a593Smuzhiyun		"", "", "", "", "", "", "", "";
150*4882a593Smuzhiyun};
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun&gpio7 {
153*4882a593Smuzhiyun	gpio-line-names =
154*4882a593Smuzhiyun		"SD3_CD", "SD3_WP", "", "", "", "", "", "",
155*4882a593Smuzhiyun		"", "", "", "", "", "", "", "",
156*4882a593Smuzhiyun		"", "", "", "", "", "", "", "",
157*4882a593Smuzhiyun		"", "", "", "", "", "", "", "";
158*4882a593Smuzhiyun};
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun&hdmi {
161*4882a593Smuzhiyun	ddc-i2c-bus = <&i2c2>;
162*4882a593Smuzhiyun	status = "okay";
163*4882a593Smuzhiyun};
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun&i2c1 {
166*4882a593Smuzhiyun	clock-frequency = <100000>;
167*4882a593Smuzhiyun	pinctrl-names = "default";
168*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
169*4882a593Smuzhiyun	status = "okay";
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun	codec: sgtl5000@a {
172*4882a593Smuzhiyun		compatible = "fsl,sgtl5000";
173*4882a593Smuzhiyun		reg = <0x0a>;
174*4882a593Smuzhiyun		clocks = <&clks IMX6QDL_CLK_CKO>;
175*4882a593Smuzhiyun		VDDA-supply = <&reg_2p5v>;
176*4882a593Smuzhiyun		VDDIO-supply = <&reg_3p3v>;
177*4882a593Smuzhiyun	};
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun	pmic: pf0100@8 {
180*4882a593Smuzhiyun		compatible = "fsl,pfuze100";
181*4882a593Smuzhiyun		reg = <0x08>;
182*4882a593Smuzhiyun		interrupt-parent = <&gpio5>;
183*4882a593Smuzhiyun		interrupts = <16 8>;
184*4882a593Smuzhiyun		fsl,pmic-stby-poweroff;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun		regulators {
187*4882a593Smuzhiyun			reg_vddcore: sw1ab {				/* VDDARM_IN */
188*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
189*4882a593Smuzhiyun				regulator-max-microvolt = <1875000>;
190*4882a593Smuzhiyun				regulator-always-on;
191*4882a593Smuzhiyun			};
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun			reg_vddsoc: sw1c {				/* VDDSOC_IN */
194*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
195*4882a593Smuzhiyun				regulator-max-microvolt = <1875000>;
196*4882a593Smuzhiyun				regulator-always-on;
197*4882a593Smuzhiyun			};
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun			reg_gen_3v3: sw2 {				/* VDDHIGH_IN */
200*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
201*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
202*4882a593Smuzhiyun				regulator-always-on;
203*4882a593Smuzhiyun			};
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun			reg_ddr_1v5a: sw3a {				/* NVCC_DRAM, NVCC_RGMII */
206*4882a593Smuzhiyun				regulator-min-microvolt = <400000>;
207*4882a593Smuzhiyun				regulator-max-microvolt = <1975000>;
208*4882a593Smuzhiyun				regulator-always-on;
209*4882a593Smuzhiyun			};
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun			reg_ddr_1v5b: sw3b {				/* NVCC_DRAM, NVCC_RGMII */
212*4882a593Smuzhiyun				regulator-min-microvolt = <400000>;
213*4882a593Smuzhiyun				regulator-max-microvolt = <1975000>;
214*4882a593Smuzhiyun				regulator-always-on;
215*4882a593Smuzhiyun			};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun			reg_ddr_vtt: sw4 {				/* MIPI conn */
218*4882a593Smuzhiyun				regulator-min-microvolt = <400000>;
219*4882a593Smuzhiyun				regulator-max-microvolt = <1975000>;
220*4882a593Smuzhiyun				regulator-always-on;
221*4882a593Smuzhiyun			};
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun			reg_5v_600mA: swbst {				/* not used */
224*4882a593Smuzhiyun				regulator-min-microvolt = <5000000>;
225*4882a593Smuzhiyun				regulator-max-microvolt = <5150000>;
226*4882a593Smuzhiyun			};
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun			reg_snvs_3v: vsnvs {				/* VDD_SNVS_IN */
229*4882a593Smuzhiyun				regulator-min-microvolt = <1500000>;
230*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
231*4882a593Smuzhiyun				regulator-always-on;
232*4882a593Smuzhiyun			};
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun			vref_reg: vrefddr {				/* VREF_DDR */
235*4882a593Smuzhiyun				regulator-boot-on;
236*4882a593Smuzhiyun				regulator-always-on;
237*4882a593Smuzhiyun			};
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun			reg_vgen1_1v5: vgen1 {				/* not used */
240*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
241*4882a593Smuzhiyun				regulator-max-microvolt = <1550000>;
242*4882a593Smuzhiyun			};
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun			reg_vgen2_1v2_eth: vgen2 {			/* pcie ? */
245*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
246*4882a593Smuzhiyun				regulator-max-microvolt = <1550000>;
247*4882a593Smuzhiyun				regulator-always-on;
248*4882a593Smuzhiyun			};
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun			reg_vgen3_2v8: vgen3 {				/* not used */
251*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
252*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
253*4882a593Smuzhiyun			};
254*4882a593Smuzhiyun			reg_vgen4_1v8: vgen4 {				/* NVCC_SD3 */
255*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
256*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
257*4882a593Smuzhiyun				regulator-always-on;
258*4882a593Smuzhiyun			};
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun			reg_vgen5_2v5_sgtl: vgen5 {			/* Pwr LED & 5V0_delayed enable */
261*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
262*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
263*4882a593Smuzhiyun				regulator-always-on;
264*4882a593Smuzhiyun			};
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun			reg_vgen6_3v3: vgen6 {				/* #V#_DELAYED enable, MIPI */
267*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
268*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
269*4882a593Smuzhiyun				regulator-always-on;
270*4882a593Smuzhiyun			};
271*4882a593Smuzhiyun		};
272*4882a593Smuzhiyun	};
273*4882a593Smuzhiyun};
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun&i2c2 {
276*4882a593Smuzhiyun	clock-frequency = <100000>;
277*4882a593Smuzhiyun	pinctrl-names = "default";
278*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
279*4882a593Smuzhiyun	status = "okay";
280*4882a593Smuzhiyun};
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun&i2c4 {
283*4882a593Smuzhiyun	clock-frequency = <100000>;
284*4882a593Smuzhiyun	pinctrl-names = "default";
285*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c4>;
286*4882a593Smuzhiyun	clocks = <&clks 116>;
287*4882a593Smuzhiyun	status = "okay";
288*4882a593Smuzhiyun};
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun&pwm1 {
291*4882a593Smuzhiyun	pinctrl-names = "default";
292*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm1>;
293*4882a593Smuzhiyun	status = "okay";
294*4882a593Smuzhiyun};
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun&pwm2 {
297*4882a593Smuzhiyun	pinctrl-names = "default";
298*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm2>;
299*4882a593Smuzhiyun	status = "okay";
300*4882a593Smuzhiyun};
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun&pwm3 {
303*4882a593Smuzhiyun	pinctrl-names = "default";
304*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm3>;
305*4882a593Smuzhiyun	status = "okay";
306*4882a593Smuzhiyun};
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun&pwm4 {
309*4882a593Smuzhiyun	pinctrl-names = "default";
310*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm4>;
311*4882a593Smuzhiyun	status = "okay";
312*4882a593Smuzhiyun};
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun&ssi1 {
315*4882a593Smuzhiyun	status = "okay";
316*4882a593Smuzhiyun};
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun&uart1 {
319*4882a593Smuzhiyun	pinctrl-names = "default";
320*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
321*4882a593Smuzhiyun	status = "okay";
322*4882a593Smuzhiyun};
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun&uart2 {
325*4882a593Smuzhiyun	pinctrl-names = "default";
326*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart2>;
327*4882a593Smuzhiyun	status = "okay";
328*4882a593Smuzhiyun};
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun&uart3 {
331*4882a593Smuzhiyun	pinctrl-names = "default";
332*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart3>;
333*4882a593Smuzhiyun	status = "okay";
334*4882a593Smuzhiyun};
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun&uart4 {
337*4882a593Smuzhiyun	pinctrl-names = "default";
338*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart4>;
339*4882a593Smuzhiyun	status = "okay";
340*4882a593Smuzhiyun};
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun&uart5 {
343*4882a593Smuzhiyun	pinctrl-names = "default";
344*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart5>;
345*4882a593Smuzhiyun	status = "okay";
346*4882a593Smuzhiyun};
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun&usbh1 {
349*4882a593Smuzhiyun	dr_mode = "host";
350*4882a593Smuzhiyun	disable-over-current;
351*4882a593Smuzhiyun	status = "okay";
352*4882a593Smuzhiyun};
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun&usbotg {
355*4882a593Smuzhiyun	vbus-supply = <&reg_usb_otg_vbus>;
356*4882a593Smuzhiyun	pinctrl-names = "default";
357*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbotg>;
358*4882a593Smuzhiyun	disable-over-current;
359*4882a593Smuzhiyun	dr_mode = "otg";
360*4882a593Smuzhiyun	status = "okay";
361*4882a593Smuzhiyun};
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun&usdhc2 {
364*4882a593Smuzhiyun	pinctrl-names = "default";
365*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2>;
366*4882a593Smuzhiyun	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
367*4882a593Smuzhiyun	wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
368*4882a593Smuzhiyun	vmmc-supply = <&reg_3p3v>;
369*4882a593Smuzhiyun	status = "okay";
370*4882a593Smuzhiyun};
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun&usdhc3 {
373*4882a593Smuzhiyun	pinctrl-names = "default";
374*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc3>;
375*4882a593Smuzhiyun	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
376*4882a593Smuzhiyun	wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
377*4882a593Smuzhiyun	vmmc-supply = <&reg_3p3v>;
378*4882a593Smuzhiyun	status = "okay";
379*4882a593Smuzhiyun};
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun&usdhc4 {
382*4882a593Smuzhiyun	pinctrl-names = "default";
383*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc4>;
384*4882a593Smuzhiyun	vmmc-supply = <&reg_3p3v>;
385*4882a593Smuzhiyun	non-removable;
386*4882a593Smuzhiyun	status = "okay";
387*4882a593Smuzhiyun};
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun&iomuxc {
390*4882a593Smuzhiyun	pinctrl-names = "default";
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun	imx6-riotboard {
393*4882a593Smuzhiyun		pinctrl_audmux: audmuxgrp {
394*4882a593Smuzhiyun			fsl,pins = <
395*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
396*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
397*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
398*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
399*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0		/* CAM_MCLK */
400*4882a593Smuzhiyun			>;
401*4882a593Smuzhiyun		};
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun		pinctrl_ecspi1: ecspi1grp {
404*4882a593Smuzhiyun			fsl,pins = <
405*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
406*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
407*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
408*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17	0x000b1		/* CS0 */
409*4882a593Smuzhiyun			>;
410*4882a593Smuzhiyun		};
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun		pinctrl_ecspi2: ecspi2grp {
413*4882a593Smuzhiyun			fsl,pins = <
414*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09	0x000b1		/* CS1 */
415*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI	0x100b1
416*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO	0x100b1
417*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12	0x000b1		/* CS0 */
418*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK	0x100b1
419*4882a593Smuzhiyun			>;
420*4882a593Smuzhiyun		};
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun		pinctrl_ecspi3: ecspi3grp {
423*4882a593Smuzhiyun			fsl,pins = <
424*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK	0x100b1
425*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI	0x100b1
426*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO	0x100b1
427*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24	0x000b1		/* CS0 */
428*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25	0x000b1		/* CS1 */
429*4882a593Smuzhiyun			>;
430*4882a593Smuzhiyun		};
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun		pinctrl_enet: enetgrp {
433*4882a593Smuzhiyun			fsl,pins = <
434*4882a593Smuzhiyun				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
435*4882a593Smuzhiyun				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
436*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
437*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
438*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
439*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
440*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
441*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
442*4882a593Smuzhiyun				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x0a0b1		/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
443*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030		/* AR8035 pin strapping: IO voltage: pull up */
444*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x13030		/* AR8035 pin strapping: PHYADDR#0: pull down */
445*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x13030		/* AR8035 pin strapping: PHYADDR#1: pull down */
446*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030		/* AR8035 pin strapping: MODE#1: pull up */
447*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030		/* AR8035 pin strapping: MODE#3: pull up */
448*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x130b0		/* AR8035 pin strapping: MODE#0: pull down */
449*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8	/* GPIO16 -> AR8035 25MHz */
450*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D31__GPIO3_IO31		0x130b0		/* RGMII_nRST */
451*4882a593Smuzhiyun				MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x180b0		/* AR8035 interrupt */
452*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
453*4882a593Smuzhiyun			>;
454*4882a593Smuzhiyun		};
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun		pinctrl_i2c1: i2c1grp {
457*4882a593Smuzhiyun			fsl,pins = <
458*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT8__I2C1_SDA		0x4001b8b1
459*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT9__I2C1_SCL		0x4001b8b1
460*4882a593Smuzhiyun			>;
461*4882a593Smuzhiyun		};
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun		pinctrl_i2c2: i2c2grp {
464*4882a593Smuzhiyun			fsl,pins = <
465*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
466*4882a593Smuzhiyun				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
467*4882a593Smuzhiyun			>;
468*4882a593Smuzhiyun		};
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun		pinctrl_i2c3: i2c3grp {
471*4882a593Smuzhiyun			fsl,pins = <
472*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_5__I2C3_SCL		0x4001b8b1
473*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
474*4882a593Smuzhiyun			>;
475*4882a593Smuzhiyun		};
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun		pinctrl_i2c4: i2c4grp {
478*4882a593Smuzhiyun			fsl,pins = <
479*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_7__I2C4_SCL             0x4001b8b1
480*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_8__I2C4_SDA             0x4001b8b1
481*4882a593Smuzhiyun			>;
482*4882a593Smuzhiyun		};
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun		pinctrl_led: ledgrp {
485*4882a593Smuzhiyun			fsl,pins = <
486*4882a593Smuzhiyun				MX6QDL_PAD_EIM_A25__GPIO5_IO02		0x1b0b1	/* user led0 */
487*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D28__GPIO3_IO28		0x1b0b1	/* user led1 */
488*4882a593Smuzhiyun			>;
489*4882a593Smuzhiyun		};
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun		pinctrl_pwm1: pwm1grp {
492*4882a593Smuzhiyun			fsl,pins = <
493*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT8__PWM1_OUT		0x1b0b1
494*4882a593Smuzhiyun			>;
495*4882a593Smuzhiyun		};
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun		pinctrl_pwm2: pwm2grp {
498*4882a593Smuzhiyun			fsl,pins = <
499*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT9__PWM2_OUT		0x1b0b1
500*4882a593Smuzhiyun			>;
501*4882a593Smuzhiyun		};
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun		pinctrl_pwm3: pwm3grp {
504*4882a593Smuzhiyun			fsl,pins = <
505*4882a593Smuzhiyun				MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
506*4882a593Smuzhiyun			>;
507*4882a593Smuzhiyun		};
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun		pinctrl_pwm4: pwm4grp {
510*4882a593Smuzhiyun			fsl,pins = <
511*4882a593Smuzhiyun				MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
512*4882a593Smuzhiyun			>;
513*4882a593Smuzhiyun		};
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun		pinctrl_uart1: uart1grp {
516*4882a593Smuzhiyun			fsl,pins = <
517*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
518*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
519*4882a593Smuzhiyun			>;
520*4882a593Smuzhiyun		};
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun		pinctrl_uart2: uart2grp {
523*4882a593Smuzhiyun			fsl,pins = <
524*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D26__UART2_TX_DATA	0x1b0b1
525*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D27__UART2_RX_DATA	0x1b0b1
526*4882a593Smuzhiyun			>;
527*4882a593Smuzhiyun		};
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun		pinctrl_uart3: uart3grp {
530*4882a593Smuzhiyun			fsl,pins = <
531*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
532*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
533*4882a593Smuzhiyun			>;
534*4882a593Smuzhiyun		};
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun		pinctrl_uart4: uart4grp {
537*4882a593Smuzhiyun			fsl,pins = <
538*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
539*4882a593Smuzhiyun				MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
540*4882a593Smuzhiyun			>;
541*4882a593Smuzhiyun		};
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun		pinctrl_uart5: uart5grp {
544*4882a593Smuzhiyun			fsl,pins = <
545*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
546*4882a593Smuzhiyun				MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
547*4882a593Smuzhiyun			>;
548*4882a593Smuzhiyun		};
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun		pinctrl_usbotg: usbotggrp {
551*4882a593Smuzhiyun			fsl,pins = <
552*4882a593Smuzhiyun				MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x17059
553*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x000b0	/* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */
554*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D21__USB_OTG_OC		0x1b0b0
555*4882a593Smuzhiyun			>;
556*4882a593Smuzhiyun		};
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun		pinctrl_usdhc2: usdhc2grp {
559*4882a593Smuzhiyun			fsl,pins = <
560*4882a593Smuzhiyun				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
561*4882a593Smuzhiyun				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
562*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
563*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
564*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
565*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
566*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x1b0b0	/* SD2 CD */
567*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x1f0b0	/* SD2 WP */
568*4882a593Smuzhiyun			>;
569*4882a593Smuzhiyun		};
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun		pinctrl_usdhc3: usdhc3grp {
572*4882a593Smuzhiyun			fsl,pins = <
573*4882a593Smuzhiyun				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
574*4882a593Smuzhiyun				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
575*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
576*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
577*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
578*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
579*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x1b0b0	/* SD3 CD */
580*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT4__GPIO7_IO01		0x1f0b0	/* SD3 WP */
581*4882a593Smuzhiyun			>;
582*4882a593Smuzhiyun		};
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun		pinctrl_usdhc4: usdhc4grp {
585*4882a593Smuzhiyun			fsl,pins = <
586*4882a593Smuzhiyun				MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
587*4882a593Smuzhiyun				MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
588*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
589*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
590*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
591*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
592*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_ALE__GPIO6_IO08	0x17059	/* SD4 RST (eMMC) */
593*4882a593Smuzhiyun			>;
594*4882a593Smuzhiyun		};
595*4882a593Smuzhiyun	};
596*4882a593Smuzhiyun};
597