1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. 3 4#include <dt-bindings/clock/rk1808-cru.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/pinctrl/rockchip.h> 8#include <dt-bindings/power/rk1808-power.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/soc/rockchip,boot-mode.h> 11#include <dt-bindings/soc/rockchip-system-status.h> 12#include <dt-bindings/suspend/rockchip-rk1808.h> 13#include <dt-bindings/thermal/thermal.h> 14#include "rk1808-dram-default-timing.dtsi" 15 16/ { 17 compatible = "rockchip,rk1808"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 i2c4 = &i2c4; 29 i2c5 = &i2c5; 30 serial0 = &uart0; 31 serial1 = &uart1; 32 serial2 = &uart2; 33 serial3 = &uart3; 34 serial4 = &uart4; 35 serial5 = &uart5; 36 serial6 = &uart6; 37 serial7 = &uart7; 38 spi0 = &spi0; 39 spi1 = &spi1; 40 spi2 = &spi2; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 cpu0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a35", "arm,armv8"; 50 reg = <0x0 0x0>; 51 enable-method = "psci"; 52 clocks = <&cru ARMCLK>; 53 operating-points-v2 = <&cpu0_opp_table>; 54 dynamic-power-coefficient = <74>; 55 #cooling-cells = <2>; 56 cpu-idle-states = <&CPU_SLEEP>; 57 power-model { 58 compatible = "simple-power-model"; 59 ref-leakage = <31>; 60 static-coefficient = <100000>; 61 ts = <597400 241050 (-2450) 70>; 62 thermal-zone = "soc-thermal"; 63 }; 64 }; 65 66 cpu1: cpu@1 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a35", "arm,armv8"; 69 reg = <0x0 0x1>; 70 enable-method = "psci"; 71 clocks = <&cru ARMCLK>; 72 operating-points-v2 = <&cpu0_opp_table>; 73 dynamic-power-coefficient = <74>; 74 cpu-idle-states = <&CPU_SLEEP>; 75 }; 76 77 idle-states { 78 entry-method = "psci"; 79 80 CPU_SLEEP: cpu-sleep { 81 compatible = "arm,idle-state"; 82 local-timer-stop; 83 arm,psci-suspend-param = <0x0010000>; 84 entry-latency-us = <120>; 85 exit-latency-us = <250>; 86 min-residency-us = <900>; 87 }; 88 89 CLUSTER_SLEEP: cluster-sleep { 90 compatible = "arm,idle-state"; 91 local-timer-stop; 92 arm,psci-suspend-param = <0x1010000>; 93 entry-latency-us = <400>; 94 exit-latency-us = <500>; 95 min-residency-us = <2000>; 96 }; 97 }; 98 }; 99 100 cpu0_opp_table: cpu0-opp-table { 101 compatible = "operating-points-v2"; 102 opp-shared; 103 104 rockchip,temp-hysteresis = <5000>; 105 rockchip,low-temp = <0>; 106 rockchip,low-temp-min-volt = <800000>; 107 rockchip,low-temp-adjust-volt = < 108 /* MHz MHz uV */ 109 0 1608 50000 110 >; 111 112 rockchip,max-volt = <950000>; 113 rockchip,evb-irdrop = <25000>; 114 nvmem-cells = <&cpu_leakage>; 115 nvmem-cell-names = "leakage"; 116 117 rockchip,pvtm-voltage-sel = < 118 0 69000 0 119 69001 74000 1 120 74001 99999 2 121 >; 122 rockchip,pvtm-freq = <408000>; 123 rockchip,pvtm-volt = <800000>; 124 rockchip,pvtm-ch = <0 0>; 125 rockchip,pvtm-sample-time = <1000>; 126 rockchip,pvtm-number = <10>; 127 rockchip,pvtm-error = <1000>; 128 rockchip,pvtm-ref-temp = <25>; 129 rockchip,pvtm-temp-prop = <(-20) (-26)>; 130 rockchip,thermal-zone = "soc-thermal"; 131 132 opp-408000000 { 133 opp-hz = /bits/ 64 <408000000>; 134 opp-microvolt = <750000 750000 950000>; 135 clock-latency-ns = <40000>; 136 opp-suspend; 137 }; 138 opp-600000000 { 139 opp-hz = /bits/ 64 <600000000>; 140 opp-microvolt = <750000 750000 950000>; 141 clock-latency-ns = <40000>; 142 }; 143 opp-816000000 { 144 opp-hz = /bits/ 64 <816000000>; 145 opp-microvolt = <750000 750000 950000>; 146 clock-latency-ns = <40000>; 147 }; 148 opp-1008000000 { 149 opp-hz = /bits/ 64 <1008000000>; 150 opp-microvolt = <750000 750000 950000>; 151 clock-latency-ns = <40000>; 152 }; 153 opp-1200000000 { 154 opp-hz = /bits/ 64 <1200000000>; 155 opp-microvolt = <800000 800000 950000>; 156 opp-microvolt-L0 = <800000 800000 950000>; 157 opp-microvolt-L1 = <750000 750000 950000>; 158 opp-microvolt-L2 = <750000 750000 950000>; 159 clock-latency-ns = <40000>; 160 }; 161 opp-1296000000 { 162 opp-hz = /bits/ 64 <1296000000>; 163 opp-microvolt = <825000 825000 950000>; 164 opp-microvolt-L0 = <825000 825000 950000>; 165 opp-microvolt-L1 = <775000 775000 950000>; 166 opp-microvolt-L2 = <750000 750000 950000>; 167 clock-latency-ns = <40000>; 168 }; 169 opp-1416000000 { 170 opp-hz = /bits/ 64 <1416000000>; 171 opp-microvolt = <850000 850000 950000>; 172 opp-microvolt-L0 = <850000 850000 950000>; 173 opp-microvolt-L1 = <800000 800000 950000>; 174 opp-microvolt-L2 = <775000 775000 950000>; 175 clock-latency-ns = <40000>; 176 }; 177 opp-1512000000 { 178 opp-hz = /bits/ 64 <1512000000>; 179 opp-microvolt = <875000 875000 950000>; 180 opp-microvolt-L0 = <875000 875000 950000>; 181 opp-microvolt-L1 = <825000 825000 950000>; 182 opp-microvolt-L2 = <800000 800000 950000>; 183 clock-latency-ns = <40000>; 184 }; 185 opp-1608000000 { 186 opp-hz = /bits/ 64 <1608000000>; 187 opp-microvolt = <900000 900000 950000>; 188 opp-microvolt-L0 = <900000 900000 950000>; 189 opp-microvolt-L1 = <850000 850000 950000>; 190 opp-microvolt-L2 = <825000 825000 950000>; 191 clock-latency-ns = <40000>; 192 }; 193 }; 194 195 arm-pmu { 196 compatible = "arm,cortex-a53-pmu"; 197 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 199 interrupt-affinity = <&cpu0>, <&cpu1>; 200 }; 201 202 cpuinfo { 203 compatible = "rockchip,cpuinfo"; 204 nvmem-cells = <&efuse_id>, <&efuse_cpu_version>; 205 nvmem-cell-names = "id", "cpu-version"; 206 }; 207 208 bus_soc: bus-soc { 209 compatible = "rockchip,rk1808-bus"; 210 rockchip,busfreq-policy = "smc"; 211 soc-bus0 { 212 bus-id = <0>; 213 cfg-val = <0x1e0>; 214 enable-msk = <0x407f>; 215 status = "okay"; 216 }; 217 soc-bus1 { 218 bus-id = <1>; 219 cfg-val = <0x12c0>; 220 enable-msk = <0x41ff>; 221 status = "okay"; 222 }; 223 soc-bus2 { 224 bus-id = <2>; 225 cfg-val = <0x12c0>; 226 enable-msk = <0x4005>; 227 status = "okay"; 228 }; 229 soc-bus3 { 230 bus-id = <3>; 231 cfg-val = <0x12c0>; 232 enable-msk = <0x4001>; 233 status = "okay"; 234 }; 235 soc-bus4 { 236 bus-id = <4>; 237 cfg-val = <0x12c0>; 238 enable-msk = <0x4001>; 239 status = "disabled"; 240 }; 241 }; 242 243 gmac_clkin: external-gmac-clock { 244 compatible = "fixed-clock"; 245 clock-frequency = <125000000>; 246 clock-output-names = "gmac_clkin"; 247 #clock-cells = <0>; 248 }; 249 250 mipi_csi2: mipi-csi2 { 251 compatible = "rockchip,rk1808-mipi-csi2"; 252 rockchip,hw = <&mipi_csi2_hw>; 253 status = "disabled"; 254 }; 255 256 psci { 257 compatible = "arm,psci-1.0"; 258 method = "smc"; 259 }; 260 261 rockchip_suspend: rockchip-suspend { 262 compatible = "rockchip,pm-rk1808"; 263 status = "disabled"; 264 rockchip,sleep-debug-en = <0>; 265 rockchip,sleep-mode-config = < 266 (0 267 | RKPM_SLP_ARMOFF 268 | RKPM_SLP_PMU_PMUALIVE_32K 269 | RKPM_SLP_PMU_DIS_OSC 270 | RKPM_SLP_PMIC_LP 271 | RKPM_SLP_32K_EXT 272 ) 273 >; 274 rockchip,wakeup-config = < 275 (0 276 | RKPM_GPIO_WKUP_EN 277 ) 278 >; 279 }; 280 281 timer { 282 compatible = "arm,armv8-timer"; 283 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 284 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 285 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 286 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 287 arm,no-tick-in-suspend; 288 }; 289 290 xin24m: xin24m { 291 compatible = "fixed-clock"; 292 clock-frequency = <24000000>; 293 clock-output-names = "xin24m"; 294 #clock-cells = <0>; 295 }; 296 297 xin32k: xin32k { 298 compatible = "fixed-clock"; 299 clock-frequency = <32768>; 300 clock-output-names = "xin32k"; 301 #clock-cells = <0>; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&clkin_32k>; 304 }; 305 306 pcie0: pcie@fc400000 { 307 compatible = "rockchip,rk1808-pcie", "snps,dw-pcie"; 308 #address-cells = <3>; 309 #size-cells = <2>; 310 bus-range = <0x0 0x1f>; 311 clocks = <&cru HSCLK_PCIE>, <&cru LSCLK_PCIE>, 312 <&cru ACLK_PCIE>, <&cru PCLK_PCIE>, 313 <&cru SCLK_PCIE_AUX>; 314 clock-names = "hsclk", "lsclk", 315 "aclk", "pclk", 316 "sclk-aux"; 317 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 321 interrupt-names = "sys", "legacy", "msg", "err"; 322 linux,pci-domain = <0>; 323 num-ib-windows = <6>; 324 num-ob-windows = <2>; 325 msi-map = <0x0 &its 0x0 0x1000>; 326 num-lanes = <2>; 327 phys = <&combphy PHY_TYPE_PCIE>; 328 phy-names = "pcie-phy"; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&pcie_clkreq>; 331 power-domains = <&power RK1808_PD_PCIE>; 332 ranges = <0x00000800 0x0 0xf8000000 0x0 0xf8000000 0x0 0x800000 333 0x83000000 0x0 0xf8800000 0x0 0xf8800000 0x0 0x3700000 334 0x81000000 0x0 0xfbf00000 0x0 0xfbf00000 0x0 0x100000>; 335 reg = <0x0 0xfc000000 0x0 0x400000>, 336 <0x0 0xfc400000 0x0 0x10000>; 337 reg-names = "pcie-dbi", "pcie-apb"; 338 resets = <&cru SRST_PCIE_NIU_H>, <&cru SRST_PCIE_NIU_L>, 339 <&cru SRST_PCIEGRF_P>, <&cru SRST_PCIECTL_P>, 340 <&cru SRST_PCIECTL_POWERUP>, <&cru SRST_PCIECTL_MST_A>, 341 <&cru SRST_PCIECTL_SLV_A>, <&cru SRST_PCIECTL_DBI_A>, 342 <&cru SRST_PCIECTL_BUTTON>, <&cru SRST_PCIECTL_PE>, 343 <&cru SRST_PCIECTL_CORE>, <&cru SRST_PCIECTL_NSTICKY>, 344 <&cru SRST_PCIECTL_STICKY>, <&cru SRST_PCIECTL_PWR>, 345 <&cru SRST_PCIE_NIU_A>, <&cru SRST_PCIE_NIU_P>; 346 reset-names = "niu-h", "niu-l", "grf-p", "ctl-p", 347 "ctl-powerup", "ctl-mst-a", "ctl-slv-a", 348 "ctl-dbi-a", "ctl-button", "ctl-pe", 349 "ctl-core", "ctl-nsticky", "ctl-sticky", 350 "ctl-pwr", "ctl-niu-a", "ctl-niu-p"; 351 rockchip,usbpciegrf = <&usb_pcie_grf>; 352 rockchip,pmugrf = <&pmugrf>; 353 status = "disabled"; 354 }; 355 356 usbdrd3: usb { 357 compatible = "rockchip,rk1808-dwc3", "rockchip,rk3399-dwc3"; 358 clocks = <&cru SCLK_USB3_OTG0_REF>, <&cru ACLK_USB3OTG>, 359 <&cru SCLK_USB3_OTG0_SUSPEND>; 360 clock-names = "ref_clk", "bus_clk", 361 "suspend_clk"; 362 assigned-clocks = <&cru SCLK_USB3_OTG0_SUSPEND>; 363 assigned-clock-rates = <24000000>; 364 power-domains = <&power RK1808_PD_PCIE>; 365 resets = <&cru SRST_USB3_OTG_A>; 366 reset-names = "usb3-otg"; 367 #address-cells = <2>; 368 #size-cells = <2>; 369 ranges; 370 status = "disabled"; 371 372 usbdrd_dwc3: dwc3@fd000000 { 373 compatible = "snps,dwc3"; 374 reg = <0x0 0xfd000000 0x0 0x200000>; 375 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 376 dr_mode = "otg"; 377 phys = <&u2phy_otg>, <&combphy PHY_TYPE_USB3>; 378 phy-names = "usb2-phy", "usb3-phy"; 379 phy_type = "utmi_wide"; 380 snps,dis_enblslpm_quirk; 381 snps,dis-u1u2-quirk; 382 snps,dis-u2-freeclk-exists-quirk; 383 snps,dis_u2_susphy_quirk; 384 snps,dis_u3_susphy_quirk; 385 snps,dis-del-phy-power-chg-quirk; 386 snps,tx-ipgap-linecheck-dis-quirk; 387 snps,xhci-trb-ent-quirk; 388 snps,parkmode-disable-ss-quirk; 389 status = "disabled"; 390 }; 391 }; 392 393 grf: syscon@fe000000 { 394 compatible = "rockchip,rk1808-grf", "syscon", "simple-mfd"; 395 reg = <0x0 0xfe000000 0x0 0x1000>; 396 #address-cells = <1>; 397 #size-cells = <1>; 398 399 npu_pvtm: npu-pvtm { 400 compatible = "rockchip,rk1808-npu-pvtm"; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 status = "okay"; 404 405 pvtm@2 { 406 reg = <2>; 407 clocks = <&cru SCLK_PVTM_NPU>; 408 clock-names = "clk"; 409 }; 410 }; 411 412 rgb: rgb { 413 compatible = "rockchip,rk1808-rgb"; 414 status = "disabled"; 415 416 ports { 417 #address-cells = <1>; 418 #size-cells = <0>; 419 420 port@0 { 421 reg = <0>; 422 423 rgb_in_vop_lite: endpoint { 424 remote-endpoint = <&vop_lite_out_rgb>; 425 }; 426 }; 427 }; 428 }; 429 }; 430 431 usb2phy_grf: syscon@fe010000 { 432 compatible = "rockchip,rk1808-usb2phy-grf", "syscon", 433 "simple-mfd"; 434 reg = <0x0 0xfe010000 0x0 0x8000>; 435 #address-cells = <1>; 436 #size-cells = <1>; 437 438 u2phy: usb2-phy@100 { 439 compatible = "rockchip,rk1808-usb2phy"; 440 reg = <0x100 0x10>; 441 clocks = <&cru SCLK_USBPHY_REF>; 442 clock-names = "phyclk"; 443 #clock-cells = <0>; 444 assigned-clocks = <&cru USB480M>; 445 assigned-clock-parents = <&u2phy>; 446 clock-output-names = "usb480m_phy"; 447 status = "disabled"; 448 449 u2phy_host: host-port { 450 #phy-cells = <0>; 451 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 452 interrupt-names = "linestate"; 453 status = "disabled"; 454 }; 455 456 u2phy_otg: otg-port { 457 #phy-cells = <0>; 458 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 461 interrupt-names = "otg-bvalid", "otg-id", 462 "linestate"; 463 status = "disabled"; 464 }; 465 }; 466 }; 467 468 combphy_grf: syscon@fe018000 { 469 compatible = "rockchip,usb3phy-grf", "syscon"; 470 reg = <0x0 0xfe018000 0x0 0x8000>; 471 }; 472 473 pmugrf: syscon@fe020000 { 474 compatible = "rockchip,rk1808-pmugrf", "syscon", "simple-mfd"; 475 reg = <0x0 0xfe020000 0x0 0x1000>; 476 #address-cells = <1>; 477 #size-cells = <1>; 478 479 pmu_pvtm: pmu-pvtm { 480 compatible = "rockchip,rk1808-pmu-pvtm"; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 status = "okay"; 484 485 pvtm@1 { 486 reg = <1>; 487 clocks = <&cru SCLK_PVTM_PMU>; 488 clock-names = "clk"; 489 }; 490 }; 491 492 reboot-mode { 493 compatible = "syscon-reboot-mode"; 494 offset = <0x200>; 495 mode-bootloader = <BOOT_BL_DOWNLOAD>; 496 mode-charge = <BOOT_CHARGING>; 497 mode-fastboot = <BOOT_FASTBOOT>; 498 mode-loader = <BOOT_BL_DOWNLOAD>; 499 mode-normal = <BOOT_NORMAL>; 500 mode-recovery = <BOOT_RECOVERY>; 501 mode-ums = <BOOT_UMS>; 502 }; 503 }; 504 505 usb_pcie_grf: syscon@fe040000 { 506 compatible = "rockchip,usb-pcie-grf", "syscon"; 507 reg = <0x0 0xfe040000 0x0 0x1000>; 508 }; 509 510 coregrf: syscon@fe050000 { 511 compatible = "rockchip,rk1808-coregrf", "syscon", "simple-mfd"; 512 reg = <0x0 0xfe050000 0x0 0x1000>; 513 #address-cells = <1>; 514 #size-cells = <1>; 515 516 pvtm: pvtm { 517 compatible = "rockchip,rk1808-pvtm"; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 status = "okay"; 521 522 pvtm@0 { 523 reg = <0>; 524 clocks = <&cru SCLK_PVTM_CORE>; 525 clock-names = "clk"; 526 }; 527 }; 528 }; 529 530 qos_npu: qos@fe850000 { 531 compatible = "syscon"; 532 reg = <0x0 0xfe850000 0x0 0x20>; 533 }; 534 535 qos_pcie: qos@fe880000 { 536 compatible = "syscon"; 537 reg = <0x0 0xfe880000 0x0 0x20>; 538 status = "disabled"; 539 }; 540 541 qos_usb2: qos@fe890000 { 542 compatible = "syscon"; 543 reg = <0x0 0xfe890000 0x0 0x20>; 544 status = "disabled"; 545 }; 546 547 qos_usb3: qos@fe890080 { 548 compatible = "syscon"; 549 reg = <0x0 0xfe890080 0x0 0x20>; 550 status = "disabled"; 551 }; 552 553 qos_isp: qos@fe8a0000 { 554 compatible = "syscon"; 555 reg = <0x0 0xfe8a0000 0x0 0x20>; 556 }; 557 558 qos_rga_rd: qos@fe8a0080 { 559 compatible = "syscon"; 560 reg = <0x0 0xfe8a0080 0x0 0x20>; 561 }; 562 563 qos_rga_wr: qos@fe8a0100 { 564 compatible = "syscon"; 565 reg = <0x0 0xfe8a0100 0x0 0x20>; 566 }; 567 568 qos_cif: qos@fe8a0180 { 569 compatible = "syscon"; 570 reg = <0x0 0xfe8a0180 0x0 0x20>; 571 }; 572 573 qos_vop_raw: qos@fe8b0000 { 574 compatible = "syscon"; 575 reg = <0x0 0xfe8b0000 0x0 0x20>; 576 }; 577 578 qos_vop_lite: qos@fe8b0080 { 579 compatible = "syscon"; 580 reg = <0x0 0xfe8b0080 0x0 0x20>; 581 }; 582 583 qos_vpu: qos@fe8c0000 { 584 compatible = "syscon"; 585 reg = <0x0 0xfe8c0000 0x0 0x20>; 586 }; 587 588 sram: sram@fec00000 { 589 compatible = "mmio-sram"; 590 reg = <0x0 0xfec00000 0x0 0x200000>; 591 #address-cells = <1>; 592 #size-cells = <1>; 593 ranges = <0 0x0 0xfec00000 0x200000>; 594 /* reserved for ddr dvfs and system suspend/resume */ 595 ddr-sram@0 { 596 reg = <0x0 0x8000>; 597 }; 598 /* reserved for vad audio buffer */ 599 vad_sram: vad-sram@1c0000 { 600 reg = <0x1c0000 0x40000>; 601 }; 602 }; 603 604 hwlock: hwspinlock@ff040000 { 605 compatible = "rockchip,hwspinlock"; 606 reg = <0 0xff040000 0 0x10000>; 607 #hwlock-cells = <1>; 608 }; 609 610 gic: interrupt-controller@ff100000 { 611 compatible = "arm,gic-v3"; 612 #interrupt-cells = <3>; 613 #address-cells = <2>; 614 #size-cells = <2>; 615 ranges; 616 interrupt-controller; 617 618 reg = <0x0 0xff100000 0 0x10000>, /* GICD */ 619 <0x0 0xff140000 0 0xc0000>, /* GICR */ 620 <0x0 0xff300000 0 0x10000>, /* GICC */ 621 <0x0 0xff310000 0 0x10000>, /* GICH */ 622 <0x0 0xff320000 0 0x10000>; /* GICV */ 623 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 624 its: interrupt-controller@ff120000 { 625 compatible = "arm,gic-v3-its"; 626 msi-controller; 627 reg = <0x0 0xff120000 0x0 0x20000>; 628 }; 629 }; 630 631 efuse: efuse@ff260000 { 632 compatible = "rockchip,rk1808-efuse"; 633 reg = <0x0 0xff3b0000 0x0 0x50>; 634 #address-cells = <1>; 635 #size-cells = <1>; 636 clocks = <&cru SCLK_EFUSE_NS>, <&cru PCLK_EFUSE>; 637 clock-names = "sclk_efuse", "pclk_efuse"; 638 assigned-clocks = <&cru SCLK_EFUSE_NS>; 639 assigned-clock-rates = <24000000>; 640 rockchip,efuse-size = <0x20>; 641 642 /* Data cells */ 643 efuse_id: id@7 { 644 reg = <0x07 0x10>; 645 }; 646 cpu_leakage: cpu-leakage@17 { 647 reg = <0x17 0x1>; 648 }; 649 logic_leakage: logic-leakage@18 { 650 reg = <0x18 0x1>; 651 }; 652 npu_leakage: npu-leakage@19 { 653 reg = <0x19 0x1>; 654 }; 655 efuse_cpu_version: cpu-version@1c { 656 reg = <0x1c 0x1>; 657 bits = <3 3>; 658 }; 659 }; 660 661 cru: clock-controller@ff350000 { 662 compatible = "rockchip,rk1808-cru"; 663 reg = <0x0 0xff350000 0x0 0x5000>; 664 rockchip,grf = <&grf>; 665 rockchip,pmugrf = <&pmugrf>; 666 #clock-cells = <1>; 667 #reset-cells = <1>; 668 669 assigned-clocks = 670 <&cru SCLK_32K_IOE>, 671 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 672 <&cru PLL_PPLL>, <&cru ARMCLK>, 673 <&cru MSCLK_PERI>, <&cru LSCLK_PERI>, 674 <&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>, 675 <&cru LSCLK_BUS_PRE>; 676 assigned-clock-parents = <&xin32k>; 677 assigned-clock-rates = 678 <32768>, 679 <1188000000>, <1000000000>, 680 <100000000>, <816000000>, 681 <200000000>, <100000000>, 682 <300000000>, <200000000>, 683 <100000000>; 684 }; 685 686 mipi_dphy_rx: mipi-dphy-rx@ff360000 { 687 compatible = "rockchip,rk1808-mipi-dphy-rx"; 688 reg = <0x0 0xff360000 0x0 0x4000>; 689 clocks = <&cru PCLK_MIPICSIPHY>; 690 clock-names = "pclk"; 691 power-domains = <&power RK1808_PD_VIO>; 692 rockchip,grf = <&grf>; 693 status = "disabled"; 694 }; 695 696 mipi_dphy: mipi-dphy@ff370000 { 697 compatible = "rockchip,rk1808-mipi-dphy"; 698 reg = <0x0 0xff370000 0x0 0x500>; 699 clocks = <&cru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 700 clock-names = "ref", "pclk"; 701 clock-output-names = "mipi_dphy_pll"; 702 #clock-cells = <0>; 703 resets = <&cru SRST_MIPIDSIPHY_P>; 704 reset-names = "apb"; 705 #phy-cells = <0>; 706 rockchip,grf = <&grf>; 707 status = "disabled"; 708 }; 709 710 combphy: phy@ff380000 { 711 compatible = "rockchip,rk1808-combphy"; 712 reg = <0x0 0xff380000 0x0 0x10000>; 713 #phy-cells = <1>; 714 clocks = <&cru SCLK_PCIEPHY_REF>; 715 clock-names = "refclk"; 716 assigned-clocks = <&cru SCLK_PCIEPHY_REF>; 717 assigned-clock-rates = <25000000>; 718 resets = <&cru SRST_USB3_OTG_A>, <&cru SRST_PCIEPHY_POR>, 719 <&cru SRST_PCIEPHY_P>, <&cru SRST_PCIEPHY_PIPE>, 720 <&cru SRST_USB3PHY_GRF_P>; 721 reset-names = "otg-rst", "combphy-por", 722 "combphy-apb", "combphy-pipe", 723 "usb3phy_grf_p"; 724 rockchip,combphygrf = <&combphy_grf>; 725 rockchip,usbpciegrf = <&usb_pcie_grf>; 726 status = "disabled"; 727 }; 728 729 thermal_zones: thermal-zones { 730 soc_thermal: soc-thermal { 731 polling-delay-passive = <20>; /* milliseconds */ 732 polling-delay = <1000>; /* milliseconds */ 733 sustainable-power = <977>; /* milliwatts */ 734 735 thermal-sensors = <&tsadc 0>; 736 737 trips { 738 threshold: trip-point-0 { 739 /* millicelsius */ 740 temperature = <75000>; 741 /* millicelsius */ 742 hysteresis = <2000>; 743 type = "passive"; 744 }; 745 target: trip-point-1 { 746 /* millicelsius */ 747 temperature = <85000>; 748 /* millicelsius */ 749 hysteresis = <2000>; 750 type = "passive"; 751 }; 752 soc_crit: soc-crit { 753 /* millicelsius */ 754 temperature = <115000>; 755 /* millicelsius */ 756 hysteresis = <2000>; 757 type = "critical"; 758 }; 759 }; 760 761 cooling-maps { 762 map0 { 763 trip = <&target>; 764 cooling-device = 765 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 766 contribution = <4096>; 767 }; 768 map1 { 769 trip = <&target>; 770 cooling-device = 771 <&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 772 contribution = <1024>; 773 }; 774 }; 775 }; 776 }; 777 778 tsadc: tsadc@ff3a0000 { 779 compatible = "rockchip,rk1808-tsadc"; 780 reg = <0x0 0xff3a0000 0x0 0x100>; 781 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 782 rockchip,grf = <&grf>; 783 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 784 clock-names = "tsadc", "apb_pclk"; 785 assigned-clocks = <&cru SCLK_TSADC>; 786 assigned-clock-rates = <650000>; 787 resets = <&cru SRST_TSADC>; 788 reset-names = "tsadc-apb"; 789 #thermal-sensor-cells = <1>; 790 rockchip,hw-tshut-temp = <120000>; 791 status = "disabled"; 792 }; 793 794 saradc: saradc@ff3c0000 { 795 compatible = "rockchip,rk1808-saradc", "rockchip,rk3399-saradc"; 796 reg = <0x0 0xff3c0000 0x0 0x100>; 797 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 798 #io-channel-cells = <1>; 799 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 800 clock-names = "saradc", "apb_pclk"; 801 resets = <&cru SRST_SARADC_P>; 802 reset-names = "saradc-apb"; 803 status = "disabled"; 804 }; 805 806 pwm0: pwm@ff3d0000 { 807 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 808 reg = <0x0 0xff3d0000 0x0 0x10>; 809 #pwm-cells = <3>; 810 pinctrl-names = "active"; 811 pinctrl-0 = <&pwm0_pin>; 812 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 813 clock-names = "pwm", "pclk"; 814 status = "disabled"; 815 }; 816 817 pwm1: pwm@ff3d0010 { 818 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 819 reg = <0x0 0xff3d0010 0x0 0x10>; 820 #pwm-cells = <3>; 821 pinctrl-names = "active"; 822 pinctrl-0 = <&pwm1_pin>; 823 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 824 clock-names = "pwm", "pclk"; 825 status = "disabled"; 826 }; 827 828 pwm2: pwm@ff3d0020 { 829 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 830 reg = <0x0 0xff3d0020 0x0 0x10>; 831 #pwm-cells = <3>; 832 pinctrl-names = "active"; 833 pinctrl-0 = <&pwm2_pin>; 834 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 835 clock-names = "pwm", "pclk"; 836 status = "disabled"; 837 }; 838 839 pwm3: pwm@ff3d0030 { 840 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 841 reg = <0x0 0xff3d0030 0x0 0x10>; 842 #pwm-cells = <3>; 843 pinctrl-names = "active"; 844 pinctrl-0 = <&pwm3_pin>; 845 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 846 clock-names = "pwm", "pclk"; 847 status = "disabled"; 848 }; 849 850 pwm4: pwm@ff3d8000 { 851 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 852 reg = <0x0 0xff3d8000 0x0 0x10>; 853 #pwm-cells = <3>; 854 pinctrl-names = "active"; 855 pinctrl-0 = <&pwm4_pin>; 856 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 857 clock-names = "pwm", "pclk"; 858 status = "disabled"; 859 }; 860 861 pwm5: pwm@ff3d8010 { 862 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 863 reg = <0x0 0xff3d8010 0x0 0x10>; 864 #pwm-cells = <3>; 865 pinctrl-names = "active"; 866 pinctrl-0 = <&pwm5_pin>; 867 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 868 clock-names = "pwm", "pclk"; 869 status = "disabled"; 870 }; 871 872 pwm6: pwm@ff3d8020 { 873 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 874 reg = <0x0 0xff3d8020 0x0 0x10>; 875 #pwm-cells = <3>; 876 pinctrl-names = "active"; 877 pinctrl-0 = <&pwm6_pin>; 878 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 879 clock-names = "pwm", "pclk"; 880 status = "disabled"; 881 }; 882 883 pwm7: pwm@ff3d8030 { 884 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 885 reg = <0x0 0xff3d8030 0x0 0x10>; 886 #pwm-cells = <3>; 887 pinctrl-names = "active"; 888 pinctrl-0 = <&pwm7_pin>; 889 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 890 clock-names = "pwm", "pclk"; 891 status = "disabled"; 892 }; 893 894 pmu: power-management@ff3e0000 { 895 compatible = "rockchip,rk1808-pmu", "syscon", "simple-mfd"; 896 reg = <0x0 0xff3e0000 0x0 0x1000>; 897 898 power: power-controller { 899 compatible = "rockchip,rk1808-power-controller"; 900 #power-domain-cells = <1>; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 status = "okay"; 904 905 /* These power domains are grouped by VD_NPU */ 906 pd_npu@RK1808_VD_NPU { 907 reg = <RK1808_VD_NPU>; 908 clocks = <&cru SCLK_NPU>, 909 <&cru ACLK_NPU>, 910 <&cru HCLK_NPU>; 911 pm_qos = <&qos_npu>; 912 }; 913 914 /* These power domains are grouped by VD_LOGIC */ 915 pd_pcie@RK1808_PD_PCIE { 916 reg = <RK1808_PD_PCIE>; 917 clocks = <&cru HSCLK_PCIE>, 918 <&cru LSCLK_PCIE>, 919 <&cru ACLK_PCIE>, 920 <&cru ACLK_PCIE_MST>, 921 <&cru ACLK_PCIE_SLV>, 922 <&cru PCLK_PCIE>, 923 <&cru SCLK_PCIE_AUX>, 924 <&cru SCLK_PCIE_AUX>, 925 <&cru ACLK_USB3OTG>, 926 <&cru HCLK_HOST>, 927 <&cru HCLK_HOST_ARB>, 928 <&cru SCLK_USB3_OTG0_REF>, 929 <&cru SCLK_USB3_OTG0_SUSPEND>; 930 pm_qos = <&qos_pcie>, 931 <&qos_usb2>, 932 <&qos_usb3>; 933 }; 934 pd_vpu@RK1808_PD_VPU { 935 reg = <RK1808_PD_VPU>; 936 clocks = <&cru ACLK_VPU>, 937 <&cru HCLK_VPU>; 938 pm_qos = <&qos_vpu>; 939 }; 940 pd_vio@RK1808_PD_VIO { 941 reg = <RK1808_PD_VIO>; 942 clocks = <&cru HSCLK_VIO>, 943 <&cru LSCLK_VIO>, 944 <&cru ACLK_VOPRAW>, 945 <&cru HCLK_VOPRAW>, 946 <&cru ACLK_VOPLITE>, 947 <&cru HCLK_VOPLITE>, 948 <&cru PCLK_DSI_TX>, 949 <&cru PCLK_CSI_TX>, 950 <&cru ACLK_RGA>, 951 <&cru HCLK_RGA>, 952 <&cru ACLK_ISP>, 953 <&cru HCLK_ISP>, 954 <&cru ACLK_CIF>, 955 <&cru HCLK_CIF>, 956 <&cru PCLK_CSI2HOST>, 957 <&cru DCLK_VOPRAW>, 958 <&cru DCLK_VOPLITE>; 959 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 960 <&qos_isp>, <&qos_cif>, 961 <&qos_vop_raw>, <&qos_vop_lite>; 962 }; 963 }; 964 }; 965 966 i2c0: i2c@ff410000 { 967 compatible = "rockchip,rk3399-i2c"; 968 reg = <0x0 0xff410000 0x0 0x1000>; 969 clocks = <&cru SCLK_PMU_I2C0>, <&cru PCLK_I2C0_PMU>; 970 clock-names = "i2c", "pclk"; 971 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 972 pinctrl-names = "default"; 973 pinctrl-0 = <&i2c0_xfer>; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 status = "disabled"; 977 }; 978 979 dmac: dmac@ff4e0000 { 980 compatible = "arm,pl330", "arm,primecell"; 981 reg = <0x0 0xff4e0000 0x0 0x4000>; 982 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&cru ACLK_DMAC>; 984 clock-names = "apb_pclk"; 985 #dma-cells = <1>; 986 arm,pl330-periph-burst; 987 }; 988 989 uart0: serial@ff430000 { 990 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 991 reg = <0x0 0xff430000 0x0 0x100>; 992 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 993 clocks = <&cru SCLK_UART0_PMU>, <&cru PCLK_UART0_PMU>; 994 clock-names = "baudclk", "apb_pclk"; 995 reg-shift = <2>; 996 reg-io-width = <4>; 997 dmas = <&dmac 0>, <&dmac 1>; 998 pinctrl-names = "default"; 999 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 1000 status = "disabled"; 1001 }; 1002 1003 i2c1: i2c@ff500000 { 1004 compatible = "rockchip,rk3399-i2c"; 1005 reg = <0x0 0xff500000 0x0 0x1000>; 1006 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 1007 clock-names = "i2c", "pclk"; 1008 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1009 pinctrl-names = "default"; 1010 pinctrl-0 = <&i2c1_xfer>; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 status = "disabled"; 1014 }; 1015 1016 i2c2: i2c@ff504000 { 1017 compatible = "rockchip,rk3399-i2c"; 1018 reg = <0x0 0xff504000 0x0 0x1000>; 1019 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 1020 clock-names = "i2c", "pclk"; 1021 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1022 pinctrl-names = "default"; 1023 pinctrl-0 = <&i2c2m0_xfer>; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 status = "disabled"; 1027 }; 1028 1029 i2c3: i2c@ff508000 { 1030 compatible = "rockchip,rk3399-i2c"; 1031 reg = <0x0 0xff508000 0x0 0x1000>; 1032 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 1033 clock-names = "i2c", "pclk"; 1034 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1035 pinctrl-names = "default"; 1036 pinctrl-0 = <&i2c3_xfer>; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 status = "disabled"; 1040 }; 1041 1042 i2c4: i2c@ff50c000 { 1043 compatible = "rockchip,rk3399-i2c"; 1044 reg = <0x0 0xff50c000 0x0 0x1000>; 1045 clocks = <&cru SCLK_I2C4>, <&cru PCLK_I2C4>; 1046 clock-names = "i2c", "pclk"; 1047 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1048 pinctrl-names = "default"; 1049 pinctrl-0 = <&i2c4_xfer>; 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 status = "disabled"; 1053 }; 1054 1055 i2c5: i2c@ff510000 { 1056 compatible = "rockchip,rk3399-i2c"; 1057 reg = <0x0 0xff510000 0x0 0x1000>; 1058 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 1059 clock-names = "i2c", "pclk"; 1060 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1061 pinctrl-names = "default"; 1062 pinctrl-0 = <&i2c5_xfer>; 1063 #address-cells = <1>; 1064 #size-cells = <0>; 1065 status = "disabled"; 1066 }; 1067 1068 spi0: spi@ff520000 { 1069 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; 1070 reg = <0x0 0xff520000 0x0 0x1000>; 1071 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 1075 clock-names = "spiclk", "apb_pclk"; 1076 dmas = <&dmac 10>, <&dmac 11>; 1077 pinctrl-names = "default", "high_speed"; 1078 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 1079 pinctrl-1 = <&spi0_clk_hs &spi0_csn &spi0_miso_hs &spi0_mosi_hs>; 1080 status = "disabled"; 1081 }; 1082 1083 spi1: spi@ff530000 { 1084 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; 1085 reg = <0x0 0xff530000 0x0 0x1000>; 1086 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 1090 clock-names = "spiclk", "apb_pclk"; 1091 dmas = <&dmac 12>, <&dmac 13>; 1092 pinctrl-names = "default", "high_speed"; 1093 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 1094 pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_csn1 &spi1_miso_hs &spi1_mosi_hs>; 1095 status = "disabled"; 1096 }; 1097 1098 uart1: serial@ff540000 { 1099 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 1100 reg = <0x0 0xff540000 0x0 0x100>; 1101 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1102 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1103 clock-names = "baudclk", "apb_pclk"; 1104 reg-shift = <2>; 1105 reg-io-width = <4>; 1106 dmas = <&dmac 2>, <&dmac 3>; 1107 pinctrl-names = "default"; 1108 pinctrl-0 = <&uart1m0_xfer &uart1_cts &uart1_rts>; 1109 status = "disabled"; 1110 }; 1111 1112 uart2: serial@ff550000 { 1113 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 1114 reg = <0x0 0xff550000 0x0 0x100>; 1115 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1116 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1117 clock-names = "baudclk", "apb_pclk"; 1118 reg-shift = <2>; 1119 reg-io-width = <4>; 1120 dmas = <&dmac 4>, <&dmac 5>; 1121 pinctrl-names = "default"; 1122 pinctrl-0 = <&uart2m0_xfer>; 1123 status = "disabled"; 1124 }; 1125 1126 uart3: serial@ff560000 { 1127 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 1128 reg = <0x0 0xff560000 0x0 0x100>; 1129 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1130 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1131 clock-names = "baudclk", "apb_pclk"; 1132 reg-shift = <2>; 1133 reg-io-width = <4>; 1134 dmas = <&dmac 6>, <&dmac 7>; 1135 pinctrl-names = "default"; 1136 pinctrl-0 = <&uart3m0_xfer &uart3_ctsm0 &uart3_rtsm0>; 1137 status = "disabled"; 1138 }; 1139 1140 uart4: serial@ff570000 { 1141 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 1142 reg = <0x0 0xff570000 0x0 0x100>; 1143 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1144 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1145 clock-names = "baudclk", "apb_pclk"; 1146 reg-shift = <2>; 1147 reg-io-width = <4>; 1148 dmas = <&dmac 8>, <&dmac 9>; 1149 pinctrl-names = "default"; 1150 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 1151 status = "disabled"; 1152 }; 1153 1154 spi2: spi@ff580000 { 1155 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; 1156 reg = <0x0 0xff580000 0x0 0x1000>; 1157 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 1161 clock-names = "spiclk", "apb_pclk"; 1162 dmas = <&dmac 14>, <&dmac 15>; 1163 pinctrl-names = "default", "high_speed"; 1164 pinctrl-0 = <&spi2m0_clk &spi2m0_csn &spi2m0_miso &spi2m0_mosi>; 1165 pinctrl-1 = <&spi2m0_clk_hs &spi2m0_csn &spi2m0_miso_hs &spi2m0_mosi_hs>; 1166 status = "disabled"; 1167 }; 1168 1169 uart5: serial@ff5a0000 { 1170 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 1171 reg = <0x0 0xff5a0000 0x0 0x100>; 1172 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1173 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1174 clock-names = "baudclk", "apb_pclk"; 1175 reg-shift = <2>; 1176 reg-io-width = <4>; 1177 dmas = <&dmac 25>, <&dmac 26>; 1178 pinctrl-names = "default"; 1179 pinctrl-0 = <&uart5_xfer>; 1180 status = "disabled"; 1181 }; 1182 1183 uart6: serial@ff5b0000 { 1184 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 1185 reg = <0x0 0xff5b0000 0x0 0x100>; 1186 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1187 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1188 clock-names = "baudclk", "apb_pclk"; 1189 reg-shift = <2>; 1190 reg-io-width = <4>; 1191 dmas = <&dmac 27>, <&dmac 28>; 1192 pinctrl-names = "default"; 1193 pinctrl-0 = <&uart6_xfer>; 1194 status = "disabled"; 1195 }; 1196 1197 uart7: serial@ff5c0000 { 1198 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 1199 reg = <0x0 0xff5c0000 0x0 0x100>; 1200 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1201 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1202 clock-names = "baudclk", "apb_pclk"; 1203 reg-shift = <2>; 1204 reg-io-width = <4>; 1205 dmas = <&dmac 29>, <&dmac 30>; 1206 pinctrl-names = "default"; 1207 pinctrl-0 = <&uart7_xfer>; 1208 status = "disabled"; 1209 }; 1210 1211 pwm8: pwm@ff5d0000 { 1212 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 1213 reg = <0x0 0xff5d0000 0x0 0x10>; 1214 #pwm-cells = <3>; 1215 pinctrl-names = "active"; 1216 pinctrl-0 = <&pwm8_pin>; 1217 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 1218 clock-names = "pwm", "pclk"; 1219 status = "disabled"; 1220 }; 1221 1222 pwm9: pwm@fff5d0010 { 1223 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 1224 reg = <0x0 0xff5d0010 0x0 0x10>; 1225 #pwm-cells = <3>; 1226 pinctrl-names = "active"; 1227 pinctrl-0 = <&pwm9_pin>; 1228 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 1229 clock-names = "pwm", "pclk"; 1230 status = "disabled"; 1231 }; 1232 1233 pwm10: pwm@ff5d0020 { 1234 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 1235 reg = <0x0 0xff5d0020 0x0 0x10>; 1236 #pwm-cells = <3>; 1237 pinctrl-names = "active"; 1238 pinctrl-0 = <&pwm10_pin>; 1239 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 1240 clock-names = "pwm", "pclk"; 1241 status = "disabled"; 1242 }; 1243 1244 pwm11: pwm@ff5d0030 { 1245 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 1246 reg = <0x0 0xff5d0030 0x0 0x10>; 1247 #pwm-cells = <3>; 1248 pinctrl-names = "active"; 1249 pinctrl-0 = <&pwm11_pin>; 1250 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 1251 clock-names = "pwm", "pclk"; 1252 status = "disabled"; 1253 }; 1254 1255 rng: rng@ff630000 { 1256 compatible = "rockchip,cryptov2-rng"; 1257 reg = <0x0 0xff630000 0x0 0x4000>; 1258 clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>, 1259 <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>; 1260 clock-names = "clk_crypto", "clk_crypto_apk", 1261 "aclk_crypto", "hclk_crypto"; 1262 resets = <&cru SRST_CRYPTO_CORE>; 1263 reset-names = "reset"; 1264 status = "disabled"; 1265 }; 1266 1267 dcf: dcf@ff640000 { 1268 compatible = "syscon"; 1269 reg = <0x0 0xff640000 0x0 0x1000>; 1270 }; 1271 1272 rktimer: rktimer@ff700000 { 1273 compatible = "rockchip,rk3288-timer"; 1274 reg = <0x0 0xff700000 0x0 0x1000>; 1275 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1276 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 1277 clock-names = "pclk", "timer"; 1278 }; 1279 1280 wdt: watchdog@ff720000 { 1281 compatible = "snps,dw-wdt"; 1282 reg = <0x0 0xff720000 0x0 0x100>; 1283 clocks = <&cru PCLK_WDT>; 1284 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1285 status = "okay"; 1286 }; 1287 1288 i2s0: i2s@ff7e0000 { 1289 compatible = "rockchip,rk1808-i2s-tdm"; 1290 reg = <0x0 0xff7e0000 0x0 0x1000>; 1291 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1292 clocks = <&cru SCLK_I2S0_8CH_TX>, <&cru SCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1293 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1294 dmas = <&dmac 16>, <&dmac 17>; 1295 dma-names = "tx", "rx"; 1296 resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>; 1297 reset-names = "tx-m", "rx-m"; 1298 rockchip,cru = <&cru>; 1299 rockchip,grf = <&grf>; 1300 pinctrl-names = "default"; 1301 pinctrl-0 = <&i2s0_8ch_sclktx 1302 &i2s0_8ch_sclkrx 1303 &i2s0_8ch_lrcktx 1304 &i2s0_8ch_lrckrx 1305 &i2s0_8ch_sdi0 1306 &i2s0_8ch_sdi1 1307 &i2s0_8ch_sdi2 1308 &i2s0_8ch_sdi3 1309 &i2s0_8ch_sdo0 1310 &i2s0_8ch_sdo1 1311 &i2s0_8ch_sdo2 1312 &i2s0_8ch_sdo3 1313 &i2s0_8ch_mclk>; 1314 status = "disabled"; 1315 }; 1316 1317 i2s1: i2s@ff7f0000 { 1318 compatible = "rockchip,rk1808-i2s", "rockchip,rk3066-i2s"; 1319 reg = <0x0 0xff7f0000 0x0 0x1000>; 1320 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1321 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; 1322 clock-names = "i2s_clk", "i2s_hclk"; 1323 dmas = <&dmac 18>, <&dmac 19>; 1324 dma-names = "tx", "rx"; 1325 resets = <&cru SRST_I2S1>, <&cru SRST_I2S1_H>; 1326 reset-names = "reset-m", "reset-h"; 1327 pinctrl-names = "default"; 1328 pinctrl-0 = <&i2s1_2ch_sclk 1329 &i2s1_2ch_lrck 1330 &i2s1_2ch_sdi 1331 &i2s1_2ch_sdo>; 1332 status = "disabled"; 1333 }; 1334 1335 pdm: pdm@ff800000 { 1336 compatible = "rockchip,rk1808-pdm", "rockchip,pdm"; 1337 reg = <0x0 0xff800000 0x0 0x1000>; 1338 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 1339 clock-names = "pdm_clk", "pdm_hclk"; 1340 dmas = <&dmac 24>; 1341 dma-names = "rx"; 1342 resets = <&cru SRST_PDM>; 1343 reset-names = "pdm-m"; 1344 pinctrl-names = "default"; 1345 pinctrl-0 = <&pdm_clk 1346 &pdm_clk1 1347 &pdm_sdi0 1348 &pdm_sdi1 1349 &pdm_sdi2 1350 &pdm_sdi3>; 1351 status = "disabled"; 1352 }; 1353 1354 vad: vad@ff810000 { 1355 compatible = "rockchip,rk1808-vad"; 1356 reg = <0x0 0xff810000 0x0 0x10000>; 1357 reg-names = "vad"; 1358 clocks = <&cru HCLK_VAD>; 1359 clock-names = "hclk"; 1360 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1361 rockchip,audio-sram = <&vad_sram>; 1362 rockchip,audio-src = <0>; 1363 rockchip,det-channel = <0>; 1364 rockchip,mode = <1>; 1365 status = "disabled"; 1366 }; 1367 1368 dfi: dfi@ff9c0000 { 1369 reg = <0x00 0xff9c0000 0x00 0x400>; 1370 compatible = "rockchip,rk1808-dfi"; 1371 rockchip,pmugrf = <&pmugrf>; 1372 status = "disabled"; 1373 }; 1374 1375 dmc: dmc { 1376 compatible = "rockchip,rk1808-dmc"; 1377 dcf_reg = <&dcf>; 1378 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1379 interrupt-names = "complete_irq"; 1380 devfreq-events = <&dfi>; 1381 clocks = <&cru SCLK_DDRCLK>; 1382 clock-names = "dmc_clk"; 1383 operating-points-v2 = <&dmc_opp_table>; 1384 ddr_timing = <&ddr_timing>; 1385 upthreshold = <40>; 1386 downdifferential = <20>; 1387 system-status-freq = < 1388 /*system status freq(KHz)*/ 1389 SYS_STATUS_NORMAL 924000 1390 SYS_STATUS_REBOOT 450000 1391 SYS_STATUS_SUSPEND 328000 1392 SYS_STATUS_VIDEO_1080P 924000 1393 SYS_STATUS_BOOST 924000 1394 SYS_STATUS_ISP 924000 1395 SYS_STATUS_PERFORMANCE 924000 1396 >; 1397 auto-min-freq = <328000>; 1398 auto-freq-en = <0>; 1399 #cooling-cells = <2>; 1400 status = "disabled"; 1401 }; 1402 1403 dmc_opp_table: dmc-opp-table { 1404 compatible = "operating-points-v2"; 1405 1406 rockchip,max-volt = <950000>; 1407 rockchip,evb-irdrop = <12500>; 1408 nvmem-cells = <&logic_leakage>; 1409 nvmem-cell-names = "leakage"; 1410 rockchip,temp-hysteresis = <5000>; 1411 rockchip,low-temp = <0>; 1412 rockchip,low-temp-min-volt = <800000>; 1413 1414 opp-192000000 { 1415 opp-hz = /bits/ 64 <192000000>; 1416 opp-microvolt = <800000>; 1417 }; 1418 opp-324000000 { 1419 opp-hz = /bits/ 64 <324000000>; 1420 opp-microvolt = <800000>; 1421 }; 1422 opp-450000000 { 1423 opp-hz = /bits/ 64 <450000000>; 1424 opp-microvolt = <800000>; 1425 }; 1426 opp-528000000 { 1427 opp-hz = /bits/ 64 <528000000>; 1428 opp-microvolt = <800000>; 1429 }; 1430 opp-664000000 { 1431 opp-hz = /bits/ 64 <664000000>; 1432 opp-microvolt = <800000>; 1433 }; 1434 opp-784000000 { 1435 opp-hz = /bits/ 64 <784000000>; 1436 opp-microvolt = <800000>; 1437 }; 1438 opp-924000000 { 1439 opp-hz = /bits/ 64 <924000000>; 1440 opp-microvolt = <800000>; 1441 }; 1442 /* 1066M is only for ddr4 */ 1443 opp-1066000000 { 1444 opp-hz = /bits/ 64 <1066000000>; 1445 opp-microvolt = <800000>; 1446 status = "disabled"; 1447 }; 1448 }; 1449 1450 rk_rga: rk_rga@ffaf0000 { 1451 compatible = "rockchip,rga2"; 1452 dev_mode = <0>; 1453 reg = <0x0 0xffaf0000 0x0 0x1000>; 1454 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1455 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; 1456 clock-names = "aclk_rga", "hclk_rga", "clk_rga"; 1457 power-domains = <&power RK1808_PD_VIO>; 1458 status = "disabled"; 1459 }; 1460 1461 cif: cif@ffae0000 { 1462 compatible = "rockchip,rk1808-cif"; 1463 reg = <0x0 0xffae0000 0x0 0x200>; 1464 reg-names = "cif_regs"; 1465 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1466 interrupt-names = "cif-intr"; 1467 clocks = <&cru ACLK_CIF>, <&cru DCLK_CIF>, 1468 <&cru HCLK_CIF>, <&cru SCLK_CIF_OUT>; 1469 clock-names = "aclk_cif", "dclk_cif", 1470 "hclk_cif", "sclk_cif_out"; 1471 resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, 1472 <&cru SRST_CIF_I>, <&cru SRST_CIF_D>, 1473 <&cru SRST_CIF_PCLKIN>; 1474 reset-names = "rst_cif_a", "rst_cif_h", 1475 "rst_cif_i", "rst_cif_d", 1476 "rst_cif_pclkin"; 1477 power-domains = <&power RK1808_PD_VIO>; 1478 iommus = <&cif_mmu>; 1479 status = "disabled"; 1480 }; 1481 1482 cif_mmu: iommu@ffae0800 { 1483 compatible = "rockchip,iommu"; 1484 reg = <0x0 0xffae0800 0x0 0x100>; 1485 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1486 interrupt-names = "cif_mmu"; 1487 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>; 1488 clock-names = "aclk", "iface"; 1489 power-domains = <&power RK1808_PD_VIO>; 1490 #iommu-cells = <0>; 1491 status = "disabled"; 1492 }; 1493 1494 vop_lite: vop@ffb00000 { 1495 compatible = "rockchip,rk1808-vop-lit"; 1496 reg = <0x0 0xffb00000 0x0 0x200>; 1497 reg-names = "regs"; 1498 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1499 clocks = <&cru ACLK_VOPLITE>, <&cru DCLK_VOPLITE>, 1500 <&cru HCLK_VOPLITE>; 1501 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1502 power-domains = <&power RK1808_PD_VIO>; 1503 iommus = <&vopl_mmu>; 1504 status = "disabled"; 1505 1506 vop_lite_out: port { 1507 #address-cells = <1>; 1508 #size-cells = <0>; 1509 1510 vop_lite_out_dsi: endpoint@0 { 1511 reg = <0>; 1512 remote-endpoint = <&dsi_in_vop_lite>; 1513 }; 1514 1515 vop_lite_out_rgb: endpoint@1 { 1516 reg = <1>; 1517 remote-endpoint = <&rgb_in_vop_lite>; 1518 }; 1519 }; 1520 }; 1521 1522 vopl_mmu: iommu@ffb00f00 { 1523 compatible = "rockchip,iommu"; 1524 reg = <0x0 0xffb00f00 0x0 0x100>; 1525 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1526 interrupt-names = "vopl_mmu"; 1527 clocks = <&cru ACLK_VOPLITE>, <&cru HCLK_VOPLITE>; 1528 clock-names = "aclk", "iface"; 1529 power-domains = <&power RK1808_PD_VIO>; 1530 #iommu-cells = <0>; 1531 status = "disabled"; 1532 }; 1533 1534 mipi_csi2_hw: mipi-csi2-hw@ffb10000 { 1535 compatible = "rockchip,rk1808-mipi-csi2-hw"; 1536 reg = <0x0 0xffb10000 0x0 0x100>; 1537 reg-names = "csihost_regs"; 1538 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1540 interrupt-names = "csi-intr1", "csi-intr2"; 1541 clocks = <&cru PCLK_CSI2HOST>; 1542 clock-names = "pclk_csi2host"; 1543 status = "disabled"; 1544 }; 1545 1546 csi_tx: csi@ffb20000 { 1547 compatible = "rockchip,rk1808-mipi-csi"; 1548 reg = <0x0 0xffb20000 0x0 0x500>; 1549 reg-names = "csi_regs"; 1550 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1551 clocks = <&cru PCLK_CSI_TX>, <&mipi_dphy>; 1552 clock-names = "pclk", "hs_clk"; 1553 resets = <&cru SRST_CSITX_P>, 1554 <&cru SRST_CSITX_TXBYTEHS>, 1555 <&cru SRST_CSITX_TXESC>, 1556 <&cru SRST_CSITX_CAM>, 1557 <&cru SRST_CSITX_I>; 1558 reset-names = "tx_apb", "tx_bytehs", "tx_esc", "tx_cam", "tx_i"; 1559 phys = <&mipi_dphy>; 1560 phy-names = "mipi_dphy"; 1561 power-domains = <&power RK1808_PD_VIO>; 1562 rockchip,grf = <&grf>; 1563 #address-cells = <1>; 1564 #size-cells = <0>; 1565 status = "disabled"; 1566 1567 ports { 1568 1569 port { 1570 csi_in_vop_raw: endpoint { 1571 remote-endpoint = <&vop_raw_out_csi>; 1572 }; 1573 }; 1574 }; 1575 }; 1576 1577 dsi: dsi@ffb30000 { 1578 compatible = "rockchip,rk1808-mipi-dsi"; 1579 reg = <0x0 0xffb30000 0x0 0x500>; 1580 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1581 clocks = <&cru PCLK_DSI_TX>, <&mipi_dphy>; 1582 clock-names = "pclk", "hs_clk"; 1583 resets = <&cru SRST_MIPIDSI_HOST_P>; 1584 reset-names = "apb"; 1585 phys = <&mipi_dphy>; 1586 phy-names = "mipi_dphy"; 1587 power-domains = <&power RK1808_PD_VIO>; 1588 rockchip,grf = <&grf>; 1589 #address-cells = <1>; 1590 #size-cells = <0>; 1591 status = "disabled"; 1592 1593 ports { 1594 port { 1595 dsi_in_vop_lite: endpoint { 1596 remote-endpoint = <&vop_lite_out_dsi>; 1597 }; 1598 }; 1599 }; 1600 }; 1601 1602 vop_raw: vop@ffb40000 { 1603 compatible = "rockchip,rk1808-vop-raw"; 1604 reg = <0x0 0xffb40000 0x0 0x500>; 1605 reg-names = "regs"; 1606 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1607 clocks = <&cru ACLK_VOPRAW>, <&cru DCLK_VOPRAW>, 1608 <&cru HCLK_VOPRAW>; 1609 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1610 power-domains = <&power RK1808_PD_VIO>; 1611 iommus = <&vopr_mmu>; 1612 status = "disabled"; 1613 1614 vop_raw_out: port { 1615 #address-cells = <1>; 1616 #size-cells = <0>; 1617 1618 vop_raw_out_csi: endpoint@0 { 1619 reg = <0>; 1620 remote-endpoint = <&csi_in_vop_raw>; 1621 }; 1622 }; 1623 }; 1624 1625 vopr_mmu: iommu@ffb40f00 { 1626 compatible = "rockchip,iommu"; 1627 reg = <0x0 0xffb40f00 0x0 0x100>; 1628 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1629 interrupt-names = "vopr_mmu"; 1630 clocks = <&cru ACLK_VOPRAW>, <&cru HCLK_VOPRAW>; 1631 clock-names = "aclk", "iface"; 1632 power-domains = <&power RK1808_PD_VIO>; 1633 #iommu-cells = <0>; 1634 status = "disabled"; 1635 }; 1636 1637 rkisp1: rkisp1@ffb50000 { 1638 compatible = "rockchip,rk1808-rkisp1"; 1639 reg = <0x0 0xffb50000 0x0 0x8000>; 1640 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1643 interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; 1644 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, 1645 <&cru SCLK_ISP>, <&cru DCLK_CIF>; 1646 clock-names = "aclk_isp", "hclk_isp", 1647 "clk_isp", "pclk_isp"; 1648 power-domains = <&power RK1808_PD_VIO>; 1649 iommus = <&isp_mmu>; 1650 rockchip,grf = <&grf>; 1651 status = "disabled"; 1652 }; 1653 1654 isp_mmu: iommu@ffb58000 { 1655 compatible = "rockchip,iommu"; 1656 reg = <0x0 0xffb58000 0x0 0x100>; 1657 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1658 interrupt-names = "isp_mmu"; 1659 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, 1660 <&cru SCLK_ISP>; 1661 clock-names = "aclk", "iface", "sclk"; 1662 power-domains = <&power RK1808_PD_VIO>; 1663 rk_iommu,disable_reset_quirk; 1664 #iommu-cells = <0>; 1665 status = "disabled"; 1666 }; 1667 1668 vpu_service: vpu_service@ffb80000 { 1669 compatible = "rockchip,vpu_service"; 1670 reg = <0x0 0xffb80000 0x0 0x800>; 1671 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1673 interrupt-names = "irq_enc", "irq_dec"; 1674 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1675 clock-names = "aclk_vcodec", "hclk_vcodec"; 1676 power-domains = <&power RK1808_PD_VPU>; 1677 resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>; 1678 reset-names = "video_a", "video_h"; 1679 iommus = <&vpu_mmu>; 1680 iommu_enabled = <1>; 1681 allocator = <1>; /* 0 means ion, 1 means drm */ 1682 status = "disabled"; 1683 }; 1684 1685 vpu_mmu: iommu@ffb80800 { 1686 compatible = "rockchip,iommu"; 1687 reg = <0x0 0xffb80800 0x0 0x100>; 1688 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1689 interrupt-names = "vpu_mmu"; 1690 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1691 clock-names = "aclk", "iface"; 1692 power-domains = <&power RK1808_PD_VPU>; 1693 #iommu-cells = <0>; 1694 status = "disabled"; 1695 }; 1696 1697 sdio: dwmmc@ffc60000 { 1698 compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; 1699 reg = <0x0 0xffc60000 0x0 0x4000>; 1700 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 1701 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1702 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 1703 max-frequency = <150000000>; 1704 fifo-depth = <0x100>; 1705 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1706 pinctrl-names = "default"; 1707 pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; 1708 status = "disabled"; 1709 }; 1710 1711 npu: npu@ffbc0000 { 1712 compatible = "rockchip,npu"; 1713 reg = <0x0 0xffbc0000 0x0 0x1000>; 1714 clocks = <&cru SCLK_NPU>, <&cru ACLK_NPU>, <&cru HCLK_NPU>; 1715 clock-names = "sclk_npu", "aclk_npu", "hclk_npu"; 1716 assigned-clocks = <&cru SCLK_NPU>; 1717 assigned-clock-rates = <800000000>; 1718 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1719 power-domains = <&power RK1808_VD_NPU>; 1720 operating-points-v2 = <&npu_opp_table>; 1721 #cooling-cells = <2>; 1722 status = "disabled"; 1723 1724 npu_power_model: power-model { 1725 compatible = "simple-power-model"; 1726 ref-leakage = <31>; 1727 static-coefficient = <100000>; 1728 dynamic-coefficient = <3080>; 1729 ts = <88610 303120 (-5000) 100>; 1730 thermal-zone = "soc-thermal"; 1731 }; 1732 }; 1733 1734 npu_opp_table: npu-opp-table { 1735 compatible = "operating-points-v2"; 1736 1737 rockchip,thermal-zone = "soc-thermal"; 1738 rockchip,temp-hysteresis = <5000>; 1739 rockchip,low-temp = <0>; 1740 rockchip,low-temp-min-volt = <800000>; 1741 rockchip,low-temp-adjust-volt = < 1742 /* MHz MHz uV */ 1743 0 792 50000 1744 >; 1745 1746 rockchip,max-volt = <880000>; 1747 rockchip,evb-irdrop = <37500>; 1748 nvmem-cells = <&npu_leakage>; 1749 nvmem-cell-names = "leakage"; 1750 1751 rockchip,pvtm-voltage-sel = < 1752 0 69000 0 1753 69001 74000 1 1754 74001 99999 2 1755 >; 1756 rockchip,pvtm-ch = <0 0>; 1757 1758 opp-200000000 { 1759 opp-hz = /bits/ 64 <200000000>; 1760 opp-microvolt = <750000 750000 880000>; 1761 }; 1762 opp-297000000 { 1763 opp-hz = /bits/ 64 <297000000>; 1764 opp-microvolt = <750000 750000 880000>; 1765 }; 1766 opp-400000000 { 1767 opp-hz = /bits/ 64 <400000000>; 1768 opp-microvolt = <750000 750000 880000>; 1769 }; 1770 opp-594000000 { 1771 opp-hz = /bits/ 64 <594000000>; 1772 opp-microvolt = <750000 750000 880000>; 1773 }; 1774 opp-792000000 { 1775 opp-hz = /bits/ 64 <792000000>; 1776 opp-microvolt = <850000 850000 880000>; 1777 opp-microvolt-L0 = <850000 850000 880000>; 1778 opp-microvolt-L1 = <825000 825000 880000>; 1779 opp-microvolt-L2 = <800000 800000 880000>; 1780 }; 1781 }; 1782 1783 sfc: sfc@ffc50000 { 1784 compatible = "rockchip,sfc"; 1785 reg = <0x0 0xffc50000 0x0 0x4000>; 1786 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1787 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1788 clock-names = "clk_sfc", "hclk_sfc"; 1789 assigned-clocks = <&cru SCLK_SFC>; 1790 assigned-clock-rates = <100000000>; 1791 status = "disabled"; 1792 }; 1793 1794 sdmmc: dwmmc@ffcf0000 { 1795 compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; 1796 reg = <0x0 0xffcf0000 0x0 0x4000>; 1797 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 1798 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1799 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 1800 max-frequency = <150000000>; 1801 fifo-depth = <0x100>; 1802 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1803 pinctrl-names = "default"; 1804 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_detn>; 1805 status = "disabled"; 1806 }; 1807 1808 emmc: dwmmc@ffd00000 { 1809 compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; 1810 reg = <0x0 0xffd00000 0x0 0x4000>; 1811 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 1812 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 1813 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 1814 max-frequency = <150000000>; 1815 fifo-depth = <0x100>; 1816 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1817 pinctrl-names = "default"; 1818 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 1819 status = "disabled"; 1820 }; 1821 1822 usb_host0_ehci: usb@ffd80000 { 1823 compatible = "generic-ehci"; 1824 reg = <0x0 0xffd80000 0x0 0x10000>; 1825 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1826 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 1827 <&u2phy>; 1828 clock-names = "usbhost", "arbiter", "utmi"; 1829 phys = <&u2phy_host>; 1830 phy-names = "usb"; 1831 status = "disabled"; 1832 power-domains = <&power RK1808_PD_PCIE>; 1833 }; 1834 1835 usb_host0_ohci: usb@ffd90000 { 1836 compatible = "generic-ohci"; 1837 reg = <0x0 0xffd90000 0x0 0x10000>; 1838 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1839 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 1840 <&u2phy>; 1841 clock-names = "usbhost", "arbiter", "utmi"; 1842 phys = <&u2phy_host>; 1843 phy-names = "usb"; 1844 status = "disabled"; 1845 power-domains = <&power RK1808_PD_PCIE>; 1846 }; 1847 1848 gmac: ethernet@ffdd0000 { 1849 compatible = "rockchip,rk1808-gmac"; 1850 reg = <0x0 0xffdd0000 0x0 0x10000>; 1851 rockchip,grf = <&grf>; 1852 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1853 interrupt-names = "macirq"; 1854 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 1855 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_GMAC_REF>, 1856 <&cru SCLK_GMAC_REFOUT>, <&cru ACLK_GMAC>, 1857 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RGMII_SPEED>; 1858 clock-names = "stmmaceth", "mac_clk_rx", 1859 "mac_clk_tx", "clk_mac_ref", 1860 "clk_mac_refout", "aclk_mac", 1861 "pclk_mac", "clk_mac_speed"; 1862 phy-mode = "rgmii"; 1863 pinctrl-names = "default"; 1864 pinctrl-0 = <&rgmii_pins>; 1865 resets = <&cru SRST_GAMC_A>; 1866 reset-names = "stmmaceth"; 1867 /* power-domains = <&power RK1808_PD_GMAC>; */ 1868 status = "disabled"; 1869 }; 1870 1871 rockchip_system_monitor: rockchip-system-monitor { 1872 compatible = "rockchip,system-monitor"; 1873 1874 rockchip,thermal-zone = "soc-thermal"; 1875 rockchip,polling-delay = <200>; /* milliseconds */ 1876 }; 1877 1878 pinctrl: pinctrl { 1879 compatible = "rockchip,rk1808-pinctrl"; 1880 rockchip,grf = <&grf>; 1881 rockchip,pmu = <&pmugrf>; 1882 #address-cells = <2>; 1883 #size-cells = <2>; 1884 ranges; 1885 1886 gpio0: gpio0@ff4c0000 { 1887 compatible = "rockchip,gpio-bank"; 1888 reg = <0x0 0xff4c0000 0x0 0x100>; 1889 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1890 clocks = <&cru PCLK_GPIO0_PMU>, <&cru DBCLK_PMU_GPIO0>; 1891 gpio-controller; 1892 #gpio-cells = <2>; 1893 1894 interrupt-controller; 1895 #interrupt-cells = <2>; 1896 }; 1897 1898 gpio1: gpio1@ff690000 { 1899 compatible = "rockchip,gpio-bank"; 1900 reg = <0x0 0xff690000 0x0 0x100>; 1901 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1902 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1903 gpio-controller; 1904 #gpio-cells = <2>; 1905 1906 interrupt-controller; 1907 #interrupt-cells = <2>; 1908 }; 1909 1910 gpio2: gpio2@ff6a0000 { 1911 compatible = "rockchip,gpio-bank"; 1912 reg = <0x0 0xff6a0000 0x0 0x100>; 1913 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1914 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1915 gpio-controller; 1916 #gpio-cells = <2>; 1917 1918 interrupt-controller; 1919 #interrupt-cells = <2>; 1920 }; 1921 1922 gpio3: gpio3@ff6b0000 { 1923 compatible = "rockchip,gpio-bank"; 1924 reg = <0x0 0xff6b0000 0x0 0x100>; 1925 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1926 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1927 gpio-controller; 1928 #gpio-cells = <2>; 1929 1930 interrupt-controller; 1931 #interrupt-cells = <2>; 1932 }; 1933 1934 gpio4: gpio4@ff6c0000 { 1935 compatible = "rockchip,gpio-bank"; 1936 reg = <0x0 0xff6c0000 0x0 0x100>; 1937 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1938 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1939 gpio-controller; 1940 #gpio-cells = <2>; 1941 1942 interrupt-controller; 1943 #interrupt-cells = <2>; 1944 }; 1945 1946 pcfg_pull_up: pcfg-pull-up { 1947 bias-pull-up; 1948 }; 1949 1950 pcfg_pull_down: pcfg-pull-down { 1951 bias-pull-down; 1952 }; 1953 1954 pcfg_pull_none: pcfg-pull-none { 1955 bias-disable; 1956 }; 1957 1958 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1959 bias-disable; 1960 drive-strength = <2>; 1961 }; 1962 1963 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1964 bias-pull-up; 1965 drive-strength = <2>; 1966 }; 1967 1968 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1969 bias-pull-up; 1970 drive-strength = <4>; 1971 }; 1972 1973 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1974 bias-disable; 1975 drive-strength = <4>; 1976 }; 1977 1978 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1979 bias-pull-down; 1980 drive-strength = <4>; 1981 }; 1982 1983 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1984 bias-disable; 1985 drive-strength = <8>; 1986 }; 1987 1988 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1989 bias-pull-up; 1990 drive-strength = <8>; 1991 }; 1992 1993 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1994 bias-disable; 1995 drive-strength = <12>; 1996 }; 1997 1998 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1999 bias-pull-up; 2000 drive-strength = <12>; 2001 }; 2002 2003 pcfg_pull_none_smt: pcfg-pull-none-smt { 2004 bias-disable; 2005 input-schmitt-enable; 2006 }; 2007 2008 pcfg_pull_none_2ma_smt: pcfg-pull-none-2ma-smt { 2009 bias-disable; 2010 drive-strength = <2>; 2011 input-schmitt-enable; 2012 }; 2013 2014 pcfg_output_high: pcfg-output-high { 2015 output-high; 2016 }; 2017 2018 pcfg_output_low: pcfg-output-low { 2019 output-low; 2020 }; 2021 2022 pcfg_input_high: pcfg-input-high { 2023 bias-pull-up; 2024 input-enable; 2025 }; 2026 2027 pcfg_input: pcfg-input { 2028 input-enable; 2029 }; 2030 2031 pcfg_input_smt: pcfg-input-smt { 2032 input-enable; 2033 input-schmitt-enable; 2034 }; 2035 2036 cif-m0 { 2037 cif_clkout_m0: cif-clkout-m0 { 2038 rockchip,pins = 2039 <2 RK_PB7 1 &pcfg_pull_none>; 2040 }; 2041 2042 cif_d12d15_m0: cif-d12d15-m0 { 2043 rockchip,pins = 2044 <2 RK_PA0 1 &pcfg_pull_none>,/* cif_d12 */ 2045 <2 RK_PA1 1 &pcfg_pull_none>,/* cif_d13 */ 2046 <2 RK_PA2 1 &pcfg_pull_none>,/* cif_d14 */ 2047 <2 RK_PA3 1 &pcfg_pull_none>;/* cif_d15 */ 2048 }; 2049 2050 cif_d10d11_m0: cif-d10d11-m0 { 2051 rockchip,pins = 2052 <2 RK_PC2 1 &pcfg_pull_none>,/* cif_d10 */ 2053 <2 RK_PC3 1 &pcfg_pull_none>;/* cif_d11 */ 2054 }; 2055 2056 cif_d2d9_m0: cif-d2d9-m0 { 2057 rockchip,pins = 2058 <2 RK_PA4 1 &pcfg_pull_none>,/* cif_d2 */ 2059 <2 RK_PA5 1 &pcfg_pull_none>,/* cif_d3 */ 2060 <2 RK_PA6 1 &pcfg_pull_none>,/* cif_d4 */ 2061 <2 RK_PA7 1 &pcfg_pull_none>,/* cif_d5 */ 2062 <2 RK_PB0 1 &pcfg_pull_none>,/* cif_d6 */ 2063 <2 RK_PB1 1 &pcfg_pull_none>,/* cif_d7 */ 2064 <2 RK_PB2 1 &pcfg_pull_none>,/* cif_d8 */ 2065 <2 RK_PB3 1 &pcfg_pull_none>,/* cif_d9 */ 2066 <2 RK_PB4 1 &pcfg_pull_none>,/* cif_vsync */ 2067 <2 RK_PB5 1 &pcfg_pull_none>,/* cif_href */ 2068 <2 RK_PB6 1 &pcfg_pull_none>;/* cif_clkin */ 2069 }; 2070 2071 cif_d0d1_m0: cif-d0d1-m0 { 2072 rockchip,pins = 2073 <2 RK_PC0 1 &pcfg_pull_none>,/* cif_d0 */ 2074 <2 RK_PC1 1 &pcfg_pull_none>;/* cif_d1 */ 2075 }; 2076 }; 2077 2078 emmc { 2079 emmc_clk: emmc-clk { 2080 rockchip,pins = 2081 /* emmc_clkout */ 2082 <1 RK_PB1 1 &pcfg_pull_up_4ma>; 2083 }; 2084 2085 emmc_rstnout: emmc-rstnout { 2086 rockchip,pins = 2087 /* emmc_rstn */ 2088 <1 RK_PB3 1 &pcfg_pull_none>; 2089 }; 2090 2091 emmc_bus8: emmc-bus8 { 2092 rockchip,pins = 2093 /* emmc_d0 */ 2094 <1 RK_PA0 1 &pcfg_pull_up_4ma>, 2095 /* emmc_d1 */ 2096 <1 RK_PA1 1 &pcfg_pull_up_4ma>, 2097 /* emmc_d2 */ 2098 <1 RK_PA2 1 &pcfg_pull_up_4ma>, 2099 /* emmc_d3 */ 2100 <1 RK_PA3 1 &pcfg_pull_up_4ma>, 2101 /* emmc_d4 */ 2102 <1 RK_PA4 1 &pcfg_pull_up_4ma>, 2103 /* emmc_d5 */ 2104 <1 RK_PA5 1 &pcfg_pull_up_4ma>, 2105 /* emmc_d6 */ 2106 <1 RK_PA6 1 &pcfg_pull_up_4ma>, 2107 /* emmc_d7 */ 2108 <1 RK_PA7 1 &pcfg_pull_up_4ma>; 2109 }; 2110 2111 emmc_pwren: emmc-pwren { 2112 rockchip,pins = 2113 <1 RK_PB0 1 &pcfg_pull_none>; 2114 }; 2115 2116 emmc_cmd: emmc-cmd { 2117 rockchip,pins = 2118 <1 RK_PB2 1 &pcfg_pull_up_4ma>; 2119 }; 2120 }; 2121 2122 gmac { 2123 rgmii_pins: rgmii-pins { 2124 rockchip,pins = 2125 /* rgmii_txen */ 2126 <2 RK_PA1 2 &pcfg_pull_none_4ma>, 2127 /* rgmii_txd1 */ 2128 <2 RK_PA2 2 &pcfg_pull_none_4ma>, 2129 /* rgmii_txd0 */ 2130 <2 RK_PA3 2 &pcfg_pull_none_4ma>, 2131 /* rgmii_rxd0 */ 2132 <2 RK_PA4 2 &pcfg_pull_none>, 2133 /* rgmii_rxd1 */ 2134 <2 RK_PA5 2 &pcfg_pull_none>, 2135 /* rgmii_rxdv */ 2136 <2 RK_PA7 2 &pcfg_pull_none>, 2137 /* rgmii_mdio */ 2138 <2 RK_PB0 2 &pcfg_pull_none_2ma>, 2139 /* rgmii_mdc */ 2140 <2 RK_PB2 2 &pcfg_pull_none_2ma>, 2141 /* rgmii_txd3 */ 2142 <2 RK_PB3 2 &pcfg_pull_none_4ma>, 2143 /* rgmii_txd2 */ 2144 <2 RK_PB4 2 &pcfg_pull_none_4ma>, 2145 /* rgmii_rxd2 */ 2146 <2 RK_PB5 2 &pcfg_pull_none>, 2147 /* rgmii_rxd3 */ 2148 <2 RK_PB6 2 &pcfg_pull_none>, 2149 /* rgmii_clk */ 2150 <2 RK_PB7 2 &pcfg_pull_none>, 2151 /* rgmii_txclk */ 2152 <2 RK_PC1 2 &pcfg_pull_none_4ma>, 2153 /* rgmii_rxclk */ 2154 <2 RK_PC2 2 &pcfg_pull_none>; 2155 }; 2156 2157 rmii_pins: rmii-pins { 2158 rockchip,pins = 2159 /* rmii_txen */ 2160 <2 RK_PA1 2 &pcfg_pull_none_4ma>, 2161 /* rmii_txd1 */ 2162 <2 RK_PA2 2 &pcfg_pull_none_4ma>, 2163 /* rmii_txd0 */ 2164 <2 RK_PA3 2 &pcfg_pull_none_4ma>, 2165 /* rmii_rxd0 */ 2166 <2 RK_PA4 2 &pcfg_pull_none>, 2167 /* rmii_rxd1 */ 2168 <2 RK_PA5 2 &pcfg_pull_none>, 2169 /* rmii_rxer */ 2170 <2 RK_PA6 2 &pcfg_pull_none>, 2171 /* rmii_rxdv */ 2172 <2 RK_PA7 2 &pcfg_pull_none>, 2173 /* rmii_mdio */ 2174 <2 RK_PB0 2 &pcfg_pull_none_2ma>, 2175 /* rmii_mdc */ 2176 <2 RK_PB2 2 &pcfg_pull_none_2ma>, 2177 /* rmii_clk */ 2178 <2 RK_PB7 2 &pcfg_pull_none>; 2179 }; 2180 }; 2181 2182 i2c0 { 2183 i2c0_xfer: i2c0-xfer { 2184 rockchip,pins = 2185 /* i2c0_sda */ 2186 <0 RK_PB1 1 &pcfg_pull_none_2ma_smt>, 2187 /* i2c0_scl */ 2188 <0 RK_PB0 1 &pcfg_pull_none_2ma_smt>; 2189 }; 2190 }; 2191 2192 i2c1 { 2193 i2c1_xfer: i2c1-xfer { 2194 rockchip,pins = 2195 /* i2c1_sda */ 2196 <0 RK_PC1 1 &pcfg_pull_none_2ma_smt>, 2197 /* i2c1_scl */ 2198 <0 RK_PC0 1 &pcfg_pull_none_2ma_smt>; 2199 }; 2200 }; 2201 2202 i2c2m0 { 2203 i2c2m0_xfer: i2c2m0-xfer { 2204 rockchip,pins = 2205 /* i2c2m0_sda */ 2206 <3 RK_PB4 2 &pcfg_pull_none_2ma_smt>, 2207 /* i2c2m0_scl */ 2208 <3 RK_PB3 2 &pcfg_pull_none_2ma_smt>; 2209 }; 2210 }; 2211 2212 i2c2m1 { 2213 i2c2m1_xfer: i2c2m1-xfer { 2214 rockchip,pins = 2215 /* i2c2m1_sda */ 2216 <1 RK_PB5 2 &pcfg_pull_none_2ma_smt>, 2217 /* i2c2m1_scl */ 2218 <1 RK_PB4 2 &pcfg_pull_none_2ma_smt>; 2219 }; 2220 }; 2221 2222 i2c3 { 2223 i2c3_xfer: i2c3-xfer { 2224 rockchip,pins = 2225 /* i2c3_sda */ 2226 <2 RK_PD1 1 &pcfg_pull_none_2ma_smt>, 2227 /* i2c3_scl */ 2228 <2 RK_PD0 1 &pcfg_pull_none_2ma_smt>; 2229 }; 2230 }; 2231 2232 i2c4 { 2233 i2c4_xfer: i2c4-xfer { 2234 rockchip,pins = 2235 /* i2c4_sda */ 2236 <3 RK_PC3 3 &pcfg_pull_none_2ma_smt>, 2237 /* i2c4_scl */ 2238 <3 RK_PC2 3 &pcfg_pull_none_2ma_smt>; 2239 }; 2240 }; 2241 2242 i2c5 { 2243 i2c5_xfer: i2c5-xfer { 2244 rockchip,pins = 2245 /* i2c5_sda */ 2246 <4 RK_PC2 1 &pcfg_pull_none_2ma_smt>, 2247 /* i2c5_scl */ 2248 <4 RK_PC1 1 &pcfg_pull_none_2ma_smt>; 2249 }; 2250 }; 2251 2252 i2s1 { 2253 i2s1_2ch_lrck: i2s1-2ch-lrck { 2254 rockchip,pins = 2255 <3 RK_PA0 1 &pcfg_pull_none_2ma_smt>; 2256 }; 2257 i2s1_2ch_sclk: i2s1-2ch-sclk { 2258 rockchip,pins = 2259 <3 RK_PA1 1 &pcfg_pull_none_2ma_smt>; 2260 }; 2261 i2s1_2ch_mclk: i2s1-2ch-mclk { 2262 rockchip,pins = 2263 <3 RK_PA2 1 &pcfg_pull_none_2ma_smt>; 2264 }; 2265 i2s1_2ch_sdo: i2s1-2ch-sdo { 2266 rockchip,pins = 2267 <3 RK_PA3 1 &pcfg_pull_none_2ma>; 2268 }; 2269 i2s1_2ch_sdi: i2s1-2ch-sdi { 2270 rockchip,pins = 2271 <3 RK_PA4 1 &pcfg_pull_none_2ma>; 2272 }; 2273 }; 2274 2275 i2s0 { 2276 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 2277 rockchip,pins = 2278 <3 RK_PA5 1 &pcfg_pull_none_2ma>; 2279 }; 2280 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 2281 rockchip,pins = 2282 <3 RK_PA6 1 &pcfg_pull_none_2ma>; 2283 }; 2284 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 2285 rockchip,pins = 2286 <3 RK_PA7 1 &pcfg_pull_none_2ma>; 2287 }; 2288 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 2289 rockchip,pins = 2290 <3 RK_PB0 1 &pcfg_pull_none_2ma_smt>; 2291 }; 2292 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 2293 rockchip,pins = 2294 <3 RK_PB1 1 &pcfg_pull_none_2ma_smt>; 2295 }; 2296 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 2297 rockchip,pins = 2298 <3 RK_PB2 1 &pcfg_pull_none_2ma>; 2299 }; 2300 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 2301 rockchip,pins = 2302 <3 RK_PB3 1 &pcfg_pull_none_2ma>; 2303 }; 2304 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 2305 rockchip,pins = 2306 <3 RK_PB4 1 &pcfg_pull_none_2ma>; 2307 }; 2308 i2s0_8ch_mclk: i2s0-8ch-mclk { 2309 rockchip,pins = 2310 <3 RK_PB5 1 &pcfg_pull_none_2ma_smt>; 2311 }; 2312 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 2313 rockchip,pins = 2314 <3 RK_PB6 1 &pcfg_pull_none_2ma_smt>; 2315 }; 2316 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 2317 rockchip,pins = 2318 <3 RK_PB7 1 &pcfg_pull_none_2ma_smt>; 2319 }; 2320 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 2321 rockchip,pins = 2322 <3 RK_PC0 1 &pcfg_pull_none_2ma>; 2323 }; 2324 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 2325 rockchip,pins = 2326 <3 RK_PC1 1 &pcfg_pull_none_2ma>; 2327 }; 2328 }; 2329 2330 lcdc { 2331 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 2332 rockchip,pins = 2333 /* lcdc_clkm0 */ 2334 <2 RK_PC6 3 &pcfg_pull_none>; 2335 }; 2336 2337 lcdc_rgb_den_pin: lcdc-rgb-den-pin { 2338 rockchip,pins = 2339 /* lcdc_denm0 */ 2340 <2 RK_PC7 3 &pcfg_pull_none>; 2341 }; 2342 2343 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 2344 rockchip,pins = 2345 /* lcdc_hsyncm0 */ 2346 <2 RK_PB2 3 &pcfg_pull_none>; 2347 }; 2348 2349 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 2350 rockchip,pins = 2351 /* lcdc_vsyncm0 */ 2352 <2 RK_PB3 3 &pcfg_pull_none>; 2353 }; 2354 2355 lcdc_rgb_m1_hsync_pin: lcdc-rgb-m1-hsync-pin { 2356 rockchip,pins = 2357 /* lcdc_hsyncm1 */ 2358 <3 RK_PB2 3 &pcfg_pull_none>; 2359 }; 2360 2361 lcdc_rgb_m1_vsync_pin: lcdc-rgb-m1-vsync-pin { 2362 rockchip,pins = 2363 /* lcdc_vsyncm1 */ 2364 <3 RK_PB3 3 &pcfg_pull_none>; 2365 }; 2366 2367 lcdc_rgb666_data_pins: lcdc-rgb666-data-pins { 2368 rockchip,pins = 2369 /* lcdc_d0m0 */ 2370 <2 RK_PA2 3 &pcfg_pull_none>, 2371 /* lcdc_d1m0 */ 2372 <2 RK_PA3 3 &pcfg_pull_none>, 2373 /* lcdc_d2m0 */ 2374 <2 RK_PC2 3 &pcfg_pull_none>, 2375 /* lcdc_d3m0 */ 2376 <2 RK_PC3 3 &pcfg_pull_none>, 2377 /* lcdc_d4m0 */ 2378 <2 RK_PC4 3 &pcfg_pull_none>, 2379 /* lcdc_d5m0 */ 2380 <2 RK_PC5 3 &pcfg_pull_none>, 2381 /* lcdc_d6m0 */ 2382 <2 RK_PA0 3 &pcfg_pull_none>, 2383 /* lcdc_d7m0 */ 2384 <2 RK_PA1 3 &pcfg_pull_none>, 2385 /* lcdc_d8 */ 2386 <3 RK_PC2 1 &pcfg_pull_none>, 2387 /* lcdc_d9 */ 2388 <3 RK_PC3 1 &pcfg_pull_none>, 2389 /* lcdc_d10 */ 2390 <3 RK_PC4 1 &pcfg_pull_none>, 2391 /* lcdc_d11 */ 2392 <3 RK_PC5 1 &pcfg_pull_none>, 2393 /* lcdc_d12 */ 2394 <3 RK_PC6 1 &pcfg_pull_none>, 2395 /* lcdc_d13 */ 2396 <3 RK_PC7 1 &pcfg_pull_none>, 2397 /* lcdc_d14 */ 2398 <3 RK_PD0 1 &pcfg_pull_none>, 2399 /* lcdc_d15 */ 2400 <3 RK_PD1 1 &pcfg_pull_none>, 2401 /* lcdc_d16 */ 2402 <3 RK_PD2 1 &pcfg_pull_none>, 2403 /* lcdc_d17 */ 2404 <3 RK_PD3 1 &pcfg_pull_none>; 2405 }; 2406 2407 lcdc_rgb565_data_pins: lcdc-rgb565-data-pins { 2408 rockchip,pins = 2409 /* lcdc_d0m0 */ 2410 <2 RK_PA2 3 &pcfg_pull_none>, 2411 /* lcdc_d1m0 */ 2412 <2 RK_PA3 3 &pcfg_pull_none>, 2413 /* lcdc_d2m0 */ 2414 <2 RK_PC2 3 &pcfg_pull_none>, 2415 /* lcdc_d3m0 */ 2416 <2 RK_PC3 3 &pcfg_pull_none>, 2417 /* lcdc_d4m0 */ 2418 <2 RK_PC4 3 &pcfg_pull_none>, 2419 /* lcdc_d5m0 */ 2420 <2 RK_PC5 3 &pcfg_pull_none>, 2421 /* lcdc_d6m0 */ 2422 <2 RK_PA0 3 &pcfg_pull_none>, 2423 /* lcdc_d7m0 */ 2424 <2 RK_PA1 3 &pcfg_pull_none>, 2425 /* lcdc_d8 */ 2426 <3 RK_PC2 1 &pcfg_pull_none>, 2427 /* lcdc_d9 */ 2428 <3 RK_PC3 1 &pcfg_pull_none>, 2429 /* lcdc_d10 */ 2430 <3 RK_PC4 1 &pcfg_pull_none>, 2431 /* lcdc_d11 */ 2432 <3 RK_PC5 1 &pcfg_pull_none>, 2433 /* lcdc_d12 */ 2434 <3 RK_PC6 1 &pcfg_pull_none>, 2435 /* lcdc_d13 */ 2436 <3 RK_PC7 1 &pcfg_pull_none>, 2437 /* lcdc_d14 */ 2438 <3 RK_PD0 1 &pcfg_pull_none>, 2439 /* lcdc_d15 */ 2440 <3 RK_PD1 1 &pcfg_pull_none>; 2441 }; 2442 }; 2443 2444 pciusb { 2445 pciusb_pins: pciusb-pins { 2446 rockchip,pins = 2447 /* pciusb_debug0 */ 2448 <4 RK_PB4 3 &pcfg_pull_none>, 2449 /* pciusb_debug1 */ 2450 <4 RK_PB5 3 &pcfg_pull_none>, 2451 /* pciusb_debug2 */ 2452 <4 RK_PB6 3 &pcfg_pull_none>, 2453 /* pciusb_debug3 */ 2454 <4 RK_PB7 3 &pcfg_pull_none>, 2455 /* pciusb_debug4 */ 2456 <4 RK_PC0 3 &pcfg_pull_none>, 2457 /* pciusb_debug5 */ 2458 <4 RK_PC1 3 &pcfg_pull_none>, 2459 /* pciusb_debug6 */ 2460 <4 RK_PC2 3 &pcfg_pull_none>, 2461 /* pciusb_debug7 */ 2462 <4 RK_PC3 3 &pcfg_pull_none>; 2463 }; 2464 2465 pcie_clkreq: pcie-clkreq { 2466 rockchip,pins = 2467 /* pcie_clkreqn_m1 */ 2468 <0 RK_PC6 1 &pcfg_pull_none >; 2469 }; 2470 }; 2471 2472 pdm { 2473 pdm_clk: pdm-clk { 2474 rockchip,pins = 2475 /* pdm_clk0 */ 2476 <3 RK_PB0 2 &pcfg_pull_none_2ma>; 2477 }; 2478 2479 pdm_sdi3: pdm-sdi3 { 2480 rockchip,pins = 2481 <3 RK_PA5 2 &pcfg_pull_none_2ma>; 2482 }; 2483 2484 pdm_sdi2: pdm-sdi2 { 2485 rockchip,pins = 2486 <3 RK_PA6 2 &pcfg_pull_none_2ma>; 2487 }; 2488 2489 pdm_sdi1: pdm-sdi1 { 2490 rockchip,pins = 2491 <3 RK_PA7 2 &pcfg_pull_none_2ma>; 2492 }; 2493 2494 pdm_clk1: pdm-clk1 { 2495 rockchip,pins = 2496 <3 RK_PB1 2 &pcfg_pull_none_2ma>; 2497 }; 2498 2499 pdm_sdi0: pdm-sdi0 { 2500 rockchip,pins = 2501 <3 RK_PC1 2 &pcfg_pull_none_2ma>; 2502 }; 2503 }; 2504 2505 pwm0 { 2506 pwm0_pin: pwm0-pin { 2507 rockchip,pins = 2508 <0 RK_PB7 1 &pcfg_pull_none_2ma>; 2509 }; 2510 }; 2511 2512 pwm1 { 2513 pwm1_pin: pwm1-pin { 2514 rockchip,pins = 2515 <0 RK_PC3 1 &pcfg_pull_none_2ma>; 2516 }; 2517 }; 2518 2519 pwm2 { 2520 pwm2_pin: pwm2-pin { 2521 rockchip,pins = 2522 <0 RK_PC5 1 &pcfg_pull_none_2ma>; 2523 }; 2524 }; 2525 2526 pwm3 { 2527 pwm3_pin: pwm3-pin { 2528 rockchip,pins = 2529 <0 RK_PC4 1 &pcfg_pull_none_2ma>; 2530 }; 2531 }; 2532 2533 pwm4 { 2534 pwm4_pin: pwm4-pin { 2535 rockchip,pins = 2536 <1 RK_PB6 2 &pcfg_pull_none_2ma>; 2537 }; 2538 }; 2539 2540 pwm5 { 2541 pwm5_pin: pwm5-pin { 2542 rockchip,pins = 2543 <1 RK_PB7 2 &pcfg_pull_none_2ma>; 2544 }; 2545 }; 2546 pwm6 { 2547 pwm6_pin: pwm6-pin { 2548 rockchip,pins = 2549 <3 RK_PA1 2 &pcfg_pull_none_2ma>; 2550 }; 2551 }; 2552 2553 pwm7 { 2554 pwm7_pin: pwm7-pin { 2555 rockchip,pins = 2556 <3 RK_PA2 2 &pcfg_pull_none_2ma>; 2557 }; 2558 }; 2559 2560 pwm8 { 2561 pwm8_pin: pwm8-pin { 2562 rockchip,pins = 2563 <3 RK_PD0 2 &pcfg_pull_none_2ma>; 2564 }; 2565 }; 2566 2567 pwm9 { 2568 pwm9_pin: pwm9-pin { 2569 rockchip,pins = 2570 <3 RK_PD1 2 &pcfg_pull_none_2ma>; 2571 }; 2572 }; 2573 2574 pwm10 { 2575 pwm10_pin: pwm10-pin { 2576 rockchip,pins = 2577 <3 RK_PD2 2 &pcfg_pull_none_2ma>; 2578 }; 2579 }; 2580 2581 pwm11 { 2582 pwm11_pin: pwm11-pin { 2583 rockchip,pins = 2584 <3 RK_PD3 2 &pcfg_pull_none_2ma>; 2585 }; 2586 }; 2587 2588 sdmmc0 { 2589 sdmmc0_bus4: sdmmc0-bus4 { 2590 rockchip,pins = 2591 /* sdmmc0_d0 */ 2592 <4 RK_PA2 1 &pcfg_pull_up_8ma>, 2593 /* sdmmc0_d1 */ 2594 <4 RK_PA3 1 &pcfg_pull_up_8ma>, 2595 /* sdmmc0_d2 */ 2596 <4 RK_PA4 1 &pcfg_pull_up_8ma>, 2597 /* sdmmc0_d3 */ 2598 <4 RK_PA5 1 &pcfg_pull_up_8ma>; 2599 }; 2600 2601 sdmmc0_cmd: sdmmc0-cmd { 2602 rockchip,pins = 2603 <4 RK_PA0 1 &pcfg_pull_up_8ma>; 2604 }; 2605 2606 sdmmc0_clk: sdmmc0-clk { 2607 rockchip,pins = 2608 <4 RK_PA1 1 &pcfg_pull_up_8ma>; 2609 }; 2610 2611 sdmmc0_detn: sdmmc0-detn { 2612 rockchip,pins = 2613 <0 RK_PA3 1 &pcfg_pull_none>; 2614 }; 2615 }; 2616 2617 sdmmc1 { 2618 sdmmc1_bus4: sdmmc1-bus4 { 2619 rockchip,pins = 2620 /* sdmmc1_d0 */ 2621 <4 RK_PB0 1 &pcfg_pull_up_4ma>, 2622 /* sdmmc1_d1 */ 2623 <4 RK_PB1 1 &pcfg_pull_up_4ma>, 2624 /* sdmmc1_d2 */ 2625 <4 RK_PB2 1 &pcfg_pull_up_4ma>, 2626 /* sdmmc1_d3 */ 2627 <4 RK_PB3 1 &pcfg_pull_up_4ma>; 2628 }; 2629 2630 sdmmc1_cmd: sdmmc1-cmd { 2631 rockchip,pins = 2632 <4 RK_PA6 1 &pcfg_pull_up_4ma>; 2633 }; 2634 2635 sdmmc1_clk: sdmmc1-clk { 2636 rockchip,pins = 2637 <4 RK_PA7 1 &pcfg_pull_up_4ma>; 2638 }; 2639 }; 2640 2641 spi0 { 2642 spi0_mosi: spi0-mosi { 2643 rockchip,pins = 2644 <1 RK_PB4 1 &pcfg_pull_up_2ma>; 2645 }; 2646 2647 spi0_miso: spi0-miso { 2648 rockchip,pins = 2649 <1 RK_PB5 1 &pcfg_pull_up_2ma>; 2650 }; 2651 2652 spi0_csn: spi0-csn { 2653 rockchip,pins = 2654 <1 RK_PB6 1 &pcfg_pull_up_2ma>; 2655 }; 2656 2657 spi0_clk: spi0-clk { 2658 rockchip,pins = 2659 <1 RK_PB7 1 &pcfg_pull_up_2ma>; 2660 }; 2661 2662 spi0_mosi_hs: spi0-mosi-hs { 2663 rockchip,pins = 2664 <1 RK_PB4 1 &pcfg_pull_up_2ma>; 2665 }; 2666 2667 spi0_miso_hs: spi0-miso-hs { 2668 rockchip,pins = 2669 <1 RK_PB5 1 &pcfg_pull_up_2ma>; 2670 }; 2671 2672 spi0_csn_hs: spi0-csn-hs { 2673 rockchip,pins = 2674 <1 RK_PB6 1 &pcfg_pull_up_2ma>; 2675 }; 2676 2677 spi0_clk_hs: spi0-clk-hs { 2678 rockchip,pins = 2679 <1 RK_PB7 1 &pcfg_pull_up_2ma>; 2680 }; 2681 }; 2682 2683 spi1m0 { 2684 spi1_clk: spi1-clk { 2685 rockchip,pins = 2686 <4 RK_PB4 2 &pcfg_pull_up_2ma>; 2687 }; 2688 2689 spi1_mosi: spi1-mosi { 2690 rockchip,pins = 2691 <4 RK_PB5 2 &pcfg_pull_up_2ma>; 2692 }; 2693 2694 spi1_csn0: spi1-csn0 { 2695 rockchip,pins = 2696 <4 RK_PB6 2 &pcfg_pull_up_2ma>; 2697 }; 2698 2699 spi1_miso: spi1-miso { 2700 rockchip,pins = 2701 <4 RK_PB7 2 &pcfg_pull_up_2ma>; 2702 }; 2703 2704 spi1_csn1: spi1-csn1 { 2705 rockchip,pins = 2706 <4 RK_PC0 2 &pcfg_pull_up_2ma>; 2707 }; 2708 2709 spi1_clk_hs: spi1-clk-hs { 2710 rockchip,pins = 2711 <4 RK_PB4 2 &pcfg_pull_up_2ma>; 2712 }; 2713 2714 spi1_mosi_hs: spi1-mosi-hs { 2715 rockchip,pins = 2716 <4 RK_PB5 2 &pcfg_pull_up_2ma>; 2717 }; 2718 2719 spi1_csn0_hs: spi1-csn0-hs { 2720 rockchip,pins = 2721 <4 RK_PB6 2 &pcfg_pull_up_2ma>; 2722 }; 2723 2724 spi1_miso_hs: spi1-miso-hs { 2725 rockchip,pins = 2726 <4 RK_PB7 2 &pcfg_pull_up_2ma>; 2727 }; 2728 2729 spi1_csn1_hs: spi1-csn1-hs { 2730 rockchip,pins = 2731 <4 RK_PC0 2 &pcfg_pull_up_2ma>; 2732 }; 2733 }; 2734 2735 spi1m1 { 2736 spi1m1_clk: spi1m1-clk { 2737 rockchip,pins = 2738 <3 RK_PC7 3 &pcfg_pull_up_2ma>; 2739 }; 2740 2741 spi1m1_mosi: spi1m1-mosi { 2742 rockchip,pins = 2743 <3 RK_PD0 3 &pcfg_pull_up_2ma>; 2744 }; 2745 2746 spi1m1_csn0: spi1m1-csn0 { 2747 rockchip,pins = 2748 <3 RK_PD1 3 &pcfg_pull_up_2ma>; 2749 }; 2750 2751 spi1m1_miso: spi1m1-miso { 2752 rockchip,pins = 2753 <3 RK_PD2 3 &pcfg_pull_up_2ma>; 2754 }; 2755 2756 spi1m1_csn1: spi1m1-csn1 { 2757 rockchip,pins = 2758 <3 RK_PD3 3 &pcfg_pull_up_2ma>; 2759 }; 2760 2761 spi1m1_clk_hs: spi1m1-clk-hs { 2762 rockchip,pins = 2763 <3 RK_PC7 3 &pcfg_pull_up_2ma>; 2764 }; 2765 2766 spi1m1_mosi_hs: spi1m1-mosi-hs { 2767 rockchip,pins = 2768 <3 RK_PD0 3 &pcfg_pull_up_2ma>; 2769 }; 2770 2771 spi1m1_csn0_hs: spi1m1-csn0-hs { 2772 rockchip,pins = 2773 <3 RK_PD1 3 &pcfg_pull_up_2ma>; 2774 }; 2775 2776 spi1m1_miso_hs: spi1m1-miso-hs { 2777 rockchip,pins = 2778 <3 RK_PD2 3 &pcfg_pull_up_2ma>; 2779 }; 2780 2781 spi1m1_csn1_hs: spi1m1-csn1-hs { 2782 rockchip,pins = 2783 <3 RK_PD3 3 &pcfg_pull_up_2ma>; 2784 }; 2785 }; 2786 2787 spi2m0 { 2788 spi2m0_miso: spi2m0-miso { 2789 rockchip,pins = 2790 <1 RK_PA6 2 &pcfg_pull_up_2ma>; 2791 }; 2792 2793 spi2m0_clk: spi2m0-clk { 2794 rockchip,pins = 2795 <1 RK_PA7 2 &pcfg_pull_up_2ma>; 2796 }; 2797 2798 spi2m0_mosi: spi2m0-mosi { 2799 rockchip,pins = 2800 <1 RK_PB0 2 &pcfg_pull_up_2ma>; 2801 }; 2802 2803 spi2m0_csn: spi2m0-csn { 2804 rockchip,pins = 2805 <1 RK_PB1 2 &pcfg_pull_up_2ma>; 2806 }; 2807 2808 spi2m0_miso_hs: spi2m0-miso-hs { 2809 rockchip,pins = 2810 <1 RK_PA6 2 &pcfg_pull_up_2ma>; 2811 }; 2812 2813 spi2m0_clk_hs: spi2m0-clk-hs { 2814 rockchip,pins = 2815 <1 RK_PA7 2 &pcfg_pull_up_2ma>; 2816 }; 2817 2818 spi2m0_mosi_hs: spi2m0-mosi-hs { 2819 rockchip,pins = 2820 <1 RK_PB0 2 &pcfg_pull_up_2ma>; 2821 }; 2822 2823 spi2m0_csn_hs: spi2m0-csn-hs { 2824 rockchip,pins = 2825 <1 RK_PB1 2 &pcfg_pull_up_2ma>; 2826 }; 2827 }; 2828 2829 spi2m1 { 2830 spi2m1_miso: spi2m1-miso { 2831 rockchip,pins = 2832 <2 RK_PA4 3 &pcfg_pull_up_2ma>; 2833 }; 2834 2835 spi2m1_clk: spi2m1-clk { 2836 rockchip,pins = 2837 <2 RK_PA5 3 &pcfg_pull_up_2ma>; 2838 }; 2839 2840 spi2m1_mosi: spi2m1-mosi { 2841 rockchip,pins = 2842 <2 RK_PA6 3 &pcfg_pull_up_2ma>; 2843 }; 2844 2845 spi2m1_csn: spi2m1-csn { 2846 rockchip,pins = 2847 <2 RK_PA7 3 &pcfg_pull_up_2ma>; 2848 }; 2849 2850 spi2m1_miso_hs: spi2m1-miso-hs { 2851 rockchip,pins = 2852 <2 RK_PA4 3 &pcfg_pull_up_2ma>; 2853 }; 2854 2855 spi2m1_clk_hs: spi2m1-clk-hs { 2856 rockchip,pins = 2857 <2 RK_PA5 3 &pcfg_pull_up_2ma>; 2858 }; 2859 2860 spi2m1_mosi_hs: spi2m1-mosi-hs { 2861 rockchip,pins = 2862 <2 RK_PA6 3 &pcfg_pull_up_2ma>; 2863 }; 2864 2865 spi2m1_csn_hs: spi2m1-csn-hs { 2866 rockchip,pins = 2867 <2 RK_PA7 3 &pcfg_pull_up_2ma>; 2868 }; 2869 }; 2870 2871 uart0 { 2872 uart0_xfer: uart0-xfer { 2873 rockchip,pins = 2874 /* uart0_rx */ 2875 <0 RK_PB3 1 &pcfg_pull_up_2ma>, 2876 /* uart0_tx */ 2877 <0 RK_PB2 1 &pcfg_pull_up_2ma>; 2878 }; 2879 2880 uart0_cts: uart0-cts { 2881 rockchip,pins = 2882 <0 RK_PB4 1 &pcfg_pull_none>; 2883 }; 2884 2885 uart0_rts: uart0-rts { 2886 rockchip,pins = 2887 <0 RK_PB5 1 &pcfg_pull_none>; 2888 }; 2889 }; 2890 2891 uart1 { 2892 uart1m0_xfer: uart1m0-xfer { 2893 rockchip,pins = 2894 /* uart1_rxm0 */ 2895 <4 RK_PB0 2 &pcfg_pull_up_2ma>, 2896 /* uart1_txm0 */ 2897 <4 RK_PB1 2 &pcfg_pull_up_2ma>; 2898 }; 2899 2900 uart1m1_xfer: uart1m1-xfer { 2901 rockchip,pins = 2902 /* uart1_rxm1 */ 2903 <1 RK_PB4 3 &pcfg_pull_up_2ma>, 2904 /* uart1_txm1 */ 2905 <1 RK_PB5 3 &pcfg_pull_up_2ma>; 2906 }; 2907 2908 uart1_cts: uart1-cts { 2909 rockchip,pins = 2910 <4 RK_PB2 2 &pcfg_pull_none>; 2911 }; 2912 2913 uart1_rts: uart1-rts { 2914 rockchip,pins = 2915 <4 RK_PB3 2 &pcfg_pull_none>; 2916 }; 2917 }; 2918 2919 uart2 { 2920 uart2m0_xfer: uart2m0-xfer { 2921 rockchip,pins = 2922 /* uart2_rxm0 */ 2923 <4 RK_PA3 2 &pcfg_pull_up_2ma>, 2924 /* uart2_txm0 */ 2925 <4 RK_PA2 2 &pcfg_pull_up_2ma>; 2926 }; 2927 2928 uart2m1_xfer: uart2m1-xfer { 2929 rockchip,pins = 2930 /* uart2_rxm1 */ 2931 <2 RK_PD1 2 &pcfg_pull_up_2ma>, 2932 /* uart2_txm1 */ 2933 <2 RK_PD0 2 &pcfg_pull_up_2ma>; 2934 }; 2935 2936 uart2m2_xfer: uart2m2-xfer { 2937 rockchip,pins = 2938 /* uart2_rxm2 */ 2939 <3 RK_PA4 2 &pcfg_pull_up_2ma>, 2940 /* uart2_txm2 */ 2941 <3 RK_PA3 2 &pcfg_pull_up_2ma>; 2942 }; 2943 }; 2944 2945 uart3 { 2946 uart3m0_xfer: uart3m0-xfer { 2947 rockchip,pins = 2948 /* uart3_rxm0 */ 2949 <0 RK_PC4 2 &pcfg_pull_up_2ma>, 2950 /* uart3_txm0 */ 2951 <0 RK_PC3 2 &pcfg_pull_up_2ma>; 2952 }; 2953 2954 uart3_ctsm0: uart3-ctsm0 { 2955 rockchip,pins = 2956 <0 RK_PC6 2 &pcfg_pull_none>; 2957 }; 2958 2959 uart3_rtsm0: uart3-rtsm0 { 2960 rockchip,pins = 2961 <0 RK_PC7 2 &pcfg_pull_none>; 2962 }; 2963 }; 2964 2965 uart4 { 2966 uart4_xfer: uart4-xfer { 2967 rockchip,pins = 2968 /* uart4_rx */ 2969 <4 RK_PB4 1 &pcfg_pull_up_2ma>, 2970 /* uart4_tx */ 2971 <4 RK_PB5 1 &pcfg_pull_up_2ma>; 2972 }; 2973 2974 uart4_cts: uart4-cts { 2975 rockchip,pins = 2976 <4 RK_PB6 1 &pcfg_pull_none>; 2977 }; 2978 2979 uart4_rts: uart4-rts { 2980 rockchip,pins = 2981 <4 RK_PB7 1 &pcfg_pull_none>; 2982 }; 2983 }; 2984 2985 uart5 { 2986 uart5_xfer: uart5-xfer { 2987 rockchip,pins = 2988 /* uart5_rx */ 2989 <3 RK_PC3 2 &pcfg_pull_up_2ma>, 2990 /* uart5_tx */ 2991 <3 RK_PC2 2 &pcfg_pull_up_2ma>; 2992 }; 2993 }; 2994 2995 uart6 { 2996 uart6_xfer: uart6-xfer { 2997 rockchip,pins = 2998 /* uart6_rx */ 2999 <3 RK_PC5 2 &pcfg_pull_up_2ma>, 3000 /* uart6_tx */ 3001 <3 RK_PC4 2 &pcfg_pull_up_2ma>; 3002 }; 3003 }; 3004 3005 uart7 { 3006 uart7_xfer: uart7-xfer { 3007 rockchip,pins = 3008 /* uart7_rx */ 3009 <3 RK_PC7 2 &pcfg_pull_up_2ma>, 3010 /* uart7_tx */ 3011 <3 RK_PC6 2 &pcfg_pull_up_2ma>; 3012 }; 3013 }; 3014 3015 tsadc { 3016 tsadc_otp_gpio: tsadc-otp-gpio { 3017 rockchip,pins = 3018 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 3019 }; 3020 3021 tsadc_otp_out: tsadc-otp-out { 3022 rockchip,pins = 3023 <0 RK_PA6 2 &pcfg_pull_none>; 3024 }; 3025 }; 3026 3027 xin32k { 3028 clkin_32k: clkin-32k { 3029 rockchip,pins = 3030 <0 RK_PC2 1 &pcfg_pull_none>; 3031 }; 3032 3033 clkout_32k: clkout-32k { 3034 rockchip,pins = 3035 <0 RK_PC2 1 &pcfg_pull_none>; 3036 }; 3037 }; 3038 }; 3039}; 3040