1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun#include "rk3288-th804.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "Rockchip RK3288 TH804 avb"; 12*4882a593Smuzhiyun compatible = "rockchip,rk3288-th804", "rockchip,rk3288"; 13*4882a593Smuzhiyun chosen { 14*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xff690000 vmalloc=496M console=ttyFIQ0 androidboot.baseband=N/A androidboot.veritymode=enforcing androidboot.hardware=rk30board androidboot.console=ttyFIQ0 init=/init kpti=0"; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun vcc_camera: vcc-camera-regulator { 17*4882a593Smuzhiyun compatible = "regulator-fixed"; 18*4882a593Smuzhiyun gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; 19*4882a593Smuzhiyun pinctrl-names = "default"; 20*4882a593Smuzhiyun pinctrl-0 = <&camera_pwr>; 21*4882a593Smuzhiyun regulator-name = "vcc_camera"; 22*4882a593Smuzhiyun enable-active-high; 23*4882a593Smuzhiyun regulator-always-on; 24*4882a593Smuzhiyun regulator-boot-on; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun}; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun&io_domains { 29*4882a593Smuzhiyun status = "okay"; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun dvp-supply = <&vcc_18>; 32*4882a593Smuzhiyun sdcard-supply = <&vccio_sd>; 33*4882a593Smuzhiyun wifi-supply = <&vccio_wl>; 34*4882a593Smuzhiyun}; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun&isp { 37*4882a593Smuzhiyun status = "disabled"; 38*4882a593Smuzhiyun}; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun&i2c3 { 41*4882a593Smuzhiyun status = "okay"; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun gc2145: gc2145@3c { 44*4882a593Smuzhiyun compatible = "galaxycore,gc2145"; 45*4882a593Smuzhiyun reg = <0x3c>; 46*4882a593Smuzhiyun clocks = <&cru SCLK_VIP_OUT>; 47*4882a593Smuzhiyun clock-names = "xvclk"; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /*power-gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; */ 50*4882a593Smuzhiyun pwdn-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun rockchip,camera-module-index = <1>; 53*4882a593Smuzhiyun rockchip,camera-module-facing = "front"; 54*4882a593Smuzhiyun rockchip,camera-module-name = "CameraKing"; 55*4882a593Smuzhiyun rockchip,camera-module-lens-name = "Largan"; 56*4882a593Smuzhiyun port { 57*4882a593Smuzhiyun gc2145_out: endpoint { 58*4882a593Smuzhiyun remote-endpoint = <&isp_dvp_in>; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun ov8858: ov8858@36 { 64*4882a593Smuzhiyun compatible = "ovti,ov8858"; 65*4882a593Smuzhiyun reg = <0x36>; 66*4882a593Smuzhiyun clocks = <&cru SCLK_VIP_OUT>; 67*4882a593Smuzhiyun clock-names = "xvclk"; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 70*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 71*4882a593Smuzhiyun rockchip,camera-module-name = "CameraKing"; 72*4882a593Smuzhiyun rockchip,camera-module-lens-name = "Largan-9569A2"; 73*4882a593Smuzhiyun /*power-gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; */ 74*4882a593Smuzhiyun pwdn-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; 75*4882a593Smuzhiyun port { 76*4882a593Smuzhiyun ov8858_out: endpoint { 77*4882a593Smuzhiyun remote-endpoint = <&th_mipi_in>; 78*4882a593Smuzhiyun data-lanes = <1 2>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun}; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun&mipi_phy_rx0 { 86*4882a593Smuzhiyun status = "okay"; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun ports { 89*4882a593Smuzhiyun #address-cells = <1>; 90*4882a593Smuzhiyun #size-cells = <0>; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun port@0 { 93*4882a593Smuzhiyun reg = <0>; 94*4882a593Smuzhiyun #address-cells = <1>; 95*4882a593Smuzhiyun #size-cells = <0>; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun th_mipi_in: endpoint@1 { 98*4882a593Smuzhiyun reg = <1>; 99*4882a593Smuzhiyun remote-endpoint = <&ov8858_out>; 100*4882a593Smuzhiyun data-lanes = <1 2>; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun port@1 { 105*4882a593Smuzhiyun reg = <1>; 106*4882a593Smuzhiyun #address-cells = <1>; 107*4882a593Smuzhiyun #size-cells = <0>; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun dphy_rx_out: endpoint@0 { 110*4882a593Smuzhiyun reg = <0>; 111*4882a593Smuzhiyun remote-endpoint = <&isp_mipi_in>; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun}; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun&pinctrl { 118*4882a593Smuzhiyun camera { 119*4882a593Smuzhiyun camera_pwr: camera-pwr { 120*4882a593Smuzhiyun rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun pcfg_pull_none_4ma: pcfg-pull-none-4ma { 125*4882a593Smuzhiyun bias-disable; 126*4882a593Smuzhiyun drive-strength = <4>; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun isp_pin { 130*4882a593Smuzhiyun isp_mipi: isp-mipi { 131*4882a593Smuzhiyun rockchip,pins = 132*4882a593Smuzhiyun /* cif_clkout */ 133*4882a593Smuzhiyun <2 RK_PB3 1 &pcfg_pull_none_4ma>; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun isp_dvp_d2d9: isp-d2d9 { 137*4882a593Smuzhiyun rockchip,pins = 138*4882a593Smuzhiyun /* cif_data2 ... cif_data9 */ 139*4882a593Smuzhiyun <2 RK_PA0 1 &pcfg_pull_down>, 140*4882a593Smuzhiyun <2 RK_PA1 1 &pcfg_pull_down>, 141*4882a593Smuzhiyun <2 RK_PA2 1 &pcfg_pull_down>, 142*4882a593Smuzhiyun <2 RK_PA3 1 &pcfg_pull_down>, 143*4882a593Smuzhiyun <2 RK_PA4 1 &pcfg_pull_down>, 144*4882a593Smuzhiyun <2 RK_PA5 1 &pcfg_pull_down>, 145*4882a593Smuzhiyun /* cif_sync, cif_href */ 146*4882a593Smuzhiyun <2 RK_PB0 1 &pcfg_pull_down>, 147*4882a593Smuzhiyun <2 RK_PB1 1 &pcfg_pull_down>, 148*4882a593Smuzhiyun /* cif_clkin */ 149*4882a593Smuzhiyun <2 RK_PB2 1 &pcfg_pull_down>; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun isp_dvp_d0d1: isp-d0d1 { 153*4882a593Smuzhiyun rockchip,pins = 154*4882a593Smuzhiyun /* cif_data0, cif_data1 */ 155*4882a593Smuzhiyun <2 RK_PB4 1 &pcfg_pull_down>, 156*4882a593Smuzhiyun <2 RK_PB5 1 &pcfg_pull_down>; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun}; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun&rkisp1 { 162*4882a593Smuzhiyun status = "okay"; 163*4882a593Smuzhiyun pinctrl-names = "default"; 164*4882a593Smuzhiyun pinctrl-0 = <&isp_dvp_d2d9 &isp_dvp_d0d1 &isp_mipi>; 165*4882a593Smuzhiyun port { 166*4882a593Smuzhiyun #address-cells = <1>; 167*4882a593Smuzhiyun #size-cells = <0>; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun isp_dvp_in: endpoint@1 { 170*4882a593Smuzhiyun reg = <1>; 171*4882a593Smuzhiyun remote-endpoint = <&gc2145_out>; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun isp_mipi_in: endpoint@0 { 175*4882a593Smuzhiyun reg = <0>; 176*4882a593Smuzhiyun remote-endpoint = <&dphy_rx_out>; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun}; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun&vopb { 183*4882a593Smuzhiyun assigned-clocks = <&cru DCLK_VOP0>; 184*4882a593Smuzhiyun assigned-clock-parents = <&cru PLL_CPLL>; 185*4882a593Smuzhiyun}; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun&vopl { 188*4882a593Smuzhiyun assigned-clocks = <&cru DCLK_VOP1>; 189*4882a593Smuzhiyun assigned-clock-parents = <&cru PLL_GPLL>; 190*4882a593Smuzhiyun}; 191