1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. 3 4#include <dt-bindings/clock/rk1808-cru.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/pinctrl/rockchip.h> 8#include <dt-bindings/power/rk1808-power.h> 9 10/ { 11 compatible = "rockchip,rk1808"; 12 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 aliases { 18 i2c0 = &i2c0; 19 i2c1 = &i2c1; 20 i2c2 = &i2c2; 21 i2c3 = &i2c3; 22 i2c4 = &i2c4; 23 i2c5 = &i2c5; 24 serial0 = &uart0; 25 serial1 = &uart1; 26 serial2 = &uart2; 27 serial3 = &uart3; 28 serial4 = &uart4; 29 serial5 = &uart5; 30 serial6 = &uart6; 31 serial7 = &uart7; 32 spi0 = &spi0; 33 spi1 = &spi1; 34 spi2 = &spi2; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 cpu0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a35", "arm,armv8"; 44 reg = <0x0 0x0>; 45 clocks = <&cru ARMCLK>; 46 }; 47 48 cpu1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a35", "arm,armv8"; 51 reg = <0x0 0x1>; 52 clocks = <&cru ARMCLK>; 53 }; 54 }; 55 56 arm-pmu { 57 compatible = "arm,cortex-a53-pmu"; 58 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 60 interrupt-affinity = <&cpu0>, <&cpu1>; 61 }; 62 63 dmc: dmc { 64 compatible = "rockchip,rk1808-dmc"; 65 }; 66 67 gmac_clkin: external-gmac-clock { 68 compatible = "fixed-clock"; 69 clock-frequency = <125000000>; 70 clock-output-names = "gmac_clkin"; 71 #clock-cells = <0>; 72 }; 73 74 timer { 75 compatible = "arm,armv8-timer"; 76 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 77 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 78 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 79 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 80 arm,no-tick-in-suspend; 81 }; 82 83 xin24m: xin24m { 84 compatible = "fixed-clock"; 85 clock-frequency = <24000000>; 86 clock-output-names = "xin24m"; 87 #clock-cells = <0>; 88 }; 89 90 xin32k: xin32k { 91 compatible = "fixed-clock"; 92 clock-frequency = <32768>; 93 clock-output-names = "xin32k"; 94 #clock-cells = <0>; 95 }; 96 97 usbdrd3: usb { 98 compatible = "rockchip,rk1808-dwc3"; 99 clocks = <&cru SCLK_USB3_OTG0_REF>, <&cru ACLK_USB3OTG>, 100 <&cru SCLK_USB3_OTG0_SUSPEND>; 101 clock-names = "ref_clk", "bus_clk", 102 "suspend_clk"; 103 #address-cells = <2>; 104 #size-cells = <2>; 105 ranges; 106 status = "disabled"; 107 108 usbdrd_dwc3: dwc3@fd000000 { 109 compatible = "snps,dwc3"; 110 reg = <0x0 0xfd000000 0x0 0x200000>; 111 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 112 dr_mode = "otg"; 113 phys = <&u2phy_otg>; 114 phy-names = "usb2-phy"; 115 phy_type = "utmi_wide"; 116 snps,dis_enblslpm_quirk; 117 snps,dis-u2-freeclk-exists-quirk; 118 snps,dis_u2_susphy_quirk; 119 snps,dis-del-phy-power-chg-quirk; 120 snps,tx-ipgap-linecheck-dis-quirk; 121 status = "disabled"; 122 }; 123 }; 124 125 grf: syscon@fe000000 { 126 compatible = "rockchip,rk1808-grf", "syscon", "simple-mfd"; 127 reg = <0x0 0xfe000000 0x0 0x1000>; 128 #address-cells = <1>; 129 #size-cells = <1>; 130 131 io_domains: io-domains { 132 compatible = "rockchip,rk1808-io-voltage-domain"; 133 status = "disabled"; 134 }; 135 136 rgb: rgb { 137 compatible = "rockchip,rk1808-rgb"; 138 status = "disabled"; 139 140 ports { 141 #address-cells = <1>; 142 #size-cells = <0>; 143 144 port@0 { 145 reg = <0>; 146 147 rgb_in_vop_lite: endpoint { 148 remote-endpoint = <&vop_lite_out_rgb>; 149 }; 150 }; 151 }; 152 }; 153 }; 154 155 usb2phy_grf: syscon@fe010000 { 156 compatible = "rockchip,rk1808-usb2phy-grf", "syscon", 157 "simple-mfd"; 158 reg = <0x0 0xfe010000 0x0 0x8000>; 159 #address-cells = <1>; 160 #size-cells = <1>; 161 162 u2phy: usb2-phy@100 { 163 compatible = "rockchip,rk1808-usb2phy"; 164 reg = <0x100 0x10>; 165 clocks = <&cru SCLK_USBPHY_REF>; 166 clock-names = "phyclk"; 167 #clock-cells = <0>; 168 assigned-clocks = <&cru USB480M>; 169 assigned-clock-parents = <&u2phy>; 170 clock-output-names = "usb480m_phy"; 171 status = "disabled"; 172 173 u2phy_host: host-port { 174 #phy-cells = <0>; 175 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 176 interrupt-names = "linestate"; 177 status = "disabled"; 178 }; 179 180 u2phy_otg: otg-port { 181 #phy-cells = <0>; 182 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 185 interrupt-names = "otg-bvalid", "otg-id", 186 "linestate"; 187 status = "disabled"; 188 }; 189 }; 190 }; 191 192 pmugrf: syscon@fe020000 { 193 compatible = "rockchip,rk1808-pmugrf", "syscon", "simple-mfd"; 194 reg = <0x0 0xfe020000 0x0 0x1000>; 195 #address-cells = <1>; 196 #size-cells = <1>; 197 198 pmu_io_domains: io-domains { 199 compatible = "rockchip,rk1808-pmu-io-voltage-domain"; 200 status = "disabled"; 201 }; 202 }; 203 204 psci: psci { 205 compatible = "arm,psci-1.0"; 206 method = "smc"; 207 }; 208 209 qos_npu: qos@fe850000 { 210 compatible = "syscon"; 211 reg = <0x0 0xfe850000 0x0 0x20>; 212 }; 213 214 qos_pcie: qos@fe880000 { 215 compatible = "syscon"; 216 reg = <0x0 0xfe880000 0x0 0x20>; 217 }; 218 219 qos_isp: qos@fe8a0000 { 220 compatible = "syscon"; 221 reg = <0x0 0xfe8a0000 0x0 0x20>; 222 }; 223 224 qos_rga_rd: qos@fe8a0080 { 225 compatible = "syscon"; 226 reg = <0x0 0xfe8a0080 0x0 0x20>; 227 }; 228 229 qos_rga_wr: qos@fe8a0100 { 230 compatible = "syscon"; 231 reg = <0x0 0xfe8a0100 0x0 0x20>; 232 }; 233 234 qos_vip: qos@fe8a0180 { 235 compatible = "syscon"; 236 reg = <0x0 0xfe8a0180 0x0 0x20>; 237 }; 238 239 qos_vop_dma: qos@fe8b0000 { 240 compatible = "syscon"; 241 reg = <0x0 0xfe8b0000 0x0 0x20>; 242 }; 243 244 qos_vop_lite: qos@fe8b0080 { 245 compatible = "syscon"; 246 reg = <0x0 0xfe8b0080 0x0 0x20>; 247 }; 248 249 qos_vpu: qos@fe8cc000 { 250 compatible = "syscon"; 251 reg = <0x0 0xfe8c000 0x0 0x20>; 252 }; 253 254 sram: sram@fec00000 { 255 compatible = "mmio-sram"; 256 reg = <0x0 0xfec00000 0x0 0x200000>; 257 #address-cells = <1>; 258 #size-cells = <1>; 259 ranges = <0 0x0 0xfec00000 0x200000>; 260 /* reserved for ddr dvfs and system suspend/resume */ 261 ddr-sram@0 { 262 reg = <0x0 0x8000>; 263 }; 264 /* reserved for vad audio buffer */ 265 vad_sram: vad-sram@1c0000 { 266 reg = <0x1c0000 0x40000>; 267 }; 268 }; 269 270 gic: interrupt-controller@ff100000 { 271 compatible = "arm,gic-v3"; 272 #interrupt-cells = <3>; 273 #address-cells = <2>; 274 #size-cells = <2>; 275 ranges; 276 interrupt-controller; 277 278 reg = <0x0 0xff100000 0 0x10000>, /* GICD */ 279 <0x0 0xff140000 0 0xc0000>, /* GICR */ 280 <0x0 0xff300000 0 0x10000>, /* GICC */ 281 <0x0 0xff310000 0 0x10000>, /* GICH */ 282 <0x0 0xff320000 0 0x10000>; /* GICV */ 283 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 284 its: interrupt-controller@ff120000 { 285 compatible = "arm,gic-v3-its"; 286 msi-controller; 287 reg = <0x0 0xff120000 0x0 0x20000>; 288 }; 289 }; 290 291 cru: clock-controller@ff350000 { 292 compatible = "rockchip,rk1808-cru"; 293 reg = <0x0 0xff350000 0x0 0x5000>; 294 rockchip,grf = <&grf>; 295 #clock-cells = <1>; 296 #reset-cells = <1>; 297 298 assigned-clocks = 299 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 300 <&cru PLL_PPLL>, <&cru ARMCLK>, 301 <&cru MSCLK_PERI>, <&cru LSCLK_PERI>, 302 <&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>, 303 <&cru LSCLK_BUS_PRE>; 304 assigned-clock-rates = 305 <1200000000>, <1000000000>, 306 <416000000>, <816000000>, 307 <200000000>, <100000000>, 308 <300000000>, <200000000>, 309 <100000000>; 310 }; 311 312 mipi_dphy: mipi-dphy@ff370000 { 313 compatible = "rockchip,rk1808-mipi-dphy"; 314 reg = <0x0 0xff370000 0x0 0x500>; 315 clocks = <&cru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 316 clock-names = "ref", "pclk"; 317 clock-output-names = "mipi_dphy_pll"; 318 #clock-cells = <0>; 319 resets = <&cru SRST_MIPIDSIPHY_P>; 320 reset-names = "apb"; 321 #phy-cells = <0>; 322 rockchip,grf = <&grf>; 323 status = "disabled"; 324 }; 325 326 tsadc: tsadc@ff3a0000 { 327 compatible = "rockchip,rk1808-tsadc"; 328 reg = <0x0 0xff3a0000 0x0 0x100>; 329 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 330 rockchip,grf = <&grf>; 331 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 332 clock-names = "tsadc", "apb_pclk"; 333 assigned-clocks = <&cru SCLK_TSADC>; 334 assigned-clock-rates = <50000>; 335 resets = <&cru SRST_TSADC>; 336 reset-names = "tsadc-apb"; 337 #thermal-sensor-cells = <1>; 338 rockchip,hw-tshut-temp = <120000>; 339 status = "disabled"; 340 }; 341 342 pwm0: pwm@ff3d0000 { 343 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 344 reg = <0x0 0xff3d0000 0x0 0x10>; 345 #pwm-cells = <3>; 346 pinctrl-names = "active"; 347 pinctrl-0 = <&pwm0_pin>; 348 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 349 clock-names = "pwm", "pclk"; 350 status = "disabled"; 351 }; 352 353 pwm1: pwm@ff3d0010 { 354 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 355 reg = <0x0 0xff3d0010 0x0 0x10>; 356 #pwm-cells = <3>; 357 pinctrl-names = "active"; 358 pinctrl-0 = <&pwm1_pin>; 359 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 360 clock-names = "pwm", "pclk"; 361 status = "disabled"; 362 }; 363 364 pwm2: pwm@ff3d0020 { 365 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 366 reg = <0x0 0xff3d0020 0x0 0x10>; 367 #pwm-cells = <3>; 368 pinctrl-names = "active"; 369 pinctrl-0 = <&pwm2_pin>; 370 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 371 clock-names = "pwm", "pclk"; 372 status = "disabled"; 373 }; 374 375 pwm3: pwm@ff3d0030 { 376 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 377 reg = <0x0 0xff3d0030 0x0 0x10>; 378 #pwm-cells = <3>; 379 pinctrl-names = "active"; 380 pinctrl-0 = <&pwm3_pin>; 381 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 382 clock-names = "pwm", "pclk"; 383 status = "disabled"; 384 }; 385 386 pwm4: pwm@ff3d8000 { 387 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 388 reg = <0x0 0xff3d8000 0x0 0x10>; 389 #pwm-cells = <3>; 390 pinctrl-names = "active"; 391 pinctrl-0 = <&pwm4_pin>; 392 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 393 clock-names = "pwm", "pclk"; 394 status = "disabled"; 395 }; 396 397 pwm5: pwm@ff3d8010 { 398 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 399 reg = <0x0 0xff3d8010 0x0 0x10>; 400 #pwm-cells = <3>; 401 pinctrl-names = "active"; 402 pinctrl-0 = <&pwm5_pin>; 403 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 404 clock-names = "pwm", "pclk"; 405 status = "disabled"; 406 }; 407 408 pwm6: pwm@ff3d8020 { 409 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 410 reg = <0x0 0xff3d8020 0x0 0x10>; 411 #pwm-cells = <3>; 412 pinctrl-names = "active"; 413 pinctrl-0 = <&pwm6_pin>; 414 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 415 clock-names = "pwm", "pclk"; 416 status = "disabled"; 417 }; 418 419 pwm7: pwm@ff3d8030 { 420 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 421 reg = <0x0 0xff3d8030 0x0 0x10>; 422 #pwm-cells = <3>; 423 pinctrl-names = "active"; 424 pinctrl-0 = <&pwm7_pin>; 425 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 426 clock-names = "pwm", "pclk"; 427 status = "disabled"; 428 }; 429 430 pmu: power-management@ff3e0000 { 431 compatible = "rockchip,rk1808-pmu", "syscon", "simple-mfd"; 432 reg = <0x0 0xff3e0000 0x0 0x1000>; 433 434 power: power-controller { 435 compatible = "rockchip,rk1808-power-controller"; 436 #power-domain-cells = <1>; 437 #address-cells = <1>; 438 #size-cells = <0>; 439 status = "disabled"; 440 441 /* These power domains are grouped by VD_NPU */ 442 pd_npu@RK1808_VD_NPU { 443 reg = <RK1808_VD_NPU>; 444 clocks = <&cru SCLK_NPU>, 445 <&cru ACLK_NPU>, 446 <&cru HCLK_NPU>; 447 pm_qos = <&qos_npu>; 448 }; 449 450 /* These power domains are grouped by VD_LOGIC */ 451 pd_pcie@RK1808_PD_PCIE { 452 reg = <RK1808_PD_PCIE>; 453 clocks = <&cru HSCLK_PCIE>, 454 <&cru LSCLK_PCIE>, 455 <&cru ACLK_PCIE>, 456 <&cru ACLK_PCIE_MST>, 457 <&cru ACLK_PCIE_SLV>, 458 <&cru PCLK_PCIE>, 459 <&cru SCLK_PCIE_AUX>; 460 pm_qos = <&qos_pcie>; 461 }; 462 pd_vpu@RK1808_PD_VPU { 463 reg = <RK1808_PD_VPU>; 464 clocks = <&cru ACLK_VPU>, 465 <&cru HCLK_VPU>; 466 pm_qos = <&qos_vpu>; 467 }; 468 pd_vio@RK1808_PD_VIO { 469 reg = <RK1808_PD_VIO>; 470 clocks = <&cru HSCLK_VIO>, 471 <&cru LSCLK_VIO>, 472 <&cru ACLK_VOPRAW>, 473 <&cru HCLK_VOPRAW>, 474 <&cru ACLK_VOPLITE>, 475 <&cru HCLK_VOPLITE>, 476 <&cru PCLK_DSI_TX>, 477 <&cru PCLK_CSI_TX>, 478 <&cru ACLK_RGA>, 479 <&cru HCLK_RGA>, 480 <&cru ACLK_ISP>, 481 <&cru HCLK_ISP>, 482 <&cru ACLK_CIF>, 483 <&cru HCLK_CIF>, 484 <&cru PCLK_CSI2HOST>, 485 <&cru DCLK_VOPRAW>, 486 <&cru DCLK_VOPLITE>; 487 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 488 <&qos_isp>, <&qos_vip>, 489 <&qos_vop_dma>, <&qos_vop_lite>; 490 }; 491 }; 492 }; 493 494 i2c0: i2c@ff410000 { 495 compatible = "rockchip,rk3399-i2c"; 496 reg = <0x0 0xff410000 0x0 0x1000>; 497 clocks = <&cru SCLK_PMU_I2C0>, <&cru PCLK_I2C0_PMU>; 498 clock-names = "i2c", "pclk"; 499 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 500 pinctrl-names = "default"; 501 pinctrl-0 = <&i2c0_xfer>; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 status = "disabled"; 505 }; 506 507 dmac: dmac@ff4e0000 { 508 compatible = "arm,pl330", "arm,primecell"; 509 reg = <0x0 0xff4e0000 0x0 0x4000>; 510 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&cru ACLK_DMAC>; 512 clock-names = "apb_pclk"; 513 #dma-cells = <1>; 514 peripherals-req-type-burst; 515 }; 516 517 uart0: serial@ff430000 { 518 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 519 reg = <0x0 0xff430000 0x0 0x100>; 520 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&cru SCLK_UART0_PMU>, <&cru PCLK_UART0_PMU>; 522 clock-names = "baudclk", "apb_pclk"; 523 reg-shift = <2>; 524 reg-io-width = <4>; 525 dmas = <&dmac 0>, <&dmac 1>; 526 dma-names = "tx", "rx"; 527 pinctrl-names = "default"; 528 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 529 status = "disabled"; 530 }; 531 532 i2c1: i2c@ff500000 { 533 compatible = "rockchip,rk3399-i2c"; 534 reg = <0x0 0xff500000 0x0 0x1000>; 535 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 536 clock-names = "i2c", "pclk"; 537 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 538 pinctrl-names = "default"; 539 pinctrl-0 = <&i2c1_xfer>; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 status = "disabled"; 543 }; 544 545 i2c2: i2c@ff504000 { 546 compatible = "rockchip,rk3399-i2c"; 547 reg = <0x0 0xff504000 0x0 0x1000>; 548 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 549 clock-names = "i2c", "pclk"; 550 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 551 pinctrl-names = "default"; 552 pinctrl-0 = <&i2c2m0_xfer>; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 status = "disabled"; 556 }; 557 558 i2c3: i2c@ff508000 { 559 compatible = "rockchip,rk3399-i2c"; 560 reg = <0x0 0xff508000 0x0 0x1000>; 561 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 562 clock-names = "i2c", "pclk"; 563 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 564 pinctrl-names = "default"; 565 pinctrl-0 = <&i2c3_xfer>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 status = "disabled"; 569 }; 570 571 i2c4: i2c@ff50c000 { 572 compatible = "rockchip,rk3399-i2c"; 573 reg = <0x0 0xff50c000 0x0 0x1000>; 574 clocks = <&cru SCLK_I2C4>, <&cru PCLK_I2C4>; 575 clock-names = "i2c", "pclk"; 576 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 577 pinctrl-names = "default"; 578 pinctrl-0 = <&i2c4_xfer>; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 status = "disabled"; 582 }; 583 584 i2c5: i2c@ff510000 { 585 compatible = "rockchip,rk3399-i2c"; 586 reg = <0x0 0xff100000 0x0 0x1000>; 587 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 588 clock-names = "i2c", "pclk"; 589 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 590 pinctrl-names = "default"; 591 pinctrl-0 = <&i2c5_xfer>; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 status = "disabled"; 595 }; 596 597 spi0: spi@ff520000 { 598 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; 599 reg = <0x0 0xff520000 0x0 0x1000>; 600 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 601 #address-cells = <1>; 602 #size-cells = <0>; 603 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 604 clock-names = "spiclk", "apb_pclk"; 605 dmas = <&dmac 10>, <&dmac 11>; 606 dma-names = "tx", "rx"; 607 pinctrl-names = "default", "high_speed"; 608 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 609 pinctrl-1 = <&spi0_clk_hs &spi0_csn &spi0_miso_hs &spi0_mosi_hs>; 610 status = "disabled"; 611 }; 612 613 spi1: spi@ff530000 { 614 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; 615 reg = <0x0 0xff530000 0x0 0x1000>; 616 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 617 #address-cells = <1>; 618 #size-cells = <0>; 619 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 620 clock-names = "spiclk", "apb_pclk"; 621 dmas = <&dmac 12>, <&dmac 13>; 622 dma-names = "tx", "rx"; 623 pinctrl-names = "default", "high_speed"; 624 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 625 pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_csn1 &spi1_miso_hs &spi1_mosi_hs>; 626 status = "disabled"; 627 }; 628 629 uart1: serial@ff540000 { 630 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 631 reg = <0x0 0xff540000 0x0 0x100>; 632 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 634 clock-names = "baudclk", "apb_pclk"; 635 reg-shift = <2>; 636 reg-io-width = <4>; 637 dmas = <&dmac 2>, <&dmac 3>; 638 dma-names = "tx", "rx"; 639 pinctrl-names = "default"; 640 pinctrl-0 = <&uart1m0_xfer &uart1_cts &uart1_rts>; 641 status = "disabled"; 642 }; 643 644 uart2: serial@ff550000 { 645 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 646 reg = <0x0 0xff550000 0x0 0x100>; 647 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 649 clock-names = "baudclk", "apb_pclk"; 650 reg-shift = <2>; 651 reg-io-width = <4>; 652 dmas = <&dmac 4>, <&dmac 5>; 653 dma-names = "tx", "rx"; 654 pinctrl-names = "default"; 655 pinctrl-0 = <&uart2m0_xfer>; 656 status = "disabled"; 657 }; 658 659 uart3: serial@ff560000 { 660 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 661 reg = <0x0 0xff560000 0x0 0x100>; 662 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 664 clock-names = "baudclk", "apb_pclk"; 665 reg-shift = <2>; 666 reg-io-width = <4>; 667 dmas = <&dmac 6>, <&dmac 7>; 668 dma-names = "tx", "rx"; 669 pinctrl-names = "default"; 670 pinctrl-0 = <&uart3m0_xfer &uart3_ctsm0 &uart3_rtsm0>; 671 status = "disabled"; 672 }; 673 674 uart4: serial@ff570000 { 675 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 676 reg = <0x0 0xff570000 0x0 0x100>; 677 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 679 clock-names = "baudclk", "apb_pclk"; 680 reg-shift = <2>; 681 reg-io-width = <4>; 682 dmas = <&dmac 8>, <&dmac 9>; 683 dma-names = "tx", "rx"; 684 pinctrl-names = "default"; 685 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 686 status = "disabled"; 687 }; 688 689 spi2: spi@ff580000 { 690 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; 691 reg = <0x0 0xff580000 0x0 0x1000>; 692 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 693 #address-cells = <1>; 694 #size-cells = <0>; 695 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 696 clock-names = "spiclk", "apb_pclk"; 697 dmas = <&dmac 14>, <&dmac 15>; 698 dma-names = "tx", "rx"; 699 pinctrl-names = "default", "high_speed"; 700 pinctrl-0 = <&spi2m0_clk &spi2m0_csn &spi2m0_miso &spi2m0_mosi>; 701 pinctrl-1 = <&spi2m0_clk_hs &spi2m0_csn &spi2m0_miso_hs &spi2m0_mosi_hs>; 702 status = "disabled"; 703 }; 704 705 uart5: serial@ff5a0000 { 706 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 707 reg = <0x0 0xff5a0000 0x0 0x100>; 708 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 710 clock-names = "baudclk", "apb_pclk"; 711 reg-shift = <2>; 712 reg-io-width = <4>; 713 dmas = <&dmac 25>, <&dmac 26>; 714 dma-names = "tx", "rx"; 715 pinctrl-names = "default"; 716 pinctrl-0 = <&uart5_xfer>; 717 status = "disabled"; 718 }; 719 720 uart6: serial@ff5b0000 { 721 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 722 reg = <0x0 0xff5b0000 0x0 0x100>; 723 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 724 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 725 clock-names = "baudclk", "apb_pclk"; 726 reg-shift = <2>; 727 reg-io-width = <4>; 728 dmas = <&dmac 27>, <&dmac 28>; 729 dma-names = "tx", "rx"; 730 pinctrl-names = "default"; 731 pinctrl-0 = <&uart6_xfer>; 732 status = "disabled"; 733 }; 734 735 uart7: serial@ff5c0000 { 736 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 737 reg = <0x0 0xff5c0000 0x0 0x100>; 738 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 740 clock-names = "baudclk", "apb_pclk"; 741 reg-shift = <2>; 742 reg-io-width = <4>; 743 dmas = <&dmac 29>, <&dmac 30>; 744 dma-names = "tx", "rx"; 745 pinctrl-names = "default"; 746 pinctrl-0 = <&uart7_xfer>; 747 status = "disabled"; 748 }; 749 750 vop_lite: vop@ffb00000 { 751 compatible = "rockchip,rk1808-vop-lit"; 752 reg = <0x0 0xffb00000 0x0 0x200>; 753 reg-names = "regs"; 754 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&cru ACLK_VOPLITE>, <&cru DCLK_VOPLITE>, 756 <&cru HCLK_VOPLITE>; 757 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 758 power-domains = <&power RK1808_PD_VIO>; 759 iommus = <&vopl_mmu>; 760 status = "disabled"; 761 762 vop_lite_out: port { 763 #address-cells = <1>; 764 #size-cells = <0>; 765 766 vop_lite_out_dsi: endpoint@0 { 767 reg = <0>; 768 remote-endpoint = <&dsi_in_vop_lite>; 769 }; 770 771 vop_lite_out_rgb: endpoint@1 { 772 reg = <1>; 773 remote-endpoint = <&rgb_in_vop_lite>; 774 }; 775 }; 776 }; 777 778 vopl_mmu: iommu@ffb00f00 { 779 compatible = "rockchip,iommu"; 780 reg = <0x0 0xffb00f00 0x0 0x100>; 781 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 782 interrupt-names = "vopl_mmu"; 783 clocks = <&cru ACLK_VOPLITE>, <&cru HCLK_VOPLITE>; 784 clock-names = "aclk", "hclk"; 785 power-domains = <&power RK1808_PD_VIO>; 786 #iommu-cells = <0>; 787 status = "disabled"; 788 }; 789 790 vop_raw: vop@ffb40000 { 791 compatible = "rockchip,rk1808-vop-raw"; 792 reg = <0x0 0xffb40000 0x0 0x500>; 793 reg-names = "regs"; 794 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&cru ACLK_VOPRAW>, <&cru DCLK_VOPRAW>, 796 <&cru HCLK_VOPRAW>; 797 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 798 power-domains = <&power RK1808_PD_VIO>; 799 iommus = <&vopr_mmu>; 800 status = "disabled"; 801 802 vop_raw_out: port { 803 #address-cells = <1>; 804 #size-cells = <0>; 805 806 vop_raw_out_csi: endpoint@0 { 807 reg = <0>; 808 remote-endpoint = <&csi_in_vop_raw>; 809 }; 810 }; 811 }; 812 813 vopr_mmu: iommu@ffb40f00 { 814 compatible = "rockchip,iommu"; 815 reg = <0x0 0xffb40f00 0x0 0x100>; 816 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 817 interrupt-names = "vopr_mmu"; 818 clocks = <&cru ACLK_VOPRAW>, <&cru HCLK_VOPRAW>; 819 clock-names = "aclk", "hclk"; 820 power-domains = <&power RK1808_PD_VIO>; 821 #iommu-cells = <0>; 822 status = "disabled"; 823 }; 824 825 pwm8: pwm@ff5d0000 { 826 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 827 reg = <0x0 0xff5d0000 0x0 0x10>; 828 #pwm-cells = <3>; 829 pinctrl-names = "active"; 830 pinctrl-0 = <&pwm8_pin>; 831 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 832 clock-names = "pwm", "pclk"; 833 status = "disabled"; 834 }; 835 836 pwm9: pwm@fff5d0010 { 837 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 838 reg = <0x0 0xff5d0010 0x0 0x10>; 839 #pwm-cells = <3>; 840 pinctrl-names = "active"; 841 pinctrl-0 = <&pwm9_pin>; 842 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 843 clock-names = "pwm", "pclk"; 844 status = "disabled"; 845 }; 846 847 pwm10: pwm@ff5d0020 { 848 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 849 reg = <0x0 0xff5d0020 0x0 0x10>; 850 #pwm-cells = <3>; 851 pinctrl-names = "active"; 852 pinctrl-0 = <&pwm10_pin>; 853 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 854 clock-names = "pwm", "pclk"; 855 status = "disabled"; 856 }; 857 858 pwm11: pwm@ff5d0030 { 859 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 860 reg = <0x0 0xff5d0030 0x0 0x10>; 861 #pwm-cells = <3>; 862 pinctrl-names = "active"; 863 pinctrl-0 = <&pwm11_pin>; 864 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 865 clock-names = "pwm", "pclk"; 866 status = "disabled"; 867 }; 868 869 crypto: crypto@ff630000 { 870 compatible = "rockchip,rk1808-crypto"; 871 reg = <0x0 0xff630000 0x0 0x10000>; 872 clock-names = "sclk_crypto", "sclk_crypto_apk"; 873 clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>; 874 clock-frequency = <200000000>, <300000000>; 875 status = "disabled"; 876 }; 877 878 i2s0: i2s@ff7e0000 { 879 compatible = "rockchip,rk1808-i2s-tdm"; 880 reg = <0x0 0xff7e0000 0x0 0x1000>; 881 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 882 clocks = <&cru SCLK_I2S0_8CH_TX>, <&cru SCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 883 clock-names = "mclk_tx", "mclk_rx", "hclk"; 884 dmas = <&dmac 16>, <&dmac 17>; 885 dma-names = "tx", "rx"; 886 resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>; 887 reset-names = "tx-m", "rx-m"; 888 rockchip,cru = <&cru>; 889 pinctrl-names = "default"; 890 pinctrl-0 = <&i2s0_8ch_sclktx 891 &i2s0_8ch_sclkrx 892 &i2s0_8ch_lrcktx 893 &i2s0_8ch_lrckrx 894 &i2s0_8ch_sdi0 895 &i2s0_8ch_sdi1 896 &i2s0_8ch_sdi2 897 &i2s0_8ch_sdi3 898 &i2s0_8ch_sdo0 899 &i2s0_8ch_sdo1 900 &i2s0_8ch_sdo2 901 &i2s0_8ch_sdo3 902 &i2s0_8ch_mclk>; 903 status = "disabled"; 904 }; 905 906 i2s1: i2s@ff7f0000 { 907 compatible = "rockchip,rk1808-i2s", "rockchip,rk3066-i2s"; 908 reg = <0x0 0xff7f0000 0x0 0x1000>; 909 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 910 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; 911 clock-names = "i2s_clk", "i2s_hclk"; 912 dmas = <&dmac 18>, <&dmac 19>; 913 dma-names = "tx", "rx"; 914 pinctrl-names = "default"; 915 pinctrl-0 = <&i2s1_2ch_sclk 916 &i2s1_2ch_lrck 917 &i2s1_2ch_sdi 918 &i2s1_2ch_sdo>; 919 status = "disabled"; 920 }; 921 922 pdm: pdm@ff800000 { 923 compatible = "rockchip,rk1808-pdm", "rockchip,pdm"; 924 reg = <0x0 0xff800000 0x0 0x1000>; 925 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 926 clock-names = "pdm_clk", "pdm_hclk"; 927 dmas = <&dmac 24>; 928 dma-names = "rx"; 929 resets = <&cru SRST_PDM>; 930 reset-names = "pdm-m"; 931 pinctrl-names = "default"; 932 pinctrl-0 = <&pdm_clk 933 &pdm_clk1 934 &pdm_sdi0 935 &pdm_sdi1 936 &pdm_sdi2 937 &pdm_sdi3>; 938 status = "disabled"; 939 }; 940 941 vad: vad@ff810000 { 942 compatible = "rockchip,rk1808-vad"; 943 reg = <0x0 0xff810000 0x0 0x10000>; 944 reg-names = "vad"; 945 clocks = <&cru HCLK_VAD>; 946 clock-names = "hclk"; 947 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 948 rockchip,audio-sram = <&vad_sram>; 949 rockchip,audio-src = <0>; 950 rockchip,det-channel = <0>; 951 rockchip,mode = <1>; 952 status = "disabled"; 953 }; 954 955 csi_tx: csi@ffb20000 { 956 compatible = "rockchip,rk1808-mipi-csi"; 957 reg = <0x0 0xffb20000 0x0 0x500>; 958 reg-names = "csi_regs"; 959 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&cru PCLK_CSI_TX>, <&mipi_dphy>; 961 clock-names = "pclk", "hs_clk"; 962 resets = <&cru SRST_CSITX_P>; 963 reset-names = "apb"; 964 phys = <&mipi_dphy>; 965 phy-names = "mipi_dphy"; 966 power-domains = <&power RK1808_PD_VIO>; 967 rockchip,grf = <&grf>; 968 status = "disabled"; 969 970 ports { 971 #address-cells = <1>; 972 #size-cells = <0>; 973 974 port { 975 csi_in_vop_raw: endpoint { 976 remote-endpoint = <&vop_raw_out_csi>; 977 }; 978 }; 979 }; 980 }; 981 982 dsi: dsi@ffb30000 { 983 compatible = "rockchip,rk1808-mipi-dsi"; 984 reg = <0x0 0xffb30000 0x0 0x500>; 985 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 986 clocks = <&cru PCLK_DSI_TX>, <&mipi_dphy>; 987 clock-names = "pclk", "hs_clk"; 988 resets = <&cru SRST_MIPIDSI_HOST_P>; 989 reset-names = "apb"; 990 phys = <&mipi_dphy>; 991 phy-names = "mipi_dphy"; 992 power-domains = <&power RK1808_PD_VIO>; 993 rockchip,grf = <&grf>; 994 #address-cells = <1>; 995 #size-cells = <0>; 996 status = "disabled"; 997 998 ports { 999 port { 1000 dsi_in_vop_lite: endpoint { 1001 remote-endpoint = <&vop_lite_out_dsi>; 1002 }; 1003 }; 1004 }; 1005 }; 1006 1007 sfc: sfc@ffc50000 { 1008 compatible = "rockchip,rksfc","rockchip,sfc"; 1009 reg = <0x0 0xffc50000 0x0 0x4000>; 1010 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1012 clock-names = "clk_sfc", "hclk_sfc"; 1013 status = "disabled"; 1014 }; 1015 1016 sdio: dwmmc@ffc60000 { 1017 compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; 1018 reg = <0x0 0xffc60000 0x0 0x4000>; 1019 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 1020 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1021 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 1022 max-frequency = <150000000>; 1023 fifo-depth = <0x100>; 1024 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1025 pinctrl-names = "default"; 1026 pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; 1027 status = "disabled"; 1028 }; 1029 1030 npu: npu@ffbc0000 { 1031 compatible = "rockchip,npu"; 1032 reg = <0x0 0xffbc0000 0x0 0x1000>; 1033 clocks = <&cru SCLK_NPU>, <&cru HCLK_NPU>; 1034 clock-names = "sclk_npu", "hclk_npu"; 1035 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1036 status = "disabled"; 1037 }; 1038 1039 saradc: saradc@ff3c0000 { 1040 compatible = "rockchip,rk1808-saradc", "rockchip,rk3399-saradc"; 1041 reg = <0x0 0xff3c0000 0x0 0x100>; 1042 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1043 #io-channel-cells = <1>; 1044 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 1045 clock-names = "saradc", "apb_pclk"; 1046 resets = <&cru SRST_SARADC_P>; 1047 reset-names = "saradc-apb"; 1048 status = "disabled"; 1049 }; 1050 1051 sdmmc: dwmmc@ffcf0000 { 1052 compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; 1053 reg = <0x0 0xffcf0000 0x0 0x4000>; 1054 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 1055 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1056 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 1057 max-frequency = <150000000>; 1058 fifo-depth = <0x100>; 1059 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1060 pinctrl-names = "default"; 1061 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd>; 1062 status = "disabled"; 1063 }; 1064 1065 emmc: dwmmc@ffd00000 { 1066 compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; 1067 reg = <0x0 0xffd00000 0x0 0x4000>; 1068 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 1069 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 1070 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 1071 max-frequency = <150000000>; 1072 fifo-depth = <0x100>; 1073 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1074 status = "disabled"; 1075 }; 1076 1077 usb_host0_ehci: usb@ffd80000 { 1078 compatible = "generic-ehci"; 1079 reg = <0x0 0xffd80000 0x0 0x10000>; 1080 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1081 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 1082 <&u2phy>; 1083 clock-names = "usbhost", "arbiter", "utmi"; 1084 phys = <&u2phy_host>; 1085 phy-names = "usb"; 1086 status = "disabled"; 1087 }; 1088 1089 usb_host0_ohci: usb@ffd90000 { 1090 compatible = "generic-ohci"; 1091 reg = <0x0 0xffd90000 0x0 0x10000>; 1092 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1093 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 1094 <&u2phy>; 1095 clock-names = "usbhost", "arbiter", "utmi"; 1096 phys = <&u2phy_host>; 1097 phy-names = "usb"; 1098 status = "disabled"; 1099 }; 1100 1101 gmac: ethernet@ffdd0000 { 1102 compatible = "rockchip,rk1808-gmac"; 1103 reg = <0x0 0xffdd0000 0x0 0x10000>; 1104 rockchip,grf = <&grf>; 1105 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1106 interrupt-names = "macirq"; 1107 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 1108 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_GMAC_REF>, 1109 <&cru SCLK_GMAC_REFOUT>, <&cru ACLK_GMAC>, 1110 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RGMII_SPEED>; 1111 clock-names = "stmmaceth", "mac_clk_rx", 1112 "mac_clk_tx", "clk_mac_ref", 1113 "clk_mac_refout", "aclk_mac", 1114 "pclk_mac", "clk_mac_speed"; 1115 phy-mode = "rgmii"; 1116 pinctrl-names = "default"; 1117 pinctrl-0 = <&rgmii_pins>; 1118 resets = <&cru SRST_GAMC_A>; 1119 reset-names = "stmmaceth"; 1120 /* power-domains = <&power RK1808_PD_GMAC>; */ 1121 status = "disabled"; 1122 }; 1123 1124 pinctrl: pinctrl { 1125 compatible = "rockchip,rk1808-pinctrl"; 1126 rockchip,grf = <&grf>; 1127 rockchip,pmu = <&pmugrf>; 1128 #address-cells = <2>; 1129 #size-cells = <2>; 1130 ranges; 1131 1132 gpio0: gpio0@ff4c0000 { 1133 compatible = "rockchip,gpio-bank"; 1134 reg = <0x0 0xff4c0000 0x0 0x100>; 1135 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1136 clocks = <&cru PCLK_GPIO0_PMU>, <&cru DBCLK_PMU_GPIO0>; 1137 gpio-controller; 1138 #gpio-cells = <2>; 1139 1140 interrupt-controller; 1141 #interrupt-cells = <2>; 1142 }; 1143 1144 gpio1: gpio1@ff690000 { 1145 compatible = "rockchip,gpio-bank"; 1146 reg = <0x0 0xff690000 0x0 0x100>; 1147 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1148 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1149 gpio-controller; 1150 #gpio-cells = <2>; 1151 1152 interrupt-controller; 1153 #interrupt-cells = <2>; 1154 }; 1155 1156 gpio2: gpio2@ff6a0000 { 1157 compatible = "rockchip,gpio-bank"; 1158 reg = <0x0 0xff6a0000 0x0 0x100>; 1159 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1160 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1161 gpio-controller; 1162 #gpio-cells = <2>; 1163 1164 interrupt-controller; 1165 #interrupt-cells = <2>; 1166 }; 1167 1168 gpio3: gpio3@ff6b0000 { 1169 compatible = "rockchip,gpio-bank"; 1170 reg = <0x0 0xff6b0000 0x0 0x100>; 1171 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1172 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1173 gpio-controller; 1174 #gpio-cells = <2>; 1175 1176 interrupt-controller; 1177 #interrupt-cells = <2>; 1178 }; 1179 1180 gpio4: gpio4@ff6c0000 { 1181 compatible = "rockchip,gpio-bank"; 1182 reg = <0x0 0xff6c0000 0x0 0x100>; 1183 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1184 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1185 gpio-controller; 1186 #gpio-cells = <2>; 1187 1188 interrupt-controller; 1189 #interrupt-cells = <2>; 1190 }; 1191 1192 pcfg_pull_up: pcfg-pull-up { 1193 bias-pull-up; 1194 }; 1195 1196 pcfg_pull_down: pcfg-pull-down { 1197 bias-pull-down; 1198 }; 1199 1200 pcfg_pull_none: pcfg-pull-none { 1201 bias-disable; 1202 }; 1203 1204 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1205 bias-disable; 1206 drive-strength = <2>; 1207 }; 1208 1209 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1210 bias-pull-up; 1211 drive-strength = <2>; 1212 }; 1213 1214 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1215 bias-pull-up; 1216 drive-strength = <4>; 1217 }; 1218 1219 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1220 bias-disable; 1221 drive-strength = <4>; 1222 }; 1223 1224 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1225 bias-pull-down; 1226 drive-strength = <4>; 1227 }; 1228 1229 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1230 bias-disable; 1231 drive-strength = <8>; 1232 }; 1233 1234 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1235 bias-pull-up; 1236 drive-strength = <8>; 1237 }; 1238 1239 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1240 bias-disable; 1241 drive-strength = <12>; 1242 }; 1243 1244 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1245 bias-pull-up; 1246 drive-strength = <12>; 1247 }; 1248 1249 pcfg_pull_none_smt: pcfg-pull-none-smt { 1250 bias-disable; 1251 input-schmitt-enable; 1252 }; 1253 1254 pcfg_output_high: pcfg-output-high { 1255 output-high; 1256 }; 1257 1258 pcfg_output_low: pcfg-output-low { 1259 output-low; 1260 }; 1261 1262 pcfg_input_high: pcfg-input-high { 1263 bias-pull-up; 1264 input-enable; 1265 }; 1266 1267 pcfg_input: pcfg-input { 1268 input-enable; 1269 }; 1270 1271 emmc { 1272 emmc_clk: emmc-clk { 1273 rockchip,pins = 1274 /* emmc_clkout */ 1275 <1 RK_PB1 1 &pcfg_pull_none>; 1276 }; 1277 1278 emmc_rstnout: emmc-rstnout { 1279 rockchip,pins = 1280 /* emmc_rstn */ 1281 <1 RK_PB3 1 &pcfg_pull_none>; 1282 }; 1283 1284 emmc_bus8: emmc-bus8 { 1285 rockchip,pins = 1286 /* emmc_d0 */ 1287 <1 RK_PA0 1 &pcfg_pull_none>, 1288 /* emmc_d1 */ 1289 <1 RK_PA1 1 &pcfg_pull_none>, 1290 /* emmc_d2 */ 1291 <1 RK_PA2 1 &pcfg_pull_none>, 1292 /* emmc_d3 */ 1293 <1 RK_PA3 1 &pcfg_pull_none>, 1294 /* emmc_d4 */ 1295 <1 RK_PA4 1 &pcfg_pull_none>, 1296 /* emmc_d5 */ 1297 <1 RK_PA5 1 &pcfg_pull_none>, 1298 /* emmc_d6 */ 1299 <1 RK_PA6 1 &pcfg_pull_none>, 1300 /* emmc_d7 */ 1301 <1 RK_PA7 1 &pcfg_pull_none>; 1302 }; 1303 1304 emmc_pwren: emmc-pwren { 1305 rockchip,pins = 1306 <1 RK_PB0 1 &pcfg_pull_none>; 1307 }; 1308 1309 emmc_cmd: emmc-cmd { 1310 rockchip,pins = 1311 <1 RK_PB2 1 &pcfg_pull_none>; 1312 }; 1313 }; 1314 1315 gmac { 1316 rgmii_pins: rgmii-pins { 1317 rockchip,pins = 1318 /* rgmii_txen */ 1319 <2 RK_PA1 2 &pcfg_pull_none_4ma>, 1320 /* rgmii_txd1 */ 1321 <2 RK_PA2 2 &pcfg_pull_none_4ma>, 1322 /* rgmii_txd0 */ 1323 <2 RK_PA3 2 &pcfg_pull_none_4ma>, 1324 /* rgmii_rxd0 */ 1325 <2 RK_PA4 2 &pcfg_pull_none>, 1326 /* rgmii_rxd1 */ 1327 <2 RK_PA5 2 &pcfg_pull_none>, 1328 /* rgmii_rxdv */ 1329 <2 RK_PA7 2 &pcfg_pull_none>, 1330 /* rgmii_mdio */ 1331 <2 RK_PB0 2 &pcfg_pull_none_2ma>, 1332 /* rgmii_mdc */ 1333 <2 RK_PB2 2 &pcfg_pull_none_2ma>, 1334 /* rgmii_txd3 */ 1335 <2 RK_PB3 2 &pcfg_pull_none_4ma>, 1336 /* rgmii_txd2 */ 1337 <2 RK_PB4 2 &pcfg_pull_none_4ma>, 1338 /* rgmii_rxd2 */ 1339 <2 RK_PB5 2 &pcfg_pull_none>, 1340 /* rgmii_rxd3 */ 1341 <2 RK_PB6 2 &pcfg_pull_none>, 1342 /* rgmii_clk */ 1343 <2 RK_PB7 2 &pcfg_pull_none>, 1344 /* rgmii_txclk */ 1345 <2 RK_PC1 2 &pcfg_pull_none_4ma>, 1346 /* rgmii_rxclk */ 1347 <2 RK_PC2 2 &pcfg_pull_none>; 1348 }; 1349 1350 rmii_pins: rmii-pins { 1351 rockchip,pins = 1352 /* rmii_txen */ 1353 <2 RK_PA1 2 &pcfg_pull_none_4ma>, 1354 /* rmii_txd1 */ 1355 <2 RK_PA2 2 &pcfg_pull_none_4ma>, 1356 /* rmii_txd0 */ 1357 <2 RK_PA3 2 &pcfg_pull_none_4ma>, 1358 /* rmii_rxd0 */ 1359 <2 RK_PA4 2 &pcfg_pull_none>, 1360 /* rmii_rxd1 */ 1361 <2 RK_PA5 2 &pcfg_pull_none>, 1362 /* rmii_rxer */ 1363 <2 RK_PA6 2 &pcfg_pull_none>, 1364 /* rmii_rxdv */ 1365 <2 RK_PA7 2 &pcfg_pull_none>, 1366 /* rmii_mdio */ 1367 <2 RK_PB0 2 &pcfg_pull_none_2ma>, 1368 /* rmii_mdc */ 1369 <2 RK_PB2 2 &pcfg_pull_none_2ma>, 1370 /* rmii_clk */ 1371 <2 RK_PB7 2 &pcfg_pull_none>; 1372 }; 1373 }; 1374 1375 i2c0 { 1376 i2c0_xfer: i2c0-xfer { 1377 rockchip,pins = 1378 /* i2c0_sda */ 1379 <0 RK_PB1 1 &pcfg_pull_none_smt>, 1380 /* i2c0_scl */ 1381 <0 RK_PB0 1 &pcfg_pull_none_smt>; 1382 }; 1383 }; 1384 1385 i2c1 { 1386 i2c1_xfer: i2c1-xfer { 1387 rockchip,pins = 1388 /* i2c1_sda */ 1389 <0 RK_PC1 1 &pcfg_pull_none_smt>, 1390 /* i2c1_scl */ 1391 <0 RK_PC0 1 &pcfg_pull_none_smt>; 1392 }; 1393 }; 1394 1395 i2c2m0 { 1396 i2c2m0_xfer: i2c2m0-xfer { 1397 rockchip,pins = 1398 /* i2c2m0_sda */ 1399 <3 RK_PB4 2 &pcfg_pull_none_smt>, 1400 /* i2c2m0_scl */ 1401 <3 RK_PB3 2 &pcfg_pull_none_smt>; 1402 }; 1403 }; 1404 1405 i2c3 { 1406 i2c3_xfer: i2c3-xfer { 1407 rockchip,pins = 1408 /* i2c3_sda */ 1409 <2 RK_PD1 1 &pcfg_pull_none_smt>, 1410 /* i2c3_scl */ 1411 <2 RK_PD0 1 &pcfg_pull_none_smt>; 1412 }; 1413 }; 1414 1415 i2c4 { 1416 i2c4_xfer: i2c4-xfer { 1417 rockchip,pins = 1418 /* i2c4_sda */ 1419 <3 RK_PC3 3 &pcfg_pull_none_smt>, 1420 /* i2c4_scl */ 1421 <3 RK_PC2 3 &pcfg_pull_none_smt>; 1422 }; 1423 }; 1424 1425 i2c5 { 1426 i2c5_xfer: i2c5-xfer { 1427 rockchip,pins = 1428 /* i2c5_sda */ 1429 <4 RK_PC2 1 &pcfg_pull_none_smt>, 1430 /* i2c5_scl */ 1431 <4 RK_PC1 1 &pcfg_pull_none_smt>; 1432 }; 1433 }; 1434 1435 i2s1 { 1436 i2s1_2ch_lrck: i2s1-2ch-lrck { 1437 rockchip,pins = 1438 <3 RK_PA0 1 &pcfg_pull_none>; 1439 }; 1440 i2s1_2ch_sclk: i2s1-2ch-sclk { 1441 rockchip,pins = 1442 <3 RK_PA1 1 &pcfg_pull_none>; 1443 }; 1444 i2s1_2ch_mclk: i2s1-2ch-mclk { 1445 rockchip,pins = 1446 <3 RK_PA2 1 &pcfg_pull_none>; 1447 }; 1448 i2s1_2ch_sdo: i2s1-2ch-sdo { 1449 rockchip,pins = 1450 <3 RK_PA3 1 &pcfg_pull_none>; 1451 }; 1452 i2s1_2ch_sdi: i2s1-2ch-sdi { 1453 rockchip,pins = 1454 <3 RK_PA4 1 &pcfg_pull_none>; 1455 }; 1456 }; 1457 1458 i2s0 { 1459 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1460 rockchip,pins = 1461 <3 RK_PA5 1 &pcfg_pull_none>; 1462 }; 1463 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1464 rockchip,pins = 1465 <3 RK_PA6 1 &pcfg_pull_none>; 1466 }; 1467 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1468 rockchip,pins = 1469 <3 RK_PA7 1 &pcfg_pull_none>; 1470 }; 1471 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1472 rockchip,pins = 1473 <3 RK_PB0 1 &pcfg_pull_none>; 1474 }; 1475 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1476 rockchip,pins = 1477 <3 RK_PB1 1 &pcfg_pull_none>; 1478 }; 1479 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1480 rockchip,pins = 1481 <3 RK_PB2 1 &pcfg_pull_none>; 1482 }; 1483 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1484 rockchip,pins = 1485 <3 RK_PB3 1 &pcfg_pull_none>; 1486 }; 1487 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1488 rockchip,pins = 1489 <3 RK_PB4 1 &pcfg_pull_none>; 1490 }; 1491 i2s0_8ch_mclk: i2s0-8ch-mclk { 1492 rockchip,pins = 1493 <3 RK_PB5 1 &pcfg_pull_none>; 1494 }; 1495 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1496 rockchip,pins = 1497 <3 RK_PB6 1 &pcfg_pull_none>; 1498 }; 1499 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1500 rockchip,pins = 1501 <3 RK_PB7 1 &pcfg_pull_none>; 1502 }; 1503 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1504 rockchip,pins = 1505 <3 RK_PC0 1 &pcfg_pull_none>; 1506 }; 1507 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1508 rockchip,pins = 1509 <3 RK_PC1 1 &pcfg_pull_none>; 1510 }; 1511 }; 1512 1513 lcdc { 1514 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 1515 rockchip,pins = 1516 /* lcdc_clkm0 */ 1517 <2 RK_PC6 3 &pcfg_pull_none>; 1518 }; 1519 1520 lcdc_rgb_den_pin: lcdc-rgb-den-pin { 1521 rockchip,pins = 1522 /* lcdc_denm0 */ 1523 <2 RK_PC7 3 &pcfg_pull_none>; 1524 }; 1525 1526 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 1527 rockchip,pins = 1528 /* lcdc_hsyncm0 */ 1529 <2 RK_PB2 3 &pcfg_pull_none>; 1530 }; 1531 1532 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 1533 rockchip,pins = 1534 /* lcdc_vsyncm0 */ 1535 <2 RK_PB3 3 &pcfg_pull_none>; 1536 }; 1537 1538 lcdc_rgb_m1_hsync_pin: lcdc-rgb-m1-hsync-pin { 1539 rockchip,pins = 1540 /* lcdc_hsyncm1 */ 1541 <3 RK_PB2 3 &pcfg_pull_none>; 1542 }; 1543 1544 lcdc_rgb_m1_vsync_pin: lcdc-rgb-m1-vsync-pin { 1545 rockchip,pins = 1546 /* lcdc_vsyncm1 */ 1547 <3 RK_PB3 3 &pcfg_pull_none>; 1548 }; 1549 1550 lcdc_rgb666_data_pins: lcdc-rgb666-data-pins { 1551 rockchip,pins = 1552 /* lcdc_d0m0 */ 1553 <2 RK_PA2 3 &pcfg_pull_none>, 1554 /* lcdc_d1m0 */ 1555 <2 RK_PA3 3 &pcfg_pull_none>, 1556 /* lcdc_d2m0 */ 1557 <2 RK_PC2 3 &pcfg_pull_none>, 1558 /* lcdc_d3m0 */ 1559 <2 RK_PC3 3 &pcfg_pull_none>, 1560 /* lcdc_d4m0 */ 1561 <2 RK_PC4 3 &pcfg_pull_none>, 1562 /* lcdc_d5m0 */ 1563 <2 RK_PC5 3 &pcfg_pull_none>, 1564 /* lcdc_d6m0 */ 1565 <2 RK_PA0 3 &pcfg_pull_none>, 1566 /* lcdc_d7m0 */ 1567 <2 RK_PA1 3 &pcfg_pull_none>, 1568 /* lcdc_d8 */ 1569 <3 RK_PC2 1 &pcfg_pull_none>, 1570 /* lcdc_d9 */ 1571 <3 RK_PC3 1 &pcfg_pull_none>, 1572 /* lcdc_d10 */ 1573 <3 RK_PC4 1 &pcfg_pull_none>, 1574 /* lcdc_d11 */ 1575 <3 RK_PC5 1 &pcfg_pull_none>, 1576 /* lcdc_d12 */ 1577 <3 RK_PC6 1 &pcfg_pull_none>, 1578 /* lcdc_d13 */ 1579 <3 RK_PC7 1 &pcfg_pull_none>, 1580 /* lcdc_d14 */ 1581 <3 RK_PD0 1 &pcfg_pull_none>, 1582 /* lcdc_d15 */ 1583 <3 RK_PD1 1 &pcfg_pull_none>, 1584 /* lcdc_d16 */ 1585 <3 RK_PD2 1 &pcfg_pull_none>, 1586 /* lcdc_d17 */ 1587 <3 RK_PD3 1 &pcfg_pull_none>; 1588 }; 1589 1590 lcdc_rgb565_data_pins: lcdc-rgb565-data-pins { 1591 rockchip,pins = 1592 /* lcdc_d0m0 */ 1593 <2 RK_PA2 3 &pcfg_pull_none>, 1594 /* lcdc_d1m0 */ 1595 <2 RK_PA3 3 &pcfg_pull_none>, 1596 /* lcdc_d2m0 */ 1597 <2 RK_PC2 3 &pcfg_pull_none>, 1598 /* lcdc_d3m0 */ 1599 <2 RK_PC3 3 &pcfg_pull_none>, 1600 /* lcdc_d4m0 */ 1601 <2 RK_PC4 3 &pcfg_pull_none>, 1602 /* lcdc_d5m0 */ 1603 <2 RK_PC5 3 &pcfg_pull_none>, 1604 /* lcdc_d6m0 */ 1605 <2 RK_PA0 3 &pcfg_pull_none>, 1606 /* lcdc_d7m0 */ 1607 <2 RK_PA1 3 &pcfg_pull_none>, 1608 /* lcdc_d8 */ 1609 <3 RK_PC2 1 &pcfg_pull_none>, 1610 /* lcdc_d9 */ 1611 <3 RK_PC3 1 &pcfg_pull_none>, 1612 /* lcdc_d10 */ 1613 <3 RK_PC4 1 &pcfg_pull_none>, 1614 /* lcdc_d11 */ 1615 <3 RK_PC5 1 &pcfg_pull_none>, 1616 /* lcdc_d12 */ 1617 <3 RK_PC6 1 &pcfg_pull_none>, 1618 /* lcdc_d13 */ 1619 <3 RK_PC7 1 &pcfg_pull_none>, 1620 /* lcdc_d14 */ 1621 <3 RK_PD0 1 &pcfg_pull_none>, 1622 /* lcdc_d15 */ 1623 <3 RK_PD1 1 &pcfg_pull_none>; 1624 }; 1625 }; 1626 1627 pciusb { 1628 pciusb_pins: pciusb-pins { 1629 rockchip,pins = 1630 /* pciusb_debug0 */ 1631 <4 RK_PB4 3 &pcfg_pull_none>, 1632 /* pciusb_debug1 */ 1633 <4 RK_PB5 3 &pcfg_pull_none>, 1634 /* pciusb_debug2 */ 1635 <4 RK_PB6 3 &pcfg_pull_none>, 1636 /* pciusb_debug3 */ 1637 <4 RK_PB7 3 &pcfg_pull_none>, 1638 /* pciusb_debug4 */ 1639 <4 RK_PC0 3 &pcfg_pull_none>, 1640 /* pciusb_debug5 */ 1641 <4 RK_PC1 3 &pcfg_pull_none>, 1642 /* pciusb_debug6 */ 1643 <4 RK_PC2 3 &pcfg_pull_none>, 1644 /* pciusb_debug7 */ 1645 <4 RK_PC3 3 &pcfg_pull_none>; 1646 }; 1647 }; 1648 1649 pdm { 1650 pdm_clk: pdm-clk { 1651 rockchip,pins = 1652 /* pdm_clk0 */ 1653 <3 RK_PB0 2 &pcfg_pull_none>; 1654 }; 1655 1656 pdm_sdi3: pdm-sdi3 { 1657 rockchip,pins = 1658 <3 RK_PA5 2 &pcfg_pull_none>; 1659 }; 1660 1661 pdm_sdi2: pdm-sdi2 { 1662 rockchip,pins = 1663 <3 RK_PA6 2 &pcfg_pull_none>; 1664 }; 1665 1666 pdm_sdi1: pdm-sdi1 { 1667 rockchip,pins = 1668 <3 RK_PA7 2 &pcfg_pull_none>; 1669 }; 1670 1671 pdm_clk1: pdm-clk1 { 1672 rockchip,pins = 1673 <3 RK_PB1 2 &pcfg_pull_none>; 1674 }; 1675 1676 pdm_sdi0: pdm-sdi0 { 1677 rockchip,pins = 1678 <3 RK_PC1 2 &pcfg_pull_none>; 1679 }; 1680 }; 1681 1682 pwm0 { 1683 pwm0_pin: pwm0-pin { 1684 rockchip,pins = 1685 <0 RK_PB7 1 &pcfg_pull_none>; 1686 }; 1687 }; 1688 1689 pwm1 { 1690 pwm1_pin: pwm1-pin { 1691 rockchip,pins = 1692 <0 RK_PC3 1 &pcfg_pull_none>; 1693 }; 1694 }; 1695 1696 pwm2 { 1697 pwm2_pin: pwm2-pin { 1698 rockchip,pins = 1699 <0 RK_PC5 1 &pcfg_pull_none>; 1700 }; 1701 }; 1702 1703 pwm3 { 1704 pwm3_pin: pwm3-pin { 1705 rockchip,pins = 1706 <0 RK_PC4 1 &pcfg_pull_none>; 1707 }; 1708 }; 1709 1710 pwm4 { 1711 pwm4_pin: pwm4-pin { 1712 rockchip,pins = 1713 <1 RK_PB6 2 &pcfg_pull_none>; 1714 }; 1715 }; 1716 1717 pwm5 { 1718 pwm5_pin: pwm5-pin { 1719 rockchip,pins = 1720 <1 RK_PB7 2 &pcfg_pull_none>; 1721 }; 1722 }; 1723 pwm6 { 1724 pwm6_pin: pwm6-pin { 1725 rockchip,pins = 1726 <3 RK_PA1 2 &pcfg_pull_none>; 1727 }; 1728 }; 1729 1730 pwm7 { 1731 pwm7_pin: pwm7-pin { 1732 rockchip,pins = 1733 <3 RK_PA2 2 &pcfg_pull_none>; 1734 }; 1735 }; 1736 1737 pwm8 { 1738 pwm8_pin: pwm8-pin { 1739 rockchip,pins = 1740 <3 RK_PD0 2 &pcfg_pull_none>; 1741 }; 1742 }; 1743 1744 pwm9 { 1745 pwm9_pin: pwm9-pin { 1746 rockchip,pins = 1747 <3 RK_PD1 2 &pcfg_pull_none>; 1748 }; 1749 }; 1750 1751 pwm10 { 1752 pwm10_pin: pwm10-pin { 1753 rockchip,pins = 1754 <3 RK_PD2 2 &pcfg_pull_none>; 1755 }; 1756 }; 1757 1758 pwm11 { 1759 pwm11_pin: pwm11-pin { 1760 rockchip,pins = 1761 <3 RK_PD3 2 &pcfg_pull_none>; 1762 }; 1763 }; 1764 1765 sdmmc0 { 1766 sdmmc0_bus4: sdmmc0-bus4 { 1767 rockchip,pins = 1768 /* sdmmc0_d0 */ 1769 <4 RK_PA2 1 &pcfg_pull_none>, 1770 /* sdmmc0_d1 */ 1771 <4 RK_PA3 1 &pcfg_pull_none>, 1772 /* sdmmc0_d2 */ 1773 <4 RK_PA4 1 &pcfg_pull_none>, 1774 /* sdmmc0_d3 */ 1775 <4 RK_PA5 1 &pcfg_pull_none>; 1776 }; 1777 sdmmc0_cmd: sdmmc0-cmd { 1778 rockchip,pins = 1779 <4 RK_PA0 1 &pcfg_pull_none>; 1780 }; 1781 sdmmc0_clk: sdmmc0-clk { 1782 rockchip,pins = 1783 <4 RK_PA1 1 &pcfg_pull_none>; 1784 }; 1785 }; 1786 1787 sdmmc1 { 1788 sdmmc1_bus4: sdmmc1-bus4 { 1789 rockchip,pins = 1790 /* sdmmc1_d0 */ 1791 <4 RK_PB0 1 &pcfg_pull_none>, 1792 /* sdmmc1_d1 */ 1793 <4 RK_PB1 1 &pcfg_pull_none>, 1794 /* sdmmc1_d2 */ 1795 <4 RK_PB2 1 &pcfg_pull_none>, 1796 /* sdmmc1_d3 */ 1797 <4 RK_PB3 1 &pcfg_pull_none>; 1798 }; 1799 1800 sdmmc1_cmd: sdmmc1-cmd { 1801 rockchip,pins = 1802 <4 RK_PA6 1 &pcfg_pull_none>; 1803 }; 1804 1805 sdmmc1_clk: sdmmc1-clk { 1806 rockchip,pins = 1807 <4 RK_PA7 1 &pcfg_pull_none>; 1808 }; 1809 }; 1810 1811 spi0 { 1812 spi0_mosi: spi0-mosi { 1813 rockchip,pins = 1814 <1 RK_PB4 1 &pcfg_pull_up_4ma>; 1815 }; 1816 1817 spi0_miso: spi0-miso { 1818 rockchip,pins = 1819 <1 RK_PB5 1 &pcfg_pull_up_4ma>; 1820 }; 1821 1822 spi0_csn: spi0-csn { 1823 rockchip,pins = 1824 <1 RK_PB6 1 &pcfg_pull_up_4ma>; 1825 }; 1826 1827 spi0_clk: spi0-clk { 1828 rockchip,pins = 1829 <1 RK_PB7 1 &pcfg_pull_up_4ma>; 1830 }; 1831 1832 spi0_mosi_hs: spi0-mosi-hs { 1833 rockchip,pins = 1834 <1 RK_PB4 1 &pcfg_pull_up_8ma>; 1835 }; 1836 1837 spi0_miso_hs: spi0-miso-hs { 1838 rockchip,pins = 1839 <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1840 }; 1841 1842 spi0_csn_hs: spi0-csn-hs { 1843 rockchip,pins = 1844 <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1845 }; 1846 1847 spi0_clk_hs: spi0-clk-hs { 1848 rockchip,pins = 1849 <1 RK_PB7 1 &pcfg_pull_up_8ma>; 1850 }; 1851 }; 1852 1853 spi1 { 1854 spi1_clk: spi1-clk { 1855 rockchip,pins = 1856 <4 RK_PB4 2 &pcfg_pull_up_4ma>; 1857 }; 1858 1859 spi1_mosi: spi1-mosi { 1860 rockchip,pins = 1861 <4 RK_PB5 2 &pcfg_pull_up_4ma>; 1862 }; 1863 1864 spi1_csn0: spi1-csn0 { 1865 rockchip,pins = 1866 <4 RK_PB6 2 &pcfg_pull_up_4ma>; 1867 }; 1868 1869 spi1_miso: spi1-miso { 1870 rockchip,pins = 1871 <4 RK_PB7 2 &pcfg_pull_up_4ma>; 1872 }; 1873 1874 spi1_csn1: spi1-csn1 { 1875 rockchip,pins = 1876 <4 RK_PC0 2 &pcfg_pull_up_4ma>; 1877 }; 1878 1879 spi1_clk_hs: spi1-clk-hs { 1880 rockchip,pins = 1881 <4 RK_PB4 2 &pcfg_pull_up_8ma>; 1882 }; 1883 1884 spi1_mosi_hs: spi1-mosi-hs { 1885 rockchip,pins = 1886 <4 RK_PB5 2 &pcfg_pull_up_8ma>; 1887 }; 1888 1889 spi1_csn0_hs: spi1-csn0-hs { 1890 rockchip,pins = 1891 <4 RK_PB6 2 &pcfg_pull_up_8ma>; 1892 }; 1893 1894 spi1_miso_hs: spi1-miso-hs { 1895 rockchip,pins = 1896 <4 RK_PB7 2 &pcfg_pull_up_8ma>; 1897 }; 1898 1899 spi1_csn1_hs: spi1-csn1-hs { 1900 rockchip,pins = 1901 <4 RK_PC0 2 &pcfg_pull_up_8ma>; 1902 }; 1903 }; 1904 1905 spi1m1 { 1906 spi1m1_clk: spi1m1-clk { 1907 rockchip,pins = 1908 <3 RK_PC7 3 &pcfg_pull_up_4ma>; 1909 }; 1910 1911 spi1m1_mosi: spi1m1-mosi { 1912 rockchip,pins = 1913 <3 RK_PD0 3 &pcfg_pull_up_4ma>; 1914 }; 1915 1916 spi1m1_csn0: spi1m1-csn0 { 1917 rockchip,pins = 1918 <3 RK_PD1 3 &pcfg_pull_up_4ma>; 1919 }; 1920 1921 spi1m1_miso: spi1m1-miso { 1922 rockchip,pins = 1923 <3 RK_PD2 3 &pcfg_pull_up_4ma>; 1924 }; 1925 1926 spi1m1_csn1: spi1m1-csn1 { 1927 rockchip,pins = 1928 <3 RK_PD3 3 &pcfg_pull_up_4ma>; 1929 }; 1930 1931 spi1m1_clk_hs: spi1m1-clk-hs { 1932 rockchip,pins = 1933 <3 RK_PC7 3 &pcfg_pull_up_8ma>; 1934 }; 1935 1936 spi1m1_mosi_hs: spi1m1-mosi-hs { 1937 rockchip,pins = 1938 <3 RK_PD0 3 &pcfg_pull_up_8ma>; 1939 }; 1940 1941 spi1m1_csn0_hs: spi1m1-csn0-hs { 1942 rockchip,pins = 1943 <3 RK_PD1 3 &pcfg_pull_up_8ma>; 1944 }; 1945 1946 spi1m1_miso_hs: spi1m1-miso-hs { 1947 rockchip,pins = 1948 <3 RK_PD2 3 &pcfg_pull_up_8ma>; 1949 }; 1950 1951 spi1m1_csn1_hs: spi1m1-csn1-hs { 1952 rockchip,pins = 1953 <3 RK_PD3 3 &pcfg_pull_up_8ma>; 1954 }; 1955 }; 1956 1957 spi2m0 { 1958 spi2m0_miso: spi2m0-miso { 1959 rockchip,pins = 1960 <1 RK_PA6 2 &pcfg_pull_up_4ma>; 1961 }; 1962 1963 spi2m0_clk: spi2m0-clk { 1964 rockchip,pins = 1965 <1 RK_PA7 2 &pcfg_pull_up_4ma>; 1966 }; 1967 1968 spi2m0_mosi: spi2m0-mosi { 1969 rockchip,pins = 1970 <1 RK_PB0 2 &pcfg_pull_up_4ma>; 1971 }; 1972 1973 spi2m0_csn: spi2m0-csn { 1974 rockchip,pins = 1975 <1 RK_PB1 2 &pcfg_pull_up_4ma>; 1976 }; 1977 1978 spi2m0_miso_hs: spi2m0-miso-hs { 1979 rockchip,pins = 1980 <1 RK_PA6 2 &pcfg_pull_none>; 1981 }; 1982 1983 spi2m0_clk_hs: spi2m0-clk-hs { 1984 rockchip,pins = 1985 <1 RK_PA7 2 &pcfg_pull_none>; 1986 }; 1987 1988 spi2m0_mosi_hs: spi2m0-mosi-hs { 1989 rockchip,pins = 1990 <1 RK_PB0 2 &pcfg_pull_none>; 1991 }; 1992 1993 spi2m0_csn_hs: spi2m0-csn-hs { 1994 rockchip,pins = 1995 <1 RK_PB1 2 &pcfg_pull_none>; 1996 }; 1997 }; 1998 1999 spi2m1 { 2000 spi2m1_miso: spi2m1-miso { 2001 rockchip,pins = 2002 <2 RK_PA4 3 &pcfg_pull_up_4ma>; 2003 }; 2004 2005 spi2m1_clk: spi2m1-clk { 2006 rockchip,pins = 2007 <2 RK_PA5 3 &pcfg_pull_up_4ma>; 2008 }; 2009 2010 spi2m1_mosi: spi2m1-mosi { 2011 rockchip,pins = 2012 <2 RK_PA6 3 &pcfg_pull_up_4ma>; 2013 }; 2014 2015 spi2m1_csn: spi2m1-csn { 2016 rockchip,pins = 2017 <2 RK_PA7 3 &pcfg_pull_up_4ma>; 2018 }; 2019 2020 spi2m1_miso_hs: spi2m1-miso-hs { 2021 rockchip,pins = 2022 <2 RK_PA4 3 &pcfg_pull_up_8ma>; 2023 }; 2024 2025 spi2m1_clk_hs: spi2m1-clk-hs { 2026 rockchip,pins = 2027 <2 RK_PA5 3 &pcfg_pull_up_8ma>; 2028 }; 2029 2030 spi2m1_mosi_hs: spi2m1-mosi-hs { 2031 rockchip,pins = 2032 <2 RK_PA6 3 &pcfg_pull_up_8ma>; 2033 }; 2034 2035 spi2m1_csn_hs: spi2m1-csn-hs { 2036 rockchip,pins = 2037 <2 RK_PA7 3 &pcfg_pull_up_8ma>; 2038 }; 2039 }; 2040 2041 uart0 { 2042 uart0_xfer: uart0-xfer { 2043 rockchip,pins = 2044 /* uart0_rx */ 2045 <0 RK_PB3 1 &pcfg_pull_none>, 2046 /* uart0_tx */ 2047 <0 RK_PB2 1 &pcfg_pull_none>; 2048 }; 2049 2050 uart0_cts: uart0-cts { 2051 rockchip,pins = 2052 <0 RK_PB4 1 &pcfg_pull_none>; 2053 }; 2054 2055 uart0_rts: uart0-rts { 2056 rockchip,pins = 2057 <0 RK_PB5 1 &pcfg_pull_none>; 2058 }; 2059 }; 2060 2061 uart1 { 2062 uart1m0_xfer: uart1m0-xfer { 2063 rockchip,pins = 2064 /* uart1_rxm0 */ 2065 <4 RK_PB0 2 &pcfg_pull_none>, 2066 /* uart1_txm0 */ 2067 <4 RK_PB1 2 &pcfg_pull_none>; 2068 }; 2069 2070 uart1m1_xfer: uart1m1-xfer { 2071 rockchip,pins = 2072 /* uart1_rxm1 */ 2073 <1 RK_PB4 3 &pcfg_pull_none>, 2074 /* uart1_txm1 */ 2075 <1 RK_PB5 3 &pcfg_pull_none>; 2076 }; 2077 2078 uart1_cts: uart1-cts { 2079 rockchip,pins = 2080 <4 RK_PB2 2 &pcfg_pull_none>; 2081 }; 2082 2083 uart1_rts: uart1-rts { 2084 rockchip,pins = 2085 <4 RK_PB3 2 &pcfg_pull_none>; 2086 }; 2087 }; 2088 2089 uart2 { 2090 uart2m0_xfer: uart2m0-xfer { 2091 rockchip,pins = 2092 /* uart2_rxm0 */ 2093 <4 RK_PA3 2 &pcfg_pull_none>, 2094 /* uart2_txm0 */ 2095 <4 RK_PA2 2 &pcfg_pull_none>; 2096 }; 2097 2098 uart2m1_xfer: uart2m1-xfer { 2099 rockchip,pins = 2100 /* uart2_rxm1 */ 2101 <2 RK_PD1 2 &pcfg_pull_none>, 2102 /* uart2_txm1 */ 2103 <2 RK_PD0 2 &pcfg_pull_none>; 2104 }; 2105 2106 uart2m2_xfer: uart2m2-xfer { 2107 rockchip,pins = 2108 /* uart2_rxm2 */ 2109 <3 RK_PA4 2 &pcfg_pull_none>, 2110 /* uart2_txm2 */ 2111 <3 RK_PA3 2 &pcfg_pull_none>; 2112 }; 2113 }; 2114 2115 uart3 { 2116 uart3m0_xfer: uart3m0-xfer { 2117 rockchip,pins = 2118 /* uart3_rxm0 */ 2119 <0 RK_PC5 2 &pcfg_pull_none>, 2120 /* uart3_txm0 */ 2121 <0 RK_PC4 2 &pcfg_pull_none>; 2122 }; 2123 2124 uart3_ctsm0: uart3-ctsm0 { 2125 rockchip,pins = 2126 <0 RK_PC7 2 &pcfg_pull_none>; 2127 }; 2128 2129 uart3_rtsm0: uart3-rtsm0 { 2130 rockchip,pins = 2131 <0 RK_PD0 2 &pcfg_pull_none>; 2132 }; 2133 }; 2134 2135 uart4 { 2136 uart4_xfer: uart4-xfer { 2137 rockchip,pins = 2138 /* uart4_rx */ 2139 <4 RK_PB4 1 &pcfg_pull_none>, 2140 /* uart4_tx */ 2141 <4 RK_PB5 1 &pcfg_pull_none>; 2142 }; 2143 2144 uart4_cts: uart4-cts { 2145 rockchip,pins = 2146 <4 RK_PB6 1 &pcfg_pull_none>; 2147 }; 2148 2149 uart4_rts: uart4-rts { 2150 rockchip,pins = 2151 <4 RK_PB7 1 &pcfg_pull_none>; 2152 }; 2153 }; 2154 2155 uart5 { 2156 uart5_xfer: uart5-xfer { 2157 rockchip,pins = 2158 /* uart5_rx */ 2159 <3 RK_PC3 1 &pcfg_pull_none>, 2160 /* uart5_tx */ 2161 <3 RK_PC2 1 &pcfg_pull_none>; 2162 }; 2163 }; 2164 2165 uart6 { 2166 uart6_xfer: uart6-xfer { 2167 rockchip,pins = 2168 /* uart6_rx */ 2169 <3 RK_PC5 1 &pcfg_pull_none>, 2170 /* uart6_tx */ 2171 <3 RK_PC4 1 &pcfg_pull_none>; 2172 }; 2173 }; 2174 2175 uart7 { 2176 uart7_xfer: uart7-xfer { 2177 rockchip,pins = 2178 /* uart7_rx */ 2179 <3 RK_PC7 1 &pcfg_pull_none>, 2180 /* uart7_tx */ 2181 <3 RK_PC6 1 &pcfg_pull_none>; 2182 }; 2183 }; 2184 2185 tsadc { 2186 tsadc_otp_gpio: tsadc-otp-gpio { 2187 rockchip,pins = 2188 <0 RK_PA6 0 &pcfg_pull_none>; 2189 }; 2190 2191 tsadc_otp_out: tsadc-otp-out { 2192 rockchip,pins = 2193 <0 RK_PA6 2 &pcfg_pull_none>; 2194 }; 2195 }; 2196 }; 2197}; 2198