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/OK3568_Linux_fs/kernel/drivers/clk/qcom/
H A Dvideocc-sm8150.c31 { 249600000, 2000000000, 0 },
35 .l = 0x14,
36 .alpha = 0xD555,
37 .config_ctl_val = 0x20485699,
38 .config_ctl_hi_val = 0x00002267,
39 .config_ctl_hi1_val = 0x00000024,
40 .user_ctl_val = 0x00000000,
41 .user_ctl_hi_val = 0x00000805,
42 .user_ctl_hi1_val = 0x000000D0,
46 .offset = 0x42c,
[all …]
H A Dvideocc-sdm845.c30 { P_BI_TCXO, 0 },
46 .l = 0x10,
47 .alpha = 0xaaab,
51 .offset = 0x42c,
64 F(100000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0),
65 F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
66 F(330000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
67 F(404000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
68 F(444000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
69 F(533000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
[all …]
H A Dvideocc-sc7180.c30 { 249600000, 2000000000, 0 },
34 .offset = 0x42c,
51 { P_BI_TCXO, 0 },
61 F(19200000, P_BI_TCXO, 1, 0, 0),
62 F(150000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0),
63 F(270000000, P_VIDEO_PLL0_OUT_MAIN, 2.5, 0, 0),
64 F(340000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
65 F(434000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
66 F(500000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
71 .cmd_rcgr = 0x7f0,
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dfpga_manager_gen5.h11 #define FPGAMGRREGS_STAT_MODE_MASK 0x7
12 #define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
19 #define FPGAMGRREGS_CTRL_EN_MASK BIT(0)
25 #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0)
28 #define FPGAMGRREGS_MODE_FPGAOFF 0x0
29 #define FPGAMGRREGS_MODE_RESETPHASE 0x1
30 #define FPGAMGRREGS_MODE_CFGPHASE 0x2
31 #define FPGAMGRREGS_MODE_INITPHASE 0x3
32 #define FPGAMGRREGS_MODE_USERMODE 0x4
33 #define FPGAMGRREGS_MODE_UNKNOWN 0x5
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/hisilicon/controller/
H A Dhi3798cv200-perictrl.yaml48 reg = <0x8a20000 0x1000>;
51 ranges = <0x0 0x8a20000 0x1000>;
55 reg = <0x850 0x8>;
58 resets = <&crg 0x188 4>;
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dmmdc.h10 #define MMDC0 0
13 #define MMDC_MDCTL 0x0
14 #define MMDC_MDPDC 0x4
15 #define MMDC_MDOTC 0x8
16 #define MMDC_MDCFG0 0xC
17 #define MMDC_MDCFG1 0x10
18 #define MMDC_MDCFG2 0x14
19 #define MMDC_MDMISC 0x18
20 #define MMDC_MDSCR 0x1C
21 #define MMDC_MDREF 0x20
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dphy-hi3798cv200-combphy.txt37 reg = <0x8a20000 0x1000>;
40 ranges = <0x0 0x8a20000 0x1000>;
44 reg = <0x850 0x8>;
47 resets = <&crg 0x188 4>;
53 reg = <0x858 0x8>;
56 resets = <&crg 0x188 12>;
57 hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dam335x-icev2.dts29 reg = <0x80000000 0x10000000>; /* 256 MB */
32 vbat: fixedregulator@0 {
51 leds@0 {
54 led@0 {
56 gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
107 pinctrl-0 = <&user_leds>;
109 led@0 {
152 AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
153 AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
154 AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
[all …]
H A Dam335x-evmsk.dts30 cpu@0 {
37 reg = <0x80000000 0x10000000>; /* 256 MB */
40 vbat: fixedregulator@0 {
56 pinctrl-0 = <&wl12xx_gpio>;
61 gpio = <&gpio1 29 0>;
79 pinctrl-0 = <&user_leds_s0>;
110 gpio_buttons: gpio_buttons@0 {
113 #size-cells = <0>;
117 linux,code = <0x100>;
123 linux,code = <0x101>;
[all …]
/OK3568_Linux_fs/kernel/include/dt-bindings/pinctrl/
H A Dam33xx.h18 #define SLEWCTRL_FAST 0
30 #define PIN_OUTPUT_PULLDOWN 0
43 #define AM335X_PIN_OFFSET_MIN 0x0800U
45 #define AM335X_PIN_GPMC_AD0 0x800
46 #define AM335X_PIN_GPMC_AD1 0x804
47 #define AM335X_PIN_GPMC_AD2 0x808
48 #define AM335X_PIN_GPMC_AD3 0x80c
49 #define AM335X_PIN_GPMC_AD4 0x810
50 #define AM335X_PIN_GPMC_AD5 0x814
51 #define AM335X_PIN_GPMC_AD6 0x818
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Ddra74x-mmc-iodelay.dtsi43 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
44 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
45 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
46 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
47 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
48 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
54 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
55 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
56 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
57 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
H A Ddra76x-mmc-iodelay.dtsi32 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
33 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
34 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
35 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
36 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
37 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
43 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
44 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
45 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
46 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
H A Dkeystone-k2hk.dtsi16 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
62 reg = <0x0c000000 0x600000>;
63 ranges = <0x0 0x0c000000 0x600000>;
68 reg = <0x5f0000 0x8000>;
78 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */
79 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */
80 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */
81 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */
[all …]
H A Dam437x-sk-evm.dts31 #clock-cells = <0>;
38 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
39 brightness-levels = <0 51 53 56 62 75 101 152 255>;
73 pinctrl-0 = <&matrix_keypad_pins>;
85 MATRIX_KEY(0, 0, KEY_DOWN)
86 MATRIX_KEY(0, 1, KEY_RIGHT)
87 MATRIX_KEY(1, 0, KEY_LEFT)
96 pinctrl-0 = <&leds_pins>;
100 gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */
131 pinctrl-0 = <&lcd_pins>;
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/mx6ullevk/
H A Dplugin.S12 ldr r1, =0x000C0000
13 str r1, [r0, #0x4B4]
14 ldr r1, =0x00000000
15 str r1, [r0, #0x4AC]
16 ldr r1, =0x00000030
17 str r1, [r0, #0x27C]
18 ldr r1, =0x00000030
19 str r1, [r0, #0x250]
20 str r1, [r0, #0x24C]
21 str r1, [r0, #0x490]
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/mx6sllevk/
H A Dplugin.S12 ldr r1, =0x00080000
13 str r1, [r0, #0x550]
14 ldr r1, =0x00000000
15 str r1, [r0, #0x534]
16 ldr r1, =0x00000030
17 str r1, [r0, #0x2AC]
18 str r1, [r0, #0x548]
19 str r1, [r0, #0x52C]
20 ldr r1, =0x00020000
21 str r1, [r0, #0x530]
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtw88/
H A Drtw8822b.h13 u8 res4[4]; /* 0xd0 */
15 u8 res5[0x1e];
17 u8 serial[0x0b]; /* 0xf5 */
18 u8 vid; /* 0x100 */
22 u8 mac_addr[ETH_ALEN]; /* 0x107 */
24 u8 vendor_name[0x07];
26 u8 device_name[0x14];
27 u8 res11[0xcf];
28 u8 package_type; /* 0x1fb */
29 u8 res12[0x4];
[all …]
H A Drtw8821c.h13 u8 mac_addr[ETH_ALEN]; /* 0xd0 */
21 u8 ltr_cap; /* 0xe3 */
26 u8 res0:2; /* 0xf4 */
50 u8 res0[0x0e];
55 u8 channel_plan; /* 0xb8 */
59 u8 pa_type; /* 0xbc */
60 u8 lna_type_2g[2]; /* 0xbd */
70 u8 rf_antenna_option; /* 0xc9 */
82 /* 0xC00-0xCFF and 0xE00-0xEFF have the same layout */ in _rtw_write32s_mask()
84 rtw_write32_mask(rtwdev, addr + 0x200, mask, data); in _rtw_write32s_mask()
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/mx7ulp_evk/
H A Dplugin.S10 ldr r2, =0x403f0000
11 ldr r3, =0x00000000
12 str r3, [r2, #0xdc]
14 ldr r2, =0x403e0000
15 ldr r3, =0x01000020
16 str r3, [r2, #0x40]
17 ldr r3, =0x01000000
18 str r3, [r2, #0x500]
19 ldr r3, =0x80808080
20 str r3, [r2, #0x50c]
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/sun4i/
H A Dsun4i_backend.h20 #define SUN4I_BACKEND_MODCTL_REG 0x800
24 #define SUN4I_BACKEND_MODCTL_OUT_LCD0 (0 << 20)
34 #define SUN4I_BACKEND_MODCTL_DEBE_EN BIT(0)
36 #define SUN4I_BACKEND_BACKCOLOR_REG 0x804
39 #define SUN4I_BACKEND_DISSIZE_REG 0x808
40 #define SUN4I_BACKEND_DISSIZE(w, h) (((((h) - 1) & 0xffff) << 16) | \
41 (((w) - 1) & 0xffff))
43 #define SUN4I_BACKEND_LAYSIZE_REG(l) (0x810 + (0x4 * (l)))
44 #define SUN4I_BACKEND_LAYSIZE(w, h) (((((h) - 1) & 0x1fff) << 16) | \
45 (((w) - 1) & 0x1fff))
[all …]
/OK3568_Linux_fs/kernel/drivers/infiniband/hw/hns/
H A Dhns_roce_common.h51 } while (0)
69 #define ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S 0
77 #define ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S 0
85 #define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S 0
93 #define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S 0
101 #define ROCEE_RAQ_WL_ROCEE_RAQ_WL_S 0
105 #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S 0
119 #define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S 0
127 #define ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S 0
135 #define ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S 0
[all …]
/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Drenesas_sdhi_internal_dmac.c25 #define DM_CM_DTRAN_MODE 0x820
26 #define DM_CM_DTRAN_CTRL 0x828
27 #define DM_CM_RST 0x830
28 #define DM_CM_INFO1 0x840
29 #define DM_CM_INFO1_MASK 0x848
30 #define DM_CM_INFO2 0x850
31 #define DM_CM_INFO2_MASK 0x858
32 #define DM_DTRAN_ADDR 0x880
35 #define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */
38 #define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address, 0 = Fixed */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-hi6220/
H A Dhi6220_regs_alwayson.h11 #define ALWAYSON_CTRL_BASE 0xF7800000
14 u32 ctrl0; /*0x0*/
20 u32 stat0; /*0x10*/
27 u32 secondary_int_en0; /*0x44*/
33 u32 mcu_wkup_int_en6; /*0x54*/
39 u32 mcu_wkup_int_en5; /*0x64*/
45 u32 mcu_wkup_int_en4; /*0x94*/
51 u32 mcu_wkup_int_en0; /*0xa8*/
55 u32 mcu_wkup_int_en1; /*0xb4*/
61 u32 int_statr; /*0xc4*/
[all …]
/OK3568_Linux_fs/kernel/drivers/media/pci/cx18/
H A Dcx18-av-core.h32 CX18_AV_SVIDEO_LUMA1 = 0x10,
33 CX18_AV_SVIDEO_LUMA2 = 0x20,
34 CX18_AV_SVIDEO_LUMA3 = 0x30,
35 CX18_AV_SVIDEO_LUMA4 = 0x40,
36 CX18_AV_SVIDEO_LUMA5 = 0x50,
37 CX18_AV_SVIDEO_LUMA6 = 0x60,
38 CX18_AV_SVIDEO_LUMA7 = 0x70,
39 CX18_AV_SVIDEO_LUMA8 = 0x80,
40 CX18_AV_SVIDEO_CHROMA4 = 0x400,
41 CX18_AV_SVIDEO_CHROMA5 = 0x500,
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/
H A Dgt64120.h21 #define GT_CPU_OFS 0x000
23 #define GT_MULTI_OFS 0x120
26 #define GT_SCS10LD_OFS 0x008
27 #define GT_SCS10HD_OFS 0x010
28 #define GT_SCS32LD_OFS 0x018
29 #define GT_SCS32HD_OFS 0x020
30 #define GT_CS20LD_OFS 0x028
31 #define GT_CS20HD_OFS 0x030
32 #define GT_CS3BOOTLD_OFS 0x038
33 #define GT_CS3BOOTHD_OFS 0x040
[all …]

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