1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2*4882a593Smuzhiyun /* Copyright(c) 2018-2019 Realtek Corporation
3*4882a593Smuzhiyun */
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #ifndef __RTW8822B_H__
6*4882a593Smuzhiyun #define __RTW8822B_H__
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <asm/byteorder.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #define RCR_VHT_ACK BIT(26)
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun struct rtw8822bu_efuse {
13*4882a593Smuzhiyun u8 res4[4]; /* 0xd0 */
14*4882a593Smuzhiyun u8 usb_optional_function;
15*4882a593Smuzhiyun u8 res5[0x1e];
16*4882a593Smuzhiyun u8 res6[2];
17*4882a593Smuzhiyun u8 serial[0x0b]; /* 0xf5 */
18*4882a593Smuzhiyun u8 vid; /* 0x100 */
19*4882a593Smuzhiyun u8 res7;
20*4882a593Smuzhiyun u8 pid;
21*4882a593Smuzhiyun u8 res8[4];
22*4882a593Smuzhiyun u8 mac_addr[ETH_ALEN]; /* 0x107 */
23*4882a593Smuzhiyun u8 res9[2];
24*4882a593Smuzhiyun u8 vendor_name[0x07];
25*4882a593Smuzhiyun u8 res10[2];
26*4882a593Smuzhiyun u8 device_name[0x14];
27*4882a593Smuzhiyun u8 res11[0xcf];
28*4882a593Smuzhiyun u8 package_type; /* 0x1fb */
29*4882a593Smuzhiyun u8 res12[0x4];
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun struct rtw8822be_efuse {
33*4882a593Smuzhiyun u8 mac_addr[ETH_ALEN]; /* 0xd0 */
34*4882a593Smuzhiyun u8 vender_id[2];
35*4882a593Smuzhiyun u8 device_id[2];
36*4882a593Smuzhiyun u8 sub_vender_id[2];
37*4882a593Smuzhiyun u8 sub_device_id[2];
38*4882a593Smuzhiyun u8 pmc[2];
39*4882a593Smuzhiyun u8 exp_device_cap[2];
40*4882a593Smuzhiyun u8 msi_cap;
41*4882a593Smuzhiyun u8 ltr_cap; /* 0xe3 */
42*4882a593Smuzhiyun u8 exp_link_control[2];
43*4882a593Smuzhiyun u8 link_cap[4];
44*4882a593Smuzhiyun u8 link_control[2];
45*4882a593Smuzhiyun u8 serial_number[8];
46*4882a593Smuzhiyun u8 res0:2; /* 0xf4 */
47*4882a593Smuzhiyun u8 ltr_en:1;
48*4882a593Smuzhiyun u8 res1:2;
49*4882a593Smuzhiyun u8 obff:2;
50*4882a593Smuzhiyun u8 res2:3;
51*4882a593Smuzhiyun u8 obff_cap:2;
52*4882a593Smuzhiyun u8 res3:4;
53*4882a593Smuzhiyun u8 res4[3];
54*4882a593Smuzhiyun u8 class_code[3];
55*4882a593Smuzhiyun u8 pci_pm_L1_2_supp:1;
56*4882a593Smuzhiyun u8 pci_pm_L1_1_supp:1;
57*4882a593Smuzhiyun u8 aspm_pm_L1_2_supp:1;
58*4882a593Smuzhiyun u8 aspm_pm_L1_1_supp:1;
59*4882a593Smuzhiyun u8 L1_pm_substates_supp:1;
60*4882a593Smuzhiyun u8 res5:3;
61*4882a593Smuzhiyun u8 port_common_mode_restore_time;
62*4882a593Smuzhiyun u8 port_t_power_on_scale:2;
63*4882a593Smuzhiyun u8 res6:1;
64*4882a593Smuzhiyun u8 port_t_power_on_value:5;
65*4882a593Smuzhiyun u8 res7;
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun struct rtw8822b_efuse {
69*4882a593Smuzhiyun __le16 rtl_id;
70*4882a593Smuzhiyun u8 res0[0x0e];
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* power index for four RF paths */
73*4882a593Smuzhiyun struct rtw_txpwr_idx txpwr_idx_table[4];
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun u8 channel_plan; /* 0xb8 */
76*4882a593Smuzhiyun u8 xtal_k;
77*4882a593Smuzhiyun u8 thermal_meter;
78*4882a593Smuzhiyun u8 iqk_lck;
79*4882a593Smuzhiyun u8 pa_type; /* 0xbc */
80*4882a593Smuzhiyun u8 lna_type_2g[2]; /* 0xbd */
81*4882a593Smuzhiyun u8 lna_type_5g[2];
82*4882a593Smuzhiyun u8 rf_board_option;
83*4882a593Smuzhiyun u8 rf_feature_option;
84*4882a593Smuzhiyun u8 rf_bt_setting;
85*4882a593Smuzhiyun u8 eeprom_version;
86*4882a593Smuzhiyun u8 eeprom_customer_id;
87*4882a593Smuzhiyun u8 tx_bb_swing_setting_2g;
88*4882a593Smuzhiyun u8 tx_bb_swing_setting_5g;
89*4882a593Smuzhiyun u8 tx_pwr_calibrate_rate;
90*4882a593Smuzhiyun u8 rf_antenna_option; /* 0xc9 */
91*4882a593Smuzhiyun u8 rfe_option;
92*4882a593Smuzhiyun u8 country_code[2];
93*4882a593Smuzhiyun u8 res[3];
94*4882a593Smuzhiyun union {
95*4882a593Smuzhiyun struct rtw8822bu_efuse u;
96*4882a593Smuzhiyun struct rtw8822be_efuse e;
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun static inline void
_rtw_write32s_mask(struct rtw_dev * rtwdev,u32 addr,u32 mask,u32 data)101*4882a593Smuzhiyun _rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun /* 0xC00-0xCFF and 0xE00-0xEFF have the same layout */
104*4882a593Smuzhiyun rtw_write32_mask(rtwdev, addr, mask, data);
105*4882a593Smuzhiyun rtw_write32_mask(rtwdev, addr + 0x200, mask, data);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun #define rtw_write32s_mask(rtwdev, addr, mask, data) \
109*4882a593Smuzhiyun do { \
110*4882a593Smuzhiyun BUILD_BUG_ON((addr) < 0xC00 || (addr) >= 0xD00); \
111*4882a593Smuzhiyun \
112*4882a593Smuzhiyun _rtw_write32s_mask(rtwdev, addr, mask, data); \
113*4882a593Smuzhiyun } while (0)
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /* phy status page0 */
116*4882a593Smuzhiyun #define GET_PHY_STAT_P0_PWDB(phy_stat) \
117*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /* phy status page1 */
120*4882a593Smuzhiyun #define GET_PHY_STAT_P1_PWDB_A(phy_stat) \
121*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
122*4882a593Smuzhiyun #define GET_PHY_STAT_P1_PWDB_B(phy_stat) \
123*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
124*4882a593Smuzhiyun #define GET_PHY_STAT_P1_RF_MODE(phy_stat) \
125*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
126*4882a593Smuzhiyun #define GET_PHY_STAT_P1_L_RXSC(phy_stat) \
127*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
128*4882a593Smuzhiyun #define GET_PHY_STAT_P1_HT_RXSC(phy_stat) \
129*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
130*4882a593Smuzhiyun #define GET_PHY_STAT_P1_RXEVM_A(phy_stat) \
131*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
132*4882a593Smuzhiyun #define GET_PHY_STAT_P1_RXEVM_B(phy_stat) \
133*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
134*4882a593Smuzhiyun #define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat) \
135*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
136*4882a593Smuzhiyun #define GET_PHY_STAT_P1_CFO_TAIL_B(phy_stat) \
137*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
138*4882a593Smuzhiyun #define GET_PHY_STAT_P1_RXSNR_A(phy_stat) \
139*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
140*4882a593Smuzhiyun #define GET_PHY_STAT_P1_RXSNR_B(phy_stat) \
141*4882a593Smuzhiyun le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun #define REG_HTSTFWT 0x800
144*4882a593Smuzhiyun #define REG_RXPSEL 0x808
145*4882a593Smuzhiyun #define BIT_RX_PSEL_RST (BIT(28) | BIT(29))
146*4882a593Smuzhiyun #define REG_TXPSEL 0x80c
147*4882a593Smuzhiyun #define REG_RXCCAMSK 0x814
148*4882a593Smuzhiyun #define REG_CCASEL 0x82c
149*4882a593Smuzhiyun #define REG_PDMFTH 0x830
150*4882a593Smuzhiyun #define REG_CCA2ND 0x838
151*4882a593Smuzhiyun #define REG_L1WT 0x83c
152*4882a593Smuzhiyun #define REG_L1PKWT 0x840
153*4882a593Smuzhiyun #define REG_MRC 0x850
154*4882a593Smuzhiyun #define REG_CLKTRK 0x860
155*4882a593Smuzhiyun #define REG_ADCCLK 0x8ac
156*4882a593Smuzhiyun #define REG_ADC160 0x8c4
157*4882a593Smuzhiyun #define REG_ADC40 0x8c8
158*4882a593Smuzhiyun #define REG_CDDTXP 0x93c
159*4882a593Smuzhiyun #define REG_TXPSEL1 0x940
160*4882a593Smuzhiyun #define REG_ACBB0 0x948
161*4882a593Smuzhiyun #define REG_ACBBRXFIR 0x94c
162*4882a593Smuzhiyun #define REG_ACGG2TBL 0x958
163*4882a593Smuzhiyun #define REG_RXSB 0xa00
164*4882a593Smuzhiyun #define REG_ADCINI 0xa04
165*4882a593Smuzhiyun #define REG_TXSF2 0xa24
166*4882a593Smuzhiyun #define REG_TXSF6 0xa28
167*4882a593Smuzhiyun #define REG_RXDESC 0xa2c
168*4882a593Smuzhiyun #define REG_ENTXCCK 0xa80
169*4882a593Smuzhiyun #define REG_AGCTR_A 0xc08
170*4882a593Smuzhiyun #define REG_TXDFIR 0xc20
171*4882a593Smuzhiyun #define REG_RXIGI_A 0xc50
172*4882a593Smuzhiyun #define REG_TRSW 0xca0
173*4882a593Smuzhiyun #define REG_RFESEL0 0xcb0
174*4882a593Smuzhiyun #define REG_RFESEL8 0xcb4
175*4882a593Smuzhiyun #define REG_RFECTL 0xcb8
176*4882a593Smuzhiyun #define REG_RFEINV 0xcbc
177*4882a593Smuzhiyun #define REG_AGCTR_B 0xe08
178*4882a593Smuzhiyun #define REG_RXIGI_B 0xe50
179*4882a593Smuzhiyun #define REG_ANTWT 0x1904
180*4882a593Smuzhiyun #define REG_IQKFAILMSK 0x1bf0
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun #endif
183