1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides constants specific to AM33XX pinctrl bindings. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_PINCTRL_AM33XX_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_PINCTRL_AM33XX_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <dt-bindings/pinctrl/omap.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* am33xx specific mux bit defines */ 12*4882a593Smuzhiyun #undef PULL_ENA 13*4882a593Smuzhiyun #undef INPUT_EN 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define PULL_DISABLE (1 << 3) 16*4882a593Smuzhiyun #define INPUT_EN (1 << 5) 17*4882a593Smuzhiyun #define SLEWCTRL_SLOW (1 << 6) 18*4882a593Smuzhiyun #define SLEWCTRL_FAST 0 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* update macro depending on INPUT_EN and PULL_ENA */ 21*4882a593Smuzhiyun #undef PIN_OUTPUT 22*4882a593Smuzhiyun #undef PIN_OUTPUT_PULLUP 23*4882a593Smuzhiyun #undef PIN_OUTPUT_PULLDOWN 24*4882a593Smuzhiyun #undef PIN_INPUT 25*4882a593Smuzhiyun #undef PIN_INPUT_PULLUP 26*4882a593Smuzhiyun #undef PIN_INPUT_PULLDOWN 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define PIN_OUTPUT (PULL_DISABLE) 29*4882a593Smuzhiyun #define PIN_OUTPUT_PULLUP (PULL_UP) 30*4882a593Smuzhiyun #define PIN_OUTPUT_PULLDOWN 0 31*4882a593Smuzhiyun #define PIN_INPUT (INPUT_EN | PULL_DISABLE) 32*4882a593Smuzhiyun #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) 33*4882a593Smuzhiyun #define PIN_INPUT_PULLDOWN (INPUT_EN) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* undef non-existing modes */ 36*4882a593Smuzhiyun #undef PIN_OFF_NONE 37*4882a593Smuzhiyun #undef PIN_OFF_OUTPUT_HIGH 38*4882a593Smuzhiyun #undef PIN_OFF_OUTPUT_LOW 39*4882a593Smuzhiyun #undef PIN_OFF_INPUT_PULLUP 40*4882a593Smuzhiyun #undef PIN_OFF_INPUT_PULLDOWN 41*4882a593Smuzhiyun #undef PIN_OFF_WAKEUPENABLE 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define AM335X_PIN_OFFSET_MIN 0x0800U 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define AM335X_PIN_GPMC_AD0 0x800 46*4882a593Smuzhiyun #define AM335X_PIN_GPMC_AD1 0x804 47*4882a593Smuzhiyun #define AM335X_PIN_GPMC_AD2 0x808 48*4882a593Smuzhiyun #define AM335X_PIN_GPMC_AD3 0x80c 49*4882a593Smuzhiyun #define AM335X_PIN_GPMC_AD4 0x810 50*4882a593Smuzhiyun #define AM335X_PIN_GPMC_AD5 0x814 51*4882a593Smuzhiyun #define AM335X_PIN_GPMC_AD6 0x818 52*4882a593Smuzhiyun #define AM335X_PIN_GPMC_AD7 0x81c 53*4882a593Smuzhiyun #define AM335X_PIN_GPMC_AD8 0x820 54*4882a593Smuzhiyun #define AM335X_PIN_GPMC_AD9 0x824 55*4882a593Smuzhiyun #define AM335X_PIN_GPMC_AD10 0x828 56*4882a593Smuzhiyun #define AM335X_PIN_GPMC_AD11 0x82c 57*4882a593Smuzhiyun #define AM335X_PIN_GPMC_AD12 0x830 58*4882a593Smuzhiyun #define AM335X_PIN_GPMC_AD13 0x834 59*4882a593Smuzhiyun #define AM335X_PIN_GPMC_AD14 0x838 60*4882a593Smuzhiyun #define AM335X_PIN_GPMC_AD15 0x83c 61*4882a593Smuzhiyun #define AM335X_PIN_GPMC_A0 0x840 62*4882a593Smuzhiyun #define AM335X_PIN_GPMC_A1 0x844 63*4882a593Smuzhiyun #define AM335X_PIN_GPMC_A2 0x848 64*4882a593Smuzhiyun #define AM335X_PIN_GPMC_A3 0x84c 65*4882a593Smuzhiyun #define AM335X_PIN_GPMC_A4 0x850 66*4882a593Smuzhiyun #define AM335X_PIN_GPMC_A5 0x854 67*4882a593Smuzhiyun #define AM335X_PIN_GPMC_A6 0x858 68*4882a593Smuzhiyun #define AM335X_PIN_GPMC_A7 0x85c 69*4882a593Smuzhiyun #define AM335X_PIN_GPMC_A8 0x860 70*4882a593Smuzhiyun #define AM335X_PIN_GPMC_A9 0x864 71*4882a593Smuzhiyun #define AM335X_PIN_GPMC_A10 0x868 72*4882a593Smuzhiyun #define AM335X_PIN_GPMC_A11 0x86c 73*4882a593Smuzhiyun #define AM335X_PIN_GPMC_WAIT0 0x870 74*4882a593Smuzhiyun #define AM335X_PIN_GPMC_WPN 0x874 75*4882a593Smuzhiyun #define AM335X_PIN_GPMC_BEN1 0x878 76*4882a593Smuzhiyun #define AM335X_PIN_GPMC_CSN0 0x87c 77*4882a593Smuzhiyun #define AM335X_PIN_GPMC_CSN1 0x880 78*4882a593Smuzhiyun #define AM335X_PIN_GPMC_CSN2 0x884 79*4882a593Smuzhiyun #define AM335X_PIN_GPMC_CSN3 0x888 80*4882a593Smuzhiyun #define AM335X_PIN_GPMC_CLK 0x88c 81*4882a593Smuzhiyun #define AM335X_PIN_GPMC_ADVN_ALE 0x890 82*4882a593Smuzhiyun #define AM335X_PIN_GPMC_OEN_REN 0x894 83*4882a593Smuzhiyun #define AM335X_PIN_GPMC_WEN 0x898 84*4882a593Smuzhiyun #define AM335X_PIN_GPMC_BEN0_CLE 0x89c 85*4882a593Smuzhiyun #define AM335X_PIN_LCD_DATA0 0x8a0 86*4882a593Smuzhiyun #define AM335X_PIN_LCD_DATA1 0x8a4 87*4882a593Smuzhiyun #define AM335X_PIN_LCD_DATA2 0x8a8 88*4882a593Smuzhiyun #define AM335X_PIN_LCD_DATA3 0x8ac 89*4882a593Smuzhiyun #define AM335X_PIN_LCD_DATA4 0x8b0 90*4882a593Smuzhiyun #define AM335X_PIN_LCD_DATA5 0x8b4 91*4882a593Smuzhiyun #define AM335X_PIN_LCD_DATA6 0x8b8 92*4882a593Smuzhiyun #define AM335X_PIN_LCD_DATA7 0x8bc 93*4882a593Smuzhiyun #define AM335X_PIN_LCD_DATA8 0x8c0 94*4882a593Smuzhiyun #define AM335X_PIN_LCD_DATA9 0x8c4 95*4882a593Smuzhiyun #define AM335X_PIN_LCD_DATA10 0x8c8 96*4882a593Smuzhiyun #define AM335X_PIN_LCD_DATA11 0x8cc 97*4882a593Smuzhiyun #define AM335X_PIN_LCD_DATA12 0x8d0 98*4882a593Smuzhiyun #define AM335X_PIN_LCD_DATA13 0x8d4 99*4882a593Smuzhiyun #define AM335X_PIN_LCD_DATA14 0x8d8 100*4882a593Smuzhiyun #define AM335X_PIN_LCD_DATA15 0x8dc 101*4882a593Smuzhiyun #define AM335X_PIN_LCD_VSYNC 0x8e0 102*4882a593Smuzhiyun #define AM335X_PIN_LCD_HSYNC 0x8e4 103*4882a593Smuzhiyun #define AM335X_PIN_LCD_PCLK 0x8e8 104*4882a593Smuzhiyun #define AM335X_PIN_LCD_AC_BIAS_EN 0x8ec 105*4882a593Smuzhiyun #define AM335X_PIN_MMC0_DAT3 0x8f0 106*4882a593Smuzhiyun #define AM335X_PIN_MMC0_DAT2 0x8f4 107*4882a593Smuzhiyun #define AM335X_PIN_MMC0_DAT1 0x8f8 108*4882a593Smuzhiyun #define AM335X_PIN_MMC0_DAT0 0x8fc 109*4882a593Smuzhiyun #define AM335X_PIN_MMC0_CLK 0x900 110*4882a593Smuzhiyun #define AM335X_PIN_MMC0_CMD 0x904 111*4882a593Smuzhiyun #define AM335X_PIN_MII1_COL 0x908 112*4882a593Smuzhiyun #define AM335X_PIN_MII1_CRS 0x90c 113*4882a593Smuzhiyun #define AM335X_PIN_MII1_RX_ER 0x910 114*4882a593Smuzhiyun #define AM335X_PIN_MII1_TX_EN 0x914 115*4882a593Smuzhiyun #define AM335X_PIN_MII1_RX_DV 0x918 116*4882a593Smuzhiyun #define AM335X_PIN_MII1_TXD3 0x91c 117*4882a593Smuzhiyun #define AM335X_PIN_MII1_TXD2 0x920 118*4882a593Smuzhiyun #define AM335X_PIN_MII1_TXD1 0x924 119*4882a593Smuzhiyun #define AM335X_PIN_MII1_TXD0 0x928 120*4882a593Smuzhiyun #define AM335X_PIN_MII1_TX_CLK 0x92c 121*4882a593Smuzhiyun #define AM335X_PIN_MII1_RX_CLK 0x930 122*4882a593Smuzhiyun #define AM335X_PIN_MII1_RXD3 0x934 123*4882a593Smuzhiyun #define AM335X_PIN_MII1_RXD2 0x938 124*4882a593Smuzhiyun #define AM335X_PIN_MII1_RXD1 0x93c 125*4882a593Smuzhiyun #define AM335X_PIN_MII1_RXD0 0x940 126*4882a593Smuzhiyun #define AM335X_PIN_RMII1_REF_CLK 0x944 127*4882a593Smuzhiyun #define AM335X_PIN_MDIO 0x948 128*4882a593Smuzhiyun #define AM335X_PIN_MDC 0x94c 129*4882a593Smuzhiyun #define AM335X_PIN_SPI0_SCLK 0x950 130*4882a593Smuzhiyun #define AM335X_PIN_SPI0_D0 0x954 131*4882a593Smuzhiyun #define AM335X_PIN_SPI0_D1 0x958 132*4882a593Smuzhiyun #define AM335X_PIN_SPI0_CS0 0x95c 133*4882a593Smuzhiyun #define AM335X_PIN_SPI0_CS1 0x960 134*4882a593Smuzhiyun #define AM335X_PIN_ECAP0_IN_PWM0_OUT 0x964 135*4882a593Smuzhiyun #define AM335X_PIN_UART0_CTSN 0x968 136*4882a593Smuzhiyun #define AM335X_PIN_UART0_RTSN 0x96c 137*4882a593Smuzhiyun #define AM335X_PIN_UART0_RXD 0x970 138*4882a593Smuzhiyun #define AM335X_PIN_UART0_TXD 0x974 139*4882a593Smuzhiyun #define AM335X_PIN_UART1_CTSN 0x978 140*4882a593Smuzhiyun #define AM335X_PIN_UART1_RTSN 0x97c 141*4882a593Smuzhiyun #define AM335X_PIN_UART1_RXD 0x980 142*4882a593Smuzhiyun #define AM335X_PIN_UART1_TXD 0x984 143*4882a593Smuzhiyun #define AM335X_PIN_I2C0_SDA 0x988 144*4882a593Smuzhiyun #define AM335X_PIN_I2C0_SCL 0x98c 145*4882a593Smuzhiyun #define AM335X_PIN_MCASP0_ACLKX 0x990 146*4882a593Smuzhiyun #define AM335X_PIN_MCASP0_FSX 0x994 147*4882a593Smuzhiyun #define AM335X_PIN_MCASP0_AXR0 0x998 148*4882a593Smuzhiyun #define AM335X_PIN_MCASP0_AHCLKR 0x99c 149*4882a593Smuzhiyun #define AM335X_PIN_MCASP0_ACLKR 0x9a0 150*4882a593Smuzhiyun #define AM335X_PIN_MCASP0_FSR 0x9a4 151*4882a593Smuzhiyun #define AM335X_PIN_MCASP0_AXR1 0x9a8 152*4882a593Smuzhiyun #define AM335X_PIN_MCASP0_AHCLKX 0x9ac 153*4882a593Smuzhiyun #define AM335X_PIN_XDMA_EVENT_INTR0 0x9b0 154*4882a593Smuzhiyun #define AM335X_PIN_XDMA_EVENT_INTR1 0x9b4 155*4882a593Smuzhiyun #define AM335X_PIN_WARMRSTN 0x9b8 156*4882a593Smuzhiyun #define AM335X_PIN_NNMI 0x9c0 157*4882a593Smuzhiyun #define AM335X_PIN_TMS 0x9d0 158*4882a593Smuzhiyun #define AM335X_PIN_TDI 0x9d4 159*4882a593Smuzhiyun #define AM335X_PIN_TDO 0x9d8 160*4882a593Smuzhiyun #define AM335X_PIN_TCK 0x9dc 161*4882a593Smuzhiyun #define AM335X_PIN_TRSTN 0x9e0 162*4882a593Smuzhiyun #define AM335X_PIN_EMU0 0x9e4 163*4882a593Smuzhiyun #define AM335X_PIN_EMU1 0x9e8 164*4882a593Smuzhiyun #define AM335X_PIN_RTC_PWRONRSTN 0x9f8 165*4882a593Smuzhiyun #define AM335X_PIN_PMIC_POWER_EN 0x9fc 166*4882a593Smuzhiyun #define AM335X_PIN_EXT_WAKEUP 0xa00 167*4882a593Smuzhiyun #define AM335X_PIN_USB0_DRVVBUS 0xa1c 168*4882a593Smuzhiyun #define AM335X_PIN_USB1_DRVVBUS 0xa34 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun #define AM335X_PIN_OFFSET_MAX 0x0a34U 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun #endif 173