xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/am335x-icev2.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify
5*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as
6*4882a593Smuzhiyun * published by the Free Software Foundation.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/*
10*4882a593Smuzhiyun * AM335x ICE V2 board
11*4882a593Smuzhiyun * http://www.ti.com/tool/tmdsice3359
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun/dts-v1/;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun#include "am33xx.dtsi"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun/ {
19*4882a593Smuzhiyun	model = "TI AM3359 ICE-V2";
20*4882a593Smuzhiyun	compatible = "ti,am3359-icev2", "ti,am33xx";
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	chosen {
23*4882a593Smuzhiyun		stdout-path = &uart3;
24*4882a593Smuzhiyun		tick-timer = &timer2;
25*4882a593Smuzhiyun	};
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun	memory {
28*4882a593Smuzhiyun		device_type = "memory";
29*4882a593Smuzhiyun		reg = <0x80000000 0x10000000>; /* 256 MB */
30*4882a593Smuzhiyun	};
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun	vbat: fixedregulator@0 {
33*4882a593Smuzhiyun		compatible = "regulator-fixed";
34*4882a593Smuzhiyun		regulator-name = "vbat";
35*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
36*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
37*4882a593Smuzhiyun		regulator-boot-on;
38*4882a593Smuzhiyun	};
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun	vtt_fixed: fixedregulator@1 {
41*4882a593Smuzhiyun		compatible = "regulator-fixed";
42*4882a593Smuzhiyun		regulator-name = "vtt";
43*4882a593Smuzhiyun		regulator-min-microvolt = <1500000>;
44*4882a593Smuzhiyun		regulator-max-microvolt = <1500000>;
45*4882a593Smuzhiyun		gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
46*4882a593Smuzhiyun		regulator-always-on;
47*4882a593Smuzhiyun		regulator-boot-on;
48*4882a593Smuzhiyun		enable-active-high;
49*4882a593Smuzhiyun	};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun	leds@0 {
52*4882a593Smuzhiyun		compatible = "gpio-leds";
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun		led@0 {
55*4882a593Smuzhiyun			label = "out0";
56*4882a593Smuzhiyun			gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
57*4882a593Smuzhiyun			default-state = "off";
58*4882a593Smuzhiyun		};
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun		led@1 {
61*4882a593Smuzhiyun			label = "out1";
62*4882a593Smuzhiyun			gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
63*4882a593Smuzhiyun			default-state = "off";
64*4882a593Smuzhiyun		};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun		led@2 {
67*4882a593Smuzhiyun			label = "out2";
68*4882a593Smuzhiyun			gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
69*4882a593Smuzhiyun			default-state = "off";
70*4882a593Smuzhiyun		};
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun		led@3 {
73*4882a593Smuzhiyun			label = "out3";
74*4882a593Smuzhiyun			gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
75*4882a593Smuzhiyun			default-state = "off";
76*4882a593Smuzhiyun		};
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun		led@4 {
79*4882a593Smuzhiyun			label = "out4";
80*4882a593Smuzhiyun			gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
81*4882a593Smuzhiyun			default-state = "off";
82*4882a593Smuzhiyun		};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun		led@5 {
85*4882a593Smuzhiyun			label = "out5";
86*4882a593Smuzhiyun			gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
87*4882a593Smuzhiyun			default-state = "off";
88*4882a593Smuzhiyun		};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun		led@6 {
91*4882a593Smuzhiyun			label = "out6";
92*4882a593Smuzhiyun			gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
93*4882a593Smuzhiyun			default-state = "off";
94*4882a593Smuzhiyun		};
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun		led@7 {
97*4882a593Smuzhiyun			label = "out7";
98*4882a593Smuzhiyun			gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
99*4882a593Smuzhiyun			default-state = "off";
100*4882a593Smuzhiyun		};
101*4882a593Smuzhiyun	};
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun	/* Tricolor status LEDs */
104*4882a593Smuzhiyun	leds@1 {
105*4882a593Smuzhiyun		compatible = "gpio-leds";
106*4882a593Smuzhiyun		pinctrl-names = "default";
107*4882a593Smuzhiyun		pinctrl-0 = <&user_leds>;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun		led@0 {
110*4882a593Smuzhiyun			label = "status0:red:cpu0";
111*4882a593Smuzhiyun			gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
112*4882a593Smuzhiyun			default-state = "off";
113*4882a593Smuzhiyun			linux,default-trigger = "cpu0";
114*4882a593Smuzhiyun		};
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun		led@1 {
117*4882a593Smuzhiyun			label = "status0:green:usr";
118*4882a593Smuzhiyun			gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
119*4882a593Smuzhiyun			default-state = "off";
120*4882a593Smuzhiyun		};
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun		led@2 {
123*4882a593Smuzhiyun			label = "status0:yellow:usr";
124*4882a593Smuzhiyun			gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
125*4882a593Smuzhiyun			default-state = "off";
126*4882a593Smuzhiyun		};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun		led@3 {
129*4882a593Smuzhiyun			label = "status1:red:mmc0";
130*4882a593Smuzhiyun			gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
131*4882a593Smuzhiyun			default-state = "off";
132*4882a593Smuzhiyun			linux,default-trigger = "mmc0";
133*4882a593Smuzhiyun		};
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun		led@4 {
136*4882a593Smuzhiyun			label = "status1:green:usr";
137*4882a593Smuzhiyun			gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
138*4882a593Smuzhiyun			default-state = "off";
139*4882a593Smuzhiyun		};
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun		led@5 {
142*4882a593Smuzhiyun			label = "status1:yellow:usr";
143*4882a593Smuzhiyun			gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
144*4882a593Smuzhiyun			default-state = "off";
145*4882a593Smuzhiyun		};
146*4882a593Smuzhiyun	};
147*4882a593Smuzhiyun};
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun&am33xx_pinmux {
150*4882a593Smuzhiyun	user_leds: user_leds {
151*4882a593Smuzhiyun		pinctrl-single,pins = <
152*4882a593Smuzhiyun			AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
153*4882a593Smuzhiyun			AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
154*4882a593Smuzhiyun			AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
155*4882a593Smuzhiyun			AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */
156*4882a593Smuzhiyun			AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */
157*4882a593Smuzhiyun			AM33XX_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */
158*4882a593Smuzhiyun		>;
159*4882a593Smuzhiyun	};
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun	mmc0_pins_default: mmc0_pins_default {
162*4882a593Smuzhiyun		pinctrl-single,pins = <
163*4882a593Smuzhiyun			AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */
164*4882a593Smuzhiyun			AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */
165*4882a593Smuzhiyun			AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */
166*4882a593Smuzhiyun			AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */
167*4882a593Smuzhiyun			AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */
168*4882a593Smuzhiyun			AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */
169*4882a593Smuzhiyun			AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */
170*4882a593Smuzhiyun		>;
171*4882a593Smuzhiyun	};
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun	i2c0_pins_default: i2c0_pins_default {
174*4882a593Smuzhiyun		pinctrl-single,pins = <
175*4882a593Smuzhiyun			AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */
176*4882a593Smuzhiyun			AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */
177*4882a593Smuzhiyun		>;
178*4882a593Smuzhiyun	};
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun	spi0_pins_default: spi0_pins_default {
181*4882a593Smuzhiyun		pinctrl-single,pins = <
182*4882a593Smuzhiyun			AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */
183*4882a593Smuzhiyun			AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
184*4882a593Smuzhiyun			AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
185*4882a593Smuzhiyun			AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
186*4882a593Smuzhiyun		>;
187*4882a593Smuzhiyun	};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun	uart3_pins_default: uart3_pins_default {
190*4882a593Smuzhiyun		pinctrl-single,pins = <
191*4882a593Smuzhiyun			AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */
192*4882a593Smuzhiyun			AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
193*4882a593Smuzhiyun		>;
194*4882a593Smuzhiyun	};
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun	cpsw_default: cpsw_default {
197*4882a593Smuzhiyun		pinctrl-single,pins = <
198*4882a593Smuzhiyun			/* Slave 1, RMII mode */
199*4882a593Smuzhiyun			AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_crs.rmii1_crs_dv */
200*4882a593Smuzhiyun			AM33XX_IOPAD(0x944, (PIN_INPUT_PULLUP | MUX_MODE0))	/* rmii1_refclk.rmii1_refclk */
201*4882a593Smuzhiyun			AM33XX_IOPAD(0x940, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_rxd0.rmii1_rxd0 */
202*4882a593Smuzhiyun			AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_rxd1.rmii1_rxd1 */
203*4882a593Smuzhiyun			AM33XX_IOPAD(0x910, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_rxerr.rmii1_rxerr */
204*4882a593Smuzhiyun			AM33XX_IOPAD(0x928, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))	/* mii1_txd0.rmii1_txd0 */
205*4882a593Smuzhiyun			AM33XX_IOPAD(0x924, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))	/* mii1_txd1.rmii1_txd1 */
206*4882a593Smuzhiyun			AM33XX_IOPAD(0x914, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))	/* mii1_txen.rmii1_txen */
207*4882a593Smuzhiyun			/* Slave 2, RMII mode */
208*4882a593Smuzhiyun			AM33XX_IOPAD(0x870, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_wait0.rmii2_crs_dv */
209*4882a593Smuzhiyun			AM33XX_IOPAD(0x908, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_col.rmii2_refclk */
210*4882a593Smuzhiyun			AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_a11.rmii2_rxd0 */
211*4882a593Smuzhiyun			AM33XX_IOPAD(0x868, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_a10.rmii2_rxd1 */
212*4882a593Smuzhiyun			AM33XX_IOPAD(0x874, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_wpn.rmii2_rxerr */
213*4882a593Smuzhiyun			AM33XX_IOPAD(0x854, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))	/* gpmc_a5.rmii2_txd0 */
214*4882a593Smuzhiyun			AM33XX_IOPAD(0x850, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))	/* gpmc_a4.rmii2_txd1 */
215*4882a593Smuzhiyun			AM33XX_IOPAD(0x840, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))	/* gpmc_a0.rmii2_txen */
216*4882a593Smuzhiyun		>;
217*4882a593Smuzhiyun	};
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun	cpsw_sleep: cpsw_sleep {
220*4882a593Smuzhiyun		pinctrl-single,pins = <
221*4882a593Smuzhiyun			/* Slave 1 reset value */
222*4882a593Smuzhiyun			AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
223*4882a593Smuzhiyun			AM33XX_IOPAD(0x944, (PIN_INPUT_PULLDOWN | MUX_MODE7))
224*4882a593Smuzhiyun			AM33XX_IOPAD(0x940, (PIN_INPUT_PULLDOWN | MUX_MODE7))
225*4882a593Smuzhiyun			AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
226*4882a593Smuzhiyun			AM33XX_IOPAD(0x910, (PIN_INPUT_PULLDOWN | MUX_MODE7))
227*4882a593Smuzhiyun			AM33XX_IOPAD(0x928, (PIN_INPUT_PULLDOWN | MUX_MODE7))
228*4882a593Smuzhiyun			AM33XX_IOPAD(0x924, (PIN_INPUT_PULLDOWN | MUX_MODE7))
229*4882a593Smuzhiyun			AM33XX_IOPAD(0x914, (PIN_INPUT_PULLDOWN | MUX_MODE7))
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun			/* Slave 2 reset value */
232*4882a593Smuzhiyun			AM33XX_IOPAD(0x870, (PIN_INPUT_PULLDOWN | MUX_MODE7))
233*4882a593Smuzhiyun			AM33XX_IOPAD(0x908, (PIN_INPUT_PULLDOWN | MUX_MODE7))
234*4882a593Smuzhiyun			AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
235*4882a593Smuzhiyun			AM33XX_IOPAD(0x868, (PIN_INPUT_PULLDOWN | MUX_MODE7))
236*4882a593Smuzhiyun			AM33XX_IOPAD(0x874, (PIN_INPUT_PULLDOWN | MUX_MODE7))
237*4882a593Smuzhiyun			AM33XX_IOPAD(0x854, (PIN_INPUT_PULLDOWN | MUX_MODE7))
238*4882a593Smuzhiyun			AM33XX_IOPAD(0x850, (PIN_INPUT_PULLDOWN | MUX_MODE7))
239*4882a593Smuzhiyun			AM33XX_IOPAD(0x840, (PIN_INPUT_PULLDOWN | MUX_MODE7))
240*4882a593Smuzhiyun		>;
241*4882a593Smuzhiyun	};
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun	davinci_mdio_default: davinci_mdio_default {
244*4882a593Smuzhiyun		pinctrl-single,pins = <
245*4882a593Smuzhiyun			/* MDIO */
246*4882a593Smuzhiyun			AM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0))	/* mdio_data.mdio_data */
247*4882a593Smuzhiyun			AM33XX_IOPAD(0x94c, (PIN_OUTPUT_PULLUP | MUX_MODE0))			/* mdio_clk.mdio_clk */
248*4882a593Smuzhiyun		>;
249*4882a593Smuzhiyun	};
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun	davinci_mdio_sleep: davinci_mdio_sleep {
252*4882a593Smuzhiyun		pinctrl-single,pins = <
253*4882a593Smuzhiyun			/* MDIO reset value */
254*4882a593Smuzhiyun			AM33XX_IOPAD(0x948, (PIN_INPUT_PULLDOWN | MUX_MODE7))
255*4882a593Smuzhiyun			AM33XX_IOPAD(0x94c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
256*4882a593Smuzhiyun		>;
257*4882a593Smuzhiyun	};
258*4882a593Smuzhiyun};
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun&i2c0 {
261*4882a593Smuzhiyun	pinctrl-names = "default";
262*4882a593Smuzhiyun	pinctrl-0 = <&i2c0_pins_default>;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun	status = "okay";
265*4882a593Smuzhiyun	clock-frequency = <400000>;
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun	tps: power-controller@2d {
268*4882a593Smuzhiyun		reg = <0x2d>;
269*4882a593Smuzhiyun	};
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun	tpic2810: gpio@60 {
272*4882a593Smuzhiyun		compatible = "ti,tpic2810";
273*4882a593Smuzhiyun		reg = <0x60>;
274*4882a593Smuzhiyun		gpio-controller;
275*4882a593Smuzhiyun		#gpio-cells = <2>;
276*4882a593Smuzhiyun	};
277*4882a593Smuzhiyun};
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun#include "tps65910.dtsi"
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun&tps {
282*4882a593Smuzhiyun	vcc1-supply = <&vbat>;
283*4882a593Smuzhiyun	vcc2-supply = <&vbat>;
284*4882a593Smuzhiyun	vcc3-supply = <&vbat>;
285*4882a593Smuzhiyun	vcc4-supply = <&vbat>;
286*4882a593Smuzhiyun	vcc5-supply = <&vbat>;
287*4882a593Smuzhiyun	vcc6-supply = <&vbat>;
288*4882a593Smuzhiyun	vcc7-supply = <&vbat>;
289*4882a593Smuzhiyun	vccio-supply = <&vbat>;
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun	regulators {
292*4882a593Smuzhiyun		vrtc_reg: regulator@0 {
293*4882a593Smuzhiyun			regulator-always-on;
294*4882a593Smuzhiyun		};
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun		vio_reg: regulator@1 {
297*4882a593Smuzhiyun			regulator-always-on;
298*4882a593Smuzhiyun		};
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun		vdd1_reg: regulator@2 {
301*4882a593Smuzhiyun			regulator-name = "vdd_mpu";
302*4882a593Smuzhiyun			regulator-min-microvolt = <912500>;
303*4882a593Smuzhiyun			regulator-max-microvolt = <1326000>;
304*4882a593Smuzhiyun			regulator-boot-on;
305*4882a593Smuzhiyun			regulator-always-on;
306*4882a593Smuzhiyun		};
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun		vdd2_reg: regulator@3 {
309*4882a593Smuzhiyun			regulator-name = "vdd_core";
310*4882a593Smuzhiyun			regulator-min-microvolt = <912500>;
311*4882a593Smuzhiyun			regulator-max-microvolt = <1144000>;
312*4882a593Smuzhiyun			regulator-boot-on;
313*4882a593Smuzhiyun			regulator-always-on;
314*4882a593Smuzhiyun		};
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun		vdd3_reg: regulator@4 {
317*4882a593Smuzhiyun			regulator-always-on;
318*4882a593Smuzhiyun		};
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun		vdig1_reg: regulator@5 {
321*4882a593Smuzhiyun			regulator-always-on;
322*4882a593Smuzhiyun		};
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun		vdig2_reg: regulator@6 {
325*4882a593Smuzhiyun			regulator-always-on;
326*4882a593Smuzhiyun		};
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun		vpll_reg: regulator@7 {
329*4882a593Smuzhiyun			regulator-always-on;
330*4882a593Smuzhiyun		};
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun		vdac_reg: regulator@8 {
333*4882a593Smuzhiyun			regulator-always-on;
334*4882a593Smuzhiyun		};
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun		vaux1_reg: regulator@9 {
337*4882a593Smuzhiyun			regulator-always-on;
338*4882a593Smuzhiyun		};
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun		vaux2_reg: regulator@10 {
341*4882a593Smuzhiyun			regulator-always-on;
342*4882a593Smuzhiyun		};
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun		vaux33_reg: regulator@11 {
345*4882a593Smuzhiyun			regulator-always-on;
346*4882a593Smuzhiyun		};
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun		vmmc_reg: regulator@12 {
349*4882a593Smuzhiyun			regulator-min-microvolt = <1800000>;
350*4882a593Smuzhiyun			regulator-max-microvolt = <3300000>;
351*4882a593Smuzhiyun			regulator-always-on;
352*4882a593Smuzhiyun		};
353*4882a593Smuzhiyun	};
354*4882a593Smuzhiyun};
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun&mmc1 {
357*4882a593Smuzhiyun	status = "okay";
358*4882a593Smuzhiyun	vmmc-supply = <&vmmc_reg>;
359*4882a593Smuzhiyun	bus-width = <4>;
360*4882a593Smuzhiyun	pinctrl-names = "default";
361*4882a593Smuzhiyun	pinctrl-0 = <&mmc0_pins_default>;
362*4882a593Smuzhiyun};
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun&gpio0 {
365*4882a593Smuzhiyun	/* Do not idle the GPIO used for holding the VTT regulator */
366*4882a593Smuzhiyun	ti,no-reset-on-init;
367*4882a593Smuzhiyun	ti,no-idle-on-init;
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun	p7 {
370*4882a593Smuzhiyun		gpio-hog;
371*4882a593Smuzhiyun		gpios = <7 GPIO_ACTIVE_HIGH>;
372*4882a593Smuzhiyun		output-high;
373*4882a593Smuzhiyun		line-name = "FET_SWITCH_CTRL";
374*4882a593Smuzhiyun	};
375*4882a593Smuzhiyun};
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun&uart3 {
378*4882a593Smuzhiyun	pinctrl-names = "default";
379*4882a593Smuzhiyun	pinctrl-0 = <&uart3_pins_default>;
380*4882a593Smuzhiyun	status = "okay";
381*4882a593Smuzhiyun};
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun&gpio3 {
384*4882a593Smuzhiyun	p4 {
385*4882a593Smuzhiyun		gpio-hog;
386*4882a593Smuzhiyun		gpios = <4 GPIO_ACTIVE_HIGH>;
387*4882a593Smuzhiyun		output-high;
388*4882a593Smuzhiyun		line-name = "PR1_MII_CTRL";
389*4882a593Smuzhiyun	};
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun	p10 {
392*4882a593Smuzhiyun		gpio-hog;
393*4882a593Smuzhiyun		gpios = <10 GPIO_ACTIVE_HIGH>;
394*4882a593Smuzhiyun		output-high;
395*4882a593Smuzhiyun		line-name = "MUX_MII_CTRL";
396*4882a593Smuzhiyun	};
397*4882a593Smuzhiyun};
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun&cpsw_emac0 {
400*4882a593Smuzhiyun	phy_id = <&davinci_mdio>, <1>;
401*4882a593Smuzhiyun	phy-mode = "rmii";
402*4882a593Smuzhiyun	dual_emac_res_vlan = <1>;
403*4882a593Smuzhiyun};
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun&cpsw_emac1 {
406*4882a593Smuzhiyun	phy_id = <&davinci_mdio>, <3>;
407*4882a593Smuzhiyun	phy-mode = "rmii";
408*4882a593Smuzhiyun	dual_emac_res_vlan = <2>;
409*4882a593Smuzhiyun};
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun&mac {
412*4882a593Smuzhiyun	pinctrl-names = "default", "sleep";
413*4882a593Smuzhiyun	pinctrl-0 = <&cpsw_default>;
414*4882a593Smuzhiyun	pinctrl-1 = <&cpsw_sleep>;
415*4882a593Smuzhiyun	status = "okay";
416*4882a593Smuzhiyun	dual_emac;
417*4882a593Smuzhiyun};
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun&phy_sel {
420*4882a593Smuzhiyun	rmii-clock-ext;
421*4882a593Smuzhiyun};
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun&davinci_mdio {
424*4882a593Smuzhiyun	pinctrl-names = "default", "sleep";
425*4882a593Smuzhiyun	pinctrl-0 = <&davinci_mdio_default>;
426*4882a593Smuzhiyun	pinctrl-1 = <&davinci_mdio_sleep>;
427*4882a593Smuzhiyun	status = "okay";
428*4882a593Smuzhiyun	reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
429*4882a593Smuzhiyun	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
430*4882a593Smuzhiyun};
431