1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/arm/hisilicon/controller/hi3798cv200-perictrl.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Hisilicon Hi3798CV200 Peripheral Controller
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Wei Xu <xuwei5@hisilicon.com>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyundescription: |
13*4882a593Smuzhiyun  The Hi3798CV200 Peripheral Controller controls peripherals, queries
14*4882a593Smuzhiyun  their status, and configures some functions of peripherals.
15*4882a593Smuzhiyun
16*4882a593Smuzhiyunproperties:
17*4882a593Smuzhiyun  compatible:
18*4882a593Smuzhiyun    items:
19*4882a593Smuzhiyun      - const: hisilicon,hi3798cv200-perictrl
20*4882a593Smuzhiyun      - const: syscon
21*4882a593Smuzhiyun      - const: simple-mfd
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun  reg:
24*4882a593Smuzhiyun    maxItems: 1
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun  "#address-cells":
27*4882a593Smuzhiyun    const: 1
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun  "#size-cells":
30*4882a593Smuzhiyun    const: 1
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun  ranges: true
33*4882a593Smuzhiyun
34*4882a593Smuzhiyunrequired:
35*4882a593Smuzhiyun  - compatible
36*4882a593Smuzhiyun  - reg
37*4882a593Smuzhiyun  - "#address-cells"
38*4882a593Smuzhiyun  - "#size-cells"
39*4882a593Smuzhiyun  - ranges
40*4882a593Smuzhiyun
41*4882a593SmuzhiyunadditionalProperties:
42*4882a593Smuzhiyun  type: object
43*4882a593Smuzhiyun
44*4882a593Smuzhiyunexamples:
45*4882a593Smuzhiyun  - |
46*4882a593Smuzhiyun    peripheral-controller@8a20000 {
47*4882a593Smuzhiyun        compatible = "hisilicon,hi3798cv200-perictrl", "syscon", "simple-mfd";
48*4882a593Smuzhiyun        reg = <0x8a20000 0x1000>;
49*4882a593Smuzhiyun        #address-cells = <1>;
50*4882a593Smuzhiyun        #size-cells = <1>;
51*4882a593Smuzhiyun        ranges = <0x0 0x8a20000 0x1000>;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun        phy@850 {
54*4882a593Smuzhiyun            compatible = "hisilicon,hi3798cv200-combphy";
55*4882a593Smuzhiyun            reg = <0x850 0x8>;
56*4882a593Smuzhiyun            #phy-cells = <1>;
57*4882a593Smuzhiyun            clocks = <&crg 42>;
58*4882a593Smuzhiyun            resets = <&crg 0x188 4>;
59*4882a593Smuzhiyun            assigned-clocks = <&crg 42>;
60*4882a593Smuzhiyun            assigned-clock-rates = <100000000>;
61*4882a593Smuzhiyun            hisilicon,fixed-mode = <4>;
62*4882a593Smuzhiyun        };
63*4882a593Smuzhiyun    };
64*4882a593Smuzhiyun...
65