Lines Matching +full:0 +full:x850
30 { P_BI_TCXO, 0 },
46 .l = 0x10,
47 .alpha = 0xaaab,
51 .offset = 0x42c,
64 F(100000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0),
65 F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
66 F(330000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
67 F(404000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
68 F(444000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
69 F(533000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
74 .cmd_rcgr = 0x7f0,
75 .mnd_width = 0,
89 .halt_reg = 0x990,
92 .enable_reg = 0x990,
93 .enable_mask = BIT(0),
102 .halt_reg = 0x9f0,
105 .enable_reg = 0x9f0,
106 .enable_mask = BIT(0),
115 .halt_reg = 0x970,
118 .enable_reg = 0x970,
119 .enable_mask = BIT(0),
128 .halt_reg = 0x9d0,
131 .enable_reg = 0x9d0,
132 .enable_mask = BIT(0),
141 .halt_reg = 0x930,
144 .enable_reg = 0x930,
145 .enable_mask = BIT(0),
154 .halt_reg = 0x890,
157 .enable_reg = 0x890,
158 .enable_mask = BIT(0),
172 .halt_reg = 0x950,
175 .enable_reg = 0x950,
176 .enable_mask = BIT(0),
185 .halt_reg = 0x8d0,
188 .enable_reg = 0x8d0,
189 .enable_mask = BIT(0),
203 .halt_reg = 0x9b0,
206 .enable_reg = 0x9b0,
207 .enable_mask = BIT(0),
216 .halt_reg = 0x910,
219 .enable_reg = 0x910,
220 .enable_mask = BIT(0),
229 .halt_reg = 0x850,
232 .enable_reg = 0x850,
233 .enable_mask = BIT(0),
247 .gdscr = 0x814,
251 .cxcs = (unsigned int []){ 0x850, 0x910 },
258 .gdscr = 0x874,
262 .cxcs = (unsigned int []){ 0x890, 0x930 },
269 .gdscr = 0x8b4,
273 .cxcs = (unsigned int []){ 0x8d0, 0x950 },
305 .max_register = 0xb90,