1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 5*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 6*4882a593Smuzhiyun * published by the Free Software Foundation. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/* 10*4882a593Smuzhiyun * AM335x Starter Kit 11*4882a593Smuzhiyun * http://www.ti.com/tool/tmdssk3358 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/dts-v1/; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun#include "am33xx.dtsi" 17*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h> 18*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun/ { 21*4882a593Smuzhiyun model = "TI AM335x EVM-SK"; 22*4882a593Smuzhiyun compatible = "ti,am335x-evmsk", "ti,am33xx"; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun chosen { 25*4882a593Smuzhiyun stdout-path = &uart0; 26*4882a593Smuzhiyun tick-timer = &timer2; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun cpus { 30*4882a593Smuzhiyun cpu@0 { 31*4882a593Smuzhiyun cpu0-supply = <&vdd1_reg>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun memory { 36*4882a593Smuzhiyun device_type = "memory"; 37*4882a593Smuzhiyun reg = <0x80000000 0x10000000>; /* 256 MB */ 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun vbat: fixedregulator@0 { 41*4882a593Smuzhiyun compatible = "regulator-fixed"; 42*4882a593Smuzhiyun regulator-name = "vbat"; 43*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 44*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 45*4882a593Smuzhiyun regulator-boot-on; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun lis3_reg: fixedregulator@1 { 49*4882a593Smuzhiyun compatible = "regulator-fixed"; 50*4882a593Smuzhiyun regulator-name = "lis3_reg"; 51*4882a593Smuzhiyun regulator-boot-on; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun wl12xx_vmmc: fixedregulator@2 { 55*4882a593Smuzhiyun pinctrl-names = "default"; 56*4882a593Smuzhiyun pinctrl-0 = <&wl12xx_gpio>; 57*4882a593Smuzhiyun compatible = "regulator-fixed"; 58*4882a593Smuzhiyun regulator-name = "vwl1271"; 59*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 60*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 61*4882a593Smuzhiyun gpio = <&gpio1 29 0>; 62*4882a593Smuzhiyun startup-delay-us = <70000>; 63*4882a593Smuzhiyun enable-active-high; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun vtt_fixed: fixedregulator@3 { 67*4882a593Smuzhiyun compatible = "regulator-fixed"; 68*4882a593Smuzhiyun regulator-name = "vtt"; 69*4882a593Smuzhiyun regulator-min-microvolt = <1500000>; 70*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 71*4882a593Smuzhiyun gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>; 72*4882a593Smuzhiyun regulator-always-on; 73*4882a593Smuzhiyun regulator-boot-on; 74*4882a593Smuzhiyun enable-active-high; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun leds { 78*4882a593Smuzhiyun pinctrl-names = "default"; 79*4882a593Smuzhiyun pinctrl-0 = <&user_leds_s0>; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun compatible = "gpio-leds"; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun led@1 { 84*4882a593Smuzhiyun label = "evmsk:green:usr0"; 85*4882a593Smuzhiyun gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 86*4882a593Smuzhiyun default-state = "off"; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun led@2 { 90*4882a593Smuzhiyun label = "evmsk:green:usr1"; 91*4882a593Smuzhiyun gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; 92*4882a593Smuzhiyun default-state = "off"; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun led@3 { 96*4882a593Smuzhiyun label = "evmsk:green:mmc0"; 97*4882a593Smuzhiyun gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 98*4882a593Smuzhiyun linux,default-trigger = "mmc0"; 99*4882a593Smuzhiyun default-state = "off"; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun led@4 { 103*4882a593Smuzhiyun label = "evmsk:green:heartbeat"; 104*4882a593Smuzhiyun gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 105*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 106*4882a593Smuzhiyun default-state = "off"; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun gpio_buttons: gpio_buttons@0 { 111*4882a593Smuzhiyun compatible = "gpio-keys"; 112*4882a593Smuzhiyun #address-cells = <1>; 113*4882a593Smuzhiyun #size-cells = <0>; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun switch@1 { 116*4882a593Smuzhiyun label = "button0"; 117*4882a593Smuzhiyun linux,code = <0x100>; 118*4882a593Smuzhiyun gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun switch@2 { 122*4882a593Smuzhiyun label = "button1"; 123*4882a593Smuzhiyun linux,code = <0x101>; 124*4882a593Smuzhiyun gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun switch@3 { 128*4882a593Smuzhiyun label = "button2"; 129*4882a593Smuzhiyun linux,code = <0x102>; 130*4882a593Smuzhiyun gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; 131*4882a593Smuzhiyun wakeup-source; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun switch@4 { 135*4882a593Smuzhiyun label = "button3"; 136*4882a593Smuzhiyun linux,code = <0x103>; 137*4882a593Smuzhiyun gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun backlight { 142*4882a593Smuzhiyun compatible = "pwm-backlight"; 143*4882a593Smuzhiyun pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>; 144*4882a593Smuzhiyun brightness-levels = <0 58 61 66 75 90 125 170 255>; 145*4882a593Smuzhiyun default-brightness-level = <8>; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun sound { 149*4882a593Smuzhiyun compatible = "simple-audio-card"; 150*4882a593Smuzhiyun simple-audio-card,name = "AM335x-EVMSK"; 151*4882a593Smuzhiyun simple-audio-card,widgets = 152*4882a593Smuzhiyun "Headphone", "Headphone Jack"; 153*4882a593Smuzhiyun simple-audio-card,routing = 154*4882a593Smuzhiyun "Headphone Jack", "HPLOUT", 155*4882a593Smuzhiyun "Headphone Jack", "HPROUT"; 156*4882a593Smuzhiyun simple-audio-card,format = "dsp_b"; 157*4882a593Smuzhiyun simple-audio-card,bitclock-master = <&sound_master>; 158*4882a593Smuzhiyun simple-audio-card,frame-master = <&sound_master>; 159*4882a593Smuzhiyun simple-audio-card,bitclock-inversion; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun simple-audio-card,cpu { 162*4882a593Smuzhiyun sound-dai = <&mcasp1>; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun sound_master: simple-audio-card,codec { 166*4882a593Smuzhiyun sound-dai = <&tlv320aic3106>; 167*4882a593Smuzhiyun system-clock-frequency = <24000000>; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun }; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun panel { 172*4882a593Smuzhiyun compatible = "ti,tilcdc,panel"; 173*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 174*4882a593Smuzhiyun pinctrl-0 = <&lcd_pins_default>; 175*4882a593Smuzhiyun pinctrl-1 = <&lcd_pins_sleep>; 176*4882a593Smuzhiyun status = "okay"; 177*4882a593Smuzhiyun panel-info { 178*4882a593Smuzhiyun ac-bias = <255>; 179*4882a593Smuzhiyun ac-bias-intrpt = <0>; 180*4882a593Smuzhiyun dma-burst-sz = <16>; 181*4882a593Smuzhiyun bpp = <32>; 182*4882a593Smuzhiyun fdd = <0x80>; 183*4882a593Smuzhiyun sync-edge = <0>; 184*4882a593Smuzhiyun sync-ctrl = <1>; 185*4882a593Smuzhiyun raster-order = <0>; 186*4882a593Smuzhiyun fifo-th = <0>; 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun display-timings { 189*4882a593Smuzhiyun 480x272 { 190*4882a593Smuzhiyun hactive = <480>; 191*4882a593Smuzhiyun vactive = <272>; 192*4882a593Smuzhiyun hback-porch = <43>; 193*4882a593Smuzhiyun hfront-porch = <8>; 194*4882a593Smuzhiyun hsync-len = <4>; 195*4882a593Smuzhiyun vback-porch = <12>; 196*4882a593Smuzhiyun vfront-porch = <4>; 197*4882a593Smuzhiyun vsync-len = <10>; 198*4882a593Smuzhiyun clock-frequency = <9000000>; 199*4882a593Smuzhiyun hsync-active = <0>; 200*4882a593Smuzhiyun vsync-active = <0>; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun }; 203*4882a593Smuzhiyun }; 204*4882a593Smuzhiyun}; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun&am33xx_pinmux { 207*4882a593Smuzhiyun pinctrl-names = "default"; 208*4882a593Smuzhiyun pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun lcd_pins_default: lcd_pins_default { 211*4882a593Smuzhiyun pinctrl-single,pins = < 212*4882a593Smuzhiyun AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ 213*4882a593Smuzhiyun AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */ 214*4882a593Smuzhiyun AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */ 215*4882a593Smuzhiyun AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */ 216*4882a593Smuzhiyun AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */ 217*4882a593Smuzhiyun AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */ 218*4882a593Smuzhiyun AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */ 219*4882a593Smuzhiyun AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */ 220*4882a593Smuzhiyun AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ 221*4882a593Smuzhiyun AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ 222*4882a593Smuzhiyun AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ 223*4882a593Smuzhiyun AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ 224*4882a593Smuzhiyun AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ 225*4882a593Smuzhiyun AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ 226*4882a593Smuzhiyun AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ 227*4882a593Smuzhiyun AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ 228*4882a593Smuzhiyun AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ 229*4882a593Smuzhiyun AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ 230*4882a593Smuzhiyun AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ 231*4882a593Smuzhiyun AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ 232*4882a593Smuzhiyun AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ 233*4882a593Smuzhiyun AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ 234*4882a593Smuzhiyun AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ 235*4882a593Smuzhiyun AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ 236*4882a593Smuzhiyun AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ 237*4882a593Smuzhiyun AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ 238*4882a593Smuzhiyun AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ 239*4882a593Smuzhiyun AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ 240*4882a593Smuzhiyun >; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun lcd_pins_sleep: lcd_pins_sleep { 244*4882a593Smuzhiyun pinctrl-single,pins = < 245*4882a593Smuzhiyun AM33XX_IOPAD(0x820, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23 */ 246*4882a593Smuzhiyun AM33XX_IOPAD(0x824, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22 */ 247*4882a593Smuzhiyun AM33XX_IOPAD(0x828, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21 */ 248*4882a593Smuzhiyun AM33XX_IOPAD(0x82c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20 */ 249*4882a593Smuzhiyun AM33XX_IOPAD(0x830, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19 */ 250*4882a593Smuzhiyun AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18 */ 251*4882a593Smuzhiyun AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17 */ 252*4882a593Smuzhiyun AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16 */ 253*4882a593Smuzhiyun AM33XX_IOPAD(0x8a0, PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0 */ 254*4882a593Smuzhiyun AM33XX_IOPAD(0x8a4, PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1 */ 255*4882a593Smuzhiyun AM33XX_IOPAD(0x8a8, PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2 */ 256*4882a593Smuzhiyun AM33XX_IOPAD(0x8ac, PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3 */ 257*4882a593Smuzhiyun AM33XX_IOPAD(0x8b0, PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4 */ 258*4882a593Smuzhiyun AM33XX_IOPAD(0x8b4, PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5 */ 259*4882a593Smuzhiyun AM33XX_IOPAD(0x8b8, PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6 */ 260*4882a593Smuzhiyun AM33XX_IOPAD(0x8bc, PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7 */ 261*4882a593Smuzhiyun AM33XX_IOPAD(0x8c0, PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8 */ 262*4882a593Smuzhiyun AM33XX_IOPAD(0x8c4, PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9 */ 263*4882a593Smuzhiyun AM33XX_IOPAD(0x8c8, PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10 */ 264*4882a593Smuzhiyun AM33XX_IOPAD(0x8cc, PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11 */ 265*4882a593Smuzhiyun AM33XX_IOPAD(0x8d0, PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12 */ 266*4882a593Smuzhiyun AM33XX_IOPAD(0x8d4, PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13 */ 267*4882a593Smuzhiyun AM33XX_IOPAD(0x8d8, PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14 */ 268*4882a593Smuzhiyun AM33XX_IOPAD(0x8dc, PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15 */ 269*4882a593Smuzhiyun AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync */ 270*4882a593Smuzhiyun AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync */ 271*4882a593Smuzhiyun AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk */ 272*4882a593Smuzhiyun AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en */ 273*4882a593Smuzhiyun >; 274*4882a593Smuzhiyun }; 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun user_leds_s0: user_leds_s0 { 278*4882a593Smuzhiyun pinctrl-single,pins = < 279*4882a593Smuzhiyun AM33XX_IOPAD(0x810, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ 280*4882a593Smuzhiyun AM33XX_IOPAD(0x814, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */ 281*4882a593Smuzhiyun AM33XX_IOPAD(0x818, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */ 282*4882a593Smuzhiyun AM33XX_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */ 283*4882a593Smuzhiyun >; 284*4882a593Smuzhiyun }; 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun gpio_keys_s0: gpio_keys_s0 { 287*4882a593Smuzhiyun pinctrl-single,pins = < 288*4882a593Smuzhiyun AM33XX_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ 289*4882a593Smuzhiyun AM33XX_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ 290*4882a593Smuzhiyun AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */ 291*4882a593Smuzhiyun AM33XX_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ 292*4882a593Smuzhiyun >; 293*4882a593Smuzhiyun }; 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun i2c0_pins: pinmux_i2c0_pins { 296*4882a593Smuzhiyun pinctrl-single,pins = < 297*4882a593Smuzhiyun AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ 298*4882a593Smuzhiyun AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 299*4882a593Smuzhiyun >; 300*4882a593Smuzhiyun }; 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun uart0_pins: pinmux_uart0_pins { 303*4882a593Smuzhiyun pinctrl-single,pins = < 304*4882a593Smuzhiyun AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ 305*4882a593Smuzhiyun AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ 306*4882a593Smuzhiyun >; 307*4882a593Smuzhiyun }; 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun clkout2_pin: pinmux_clkout2_pin { 310*4882a593Smuzhiyun pinctrl-single,pins = < 311*4882a593Smuzhiyun AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ 312*4882a593Smuzhiyun >; 313*4882a593Smuzhiyun }; 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun ecap2_pins: backlight_pins { 316*4882a593Smuzhiyun pinctrl-single,pins = < 317*4882a593Smuzhiyun AM33XX_IOPAD(0x99c, MUX_MODE4) /* mcasp0_ahclkr.ecap2_in_pwm2_out */ 318*4882a593Smuzhiyun >; 319*4882a593Smuzhiyun }; 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun cpsw_default: cpsw_default { 322*4882a593Smuzhiyun pinctrl-single,pins = < 323*4882a593Smuzhiyun /* Slave 1 */ 324*4882a593Smuzhiyun AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ 325*4882a593Smuzhiyun AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ 326*4882a593Smuzhiyun AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ 327*4882a593Smuzhiyun AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ 328*4882a593Smuzhiyun AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ 329*4882a593Smuzhiyun AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ 330*4882a593Smuzhiyun AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ 331*4882a593Smuzhiyun AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ 332*4882a593Smuzhiyun AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ 333*4882a593Smuzhiyun AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ 334*4882a593Smuzhiyun AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ 335*4882a593Smuzhiyun AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun /* Slave 2 */ 338*4882a593Smuzhiyun AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ 339*4882a593Smuzhiyun AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ 340*4882a593Smuzhiyun AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ 341*4882a593Smuzhiyun AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ 342*4882a593Smuzhiyun AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ 343*4882a593Smuzhiyun AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ 344*4882a593Smuzhiyun AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ 345*4882a593Smuzhiyun AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ 346*4882a593Smuzhiyun AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ 347*4882a593Smuzhiyun AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ 348*4882a593Smuzhiyun AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ 349*4882a593Smuzhiyun AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ 350*4882a593Smuzhiyun >; 351*4882a593Smuzhiyun }; 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun cpsw_sleep: cpsw_sleep { 354*4882a593Smuzhiyun pinctrl-single,pins = < 355*4882a593Smuzhiyun /* Slave 1 reset value */ 356*4882a593Smuzhiyun AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) 357*4882a593Smuzhiyun AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) 358*4882a593Smuzhiyun AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) 359*4882a593Smuzhiyun AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) 360*4882a593Smuzhiyun AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) 361*4882a593Smuzhiyun AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) 362*4882a593Smuzhiyun AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) 363*4882a593Smuzhiyun AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) 364*4882a593Smuzhiyun AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) 365*4882a593Smuzhiyun AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) 366*4882a593Smuzhiyun AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) 367*4882a593Smuzhiyun AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun /* Slave 2 reset value*/ 370*4882a593Smuzhiyun AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) 371*4882a593Smuzhiyun AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) 372*4882a593Smuzhiyun AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) 373*4882a593Smuzhiyun AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) 374*4882a593Smuzhiyun AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) 375*4882a593Smuzhiyun AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) 376*4882a593Smuzhiyun AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) 377*4882a593Smuzhiyun AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7) 378*4882a593Smuzhiyun AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) 379*4882a593Smuzhiyun AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) 380*4882a593Smuzhiyun AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) 381*4882a593Smuzhiyun AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) 382*4882a593Smuzhiyun >; 383*4882a593Smuzhiyun }; 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun davinci_mdio_default: davinci_mdio_default { 386*4882a593Smuzhiyun pinctrl-single,pins = < 387*4882a593Smuzhiyun /* MDIO */ 388*4882a593Smuzhiyun AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 389*4882a593Smuzhiyun AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 390*4882a593Smuzhiyun >; 391*4882a593Smuzhiyun }; 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun davinci_mdio_sleep: davinci_mdio_sleep { 394*4882a593Smuzhiyun pinctrl-single,pins = < 395*4882a593Smuzhiyun /* MDIO reset value */ 396*4882a593Smuzhiyun AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) 397*4882a593Smuzhiyun AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) 398*4882a593Smuzhiyun >; 399*4882a593Smuzhiyun }; 400*4882a593Smuzhiyun 401*4882a593Smuzhiyun mmc1_pins: pinmux_mmc1_pins { 402*4882a593Smuzhiyun pinctrl-single,pins = < 403*4882a593Smuzhiyun AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ 404*4882a593Smuzhiyun >; 405*4882a593Smuzhiyun }; 406*4882a593Smuzhiyun 407*4882a593Smuzhiyun mcasp1_pins: mcasp1_pins { 408*4882a593Smuzhiyun pinctrl-single,pins = < 409*4882a593Smuzhiyun AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ 410*4882a593Smuzhiyun AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ 411*4882a593Smuzhiyun AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ 412*4882a593Smuzhiyun AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ 413*4882a593Smuzhiyun >; 414*4882a593Smuzhiyun }; 415*4882a593Smuzhiyun 416*4882a593Smuzhiyun mcasp1_pins_sleep: mcasp1_pins_sleep { 417*4882a593Smuzhiyun pinctrl-single,pins = < 418*4882a593Smuzhiyun AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) 419*4882a593Smuzhiyun AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) 420*4882a593Smuzhiyun AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) 421*4882a593Smuzhiyun AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) 422*4882a593Smuzhiyun >; 423*4882a593Smuzhiyun }; 424*4882a593Smuzhiyun 425*4882a593Smuzhiyun mmc2_pins: pinmux_mmc2_pins { 426*4882a593Smuzhiyun pinctrl-single,pins = < 427*4882a593Smuzhiyun AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ 428*4882a593Smuzhiyun AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ 429*4882a593Smuzhiyun AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ 430*4882a593Smuzhiyun AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ 431*4882a593Smuzhiyun AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ 432*4882a593Smuzhiyun AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ 433*4882a593Smuzhiyun AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ 434*4882a593Smuzhiyun >; 435*4882a593Smuzhiyun }; 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun wl12xx_gpio: pinmux_wl12xx_gpio { 438*4882a593Smuzhiyun pinctrl-single,pins = < 439*4882a593Smuzhiyun AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */ 440*4882a593Smuzhiyun >; 441*4882a593Smuzhiyun }; 442*4882a593Smuzhiyun}; 443*4882a593Smuzhiyun 444*4882a593Smuzhiyun&uart0 { 445*4882a593Smuzhiyun pinctrl-names = "default"; 446*4882a593Smuzhiyun pinctrl-0 = <&uart0_pins>; 447*4882a593Smuzhiyun 448*4882a593Smuzhiyun status = "okay"; 449*4882a593Smuzhiyun}; 450*4882a593Smuzhiyun 451*4882a593Smuzhiyun&i2c0 { 452*4882a593Smuzhiyun pinctrl-names = "default"; 453*4882a593Smuzhiyun pinctrl-0 = <&i2c0_pins>; 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun status = "okay"; 456*4882a593Smuzhiyun clock-frequency = <400000>; 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun tps: tps@2d { 459*4882a593Smuzhiyun reg = <0x2d>; 460*4882a593Smuzhiyun }; 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun lis331dlh: lis331dlh@18 { 463*4882a593Smuzhiyun compatible = "st,lis331dlh", "st,lis3lv02d"; 464*4882a593Smuzhiyun reg = <0x18>; 465*4882a593Smuzhiyun Vdd-supply = <&lis3_reg>; 466*4882a593Smuzhiyun Vdd_IO-supply = <&lis3_reg>; 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun st,click-single-x; 469*4882a593Smuzhiyun st,click-single-y; 470*4882a593Smuzhiyun st,click-single-z; 471*4882a593Smuzhiyun st,click-thresh-x = <10>; 472*4882a593Smuzhiyun st,click-thresh-y = <10>; 473*4882a593Smuzhiyun st,click-thresh-z = <10>; 474*4882a593Smuzhiyun st,irq1-click; 475*4882a593Smuzhiyun st,irq2-click; 476*4882a593Smuzhiyun st,wakeup-x-lo; 477*4882a593Smuzhiyun st,wakeup-x-hi; 478*4882a593Smuzhiyun st,wakeup-y-lo; 479*4882a593Smuzhiyun st,wakeup-y-hi; 480*4882a593Smuzhiyun st,wakeup-z-lo; 481*4882a593Smuzhiyun st,wakeup-z-hi; 482*4882a593Smuzhiyun st,min-limit-x = <120>; 483*4882a593Smuzhiyun st,min-limit-y = <120>; 484*4882a593Smuzhiyun st,min-limit-z = <140>; 485*4882a593Smuzhiyun st,max-limit-x = <550>; 486*4882a593Smuzhiyun st,max-limit-y = <550>; 487*4882a593Smuzhiyun st,max-limit-z = <750>; 488*4882a593Smuzhiyun }; 489*4882a593Smuzhiyun 490*4882a593Smuzhiyun tlv320aic3106: tlv320aic3106@1b { 491*4882a593Smuzhiyun #sound-dai-cells = <0>; 492*4882a593Smuzhiyun compatible = "ti,tlv320aic3106"; 493*4882a593Smuzhiyun reg = <0x1b>; 494*4882a593Smuzhiyun status = "okay"; 495*4882a593Smuzhiyun 496*4882a593Smuzhiyun /* Regulators */ 497*4882a593Smuzhiyun AVDD-supply = <&vaux2_reg>; 498*4882a593Smuzhiyun IOVDD-supply = <&vaux2_reg>; 499*4882a593Smuzhiyun DRVDD-supply = <&vaux2_reg>; 500*4882a593Smuzhiyun DVDD-supply = <&vbat>; 501*4882a593Smuzhiyun }; 502*4882a593Smuzhiyun}; 503*4882a593Smuzhiyun 504*4882a593Smuzhiyun&usb { 505*4882a593Smuzhiyun status = "okay"; 506*4882a593Smuzhiyun}; 507*4882a593Smuzhiyun 508*4882a593Smuzhiyun&usb_ctrl_mod { 509*4882a593Smuzhiyun status = "okay"; 510*4882a593Smuzhiyun}; 511*4882a593Smuzhiyun 512*4882a593Smuzhiyun&usb0_phy { 513*4882a593Smuzhiyun status = "okay"; 514*4882a593Smuzhiyun}; 515*4882a593Smuzhiyun 516*4882a593Smuzhiyun&usb1_phy { 517*4882a593Smuzhiyun status = "okay"; 518*4882a593Smuzhiyun}; 519*4882a593Smuzhiyun 520*4882a593Smuzhiyun&usb0 { 521*4882a593Smuzhiyun status = "okay"; 522*4882a593Smuzhiyun}; 523*4882a593Smuzhiyun 524*4882a593Smuzhiyun&usb1 { 525*4882a593Smuzhiyun status = "okay"; 526*4882a593Smuzhiyun dr_mode = "host"; 527*4882a593Smuzhiyun}; 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun&cppi41dma { 530*4882a593Smuzhiyun status = "okay"; 531*4882a593Smuzhiyun}; 532*4882a593Smuzhiyun 533*4882a593Smuzhiyun&epwmss2 { 534*4882a593Smuzhiyun status = "okay"; 535*4882a593Smuzhiyun 536*4882a593Smuzhiyun ecap2: ecap@48304100 { 537*4882a593Smuzhiyun status = "okay"; 538*4882a593Smuzhiyun pinctrl-names = "default"; 539*4882a593Smuzhiyun pinctrl-0 = <&ecap2_pins>; 540*4882a593Smuzhiyun }; 541*4882a593Smuzhiyun}; 542*4882a593Smuzhiyun 543*4882a593Smuzhiyun#include "tps65910.dtsi" 544*4882a593Smuzhiyun 545*4882a593Smuzhiyun&tps { 546*4882a593Smuzhiyun vcc1-supply = <&vbat>; 547*4882a593Smuzhiyun vcc2-supply = <&vbat>; 548*4882a593Smuzhiyun vcc3-supply = <&vbat>; 549*4882a593Smuzhiyun vcc4-supply = <&vbat>; 550*4882a593Smuzhiyun vcc5-supply = <&vbat>; 551*4882a593Smuzhiyun vcc6-supply = <&vbat>; 552*4882a593Smuzhiyun vcc7-supply = <&vbat>; 553*4882a593Smuzhiyun vccio-supply = <&vbat>; 554*4882a593Smuzhiyun 555*4882a593Smuzhiyun regulators { 556*4882a593Smuzhiyun vrtc_reg: regulator@0 { 557*4882a593Smuzhiyun regulator-always-on; 558*4882a593Smuzhiyun }; 559*4882a593Smuzhiyun 560*4882a593Smuzhiyun vio_reg: regulator@1 { 561*4882a593Smuzhiyun regulator-always-on; 562*4882a593Smuzhiyun }; 563*4882a593Smuzhiyun 564*4882a593Smuzhiyun vdd1_reg: regulator@2 { 565*4882a593Smuzhiyun /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ 566*4882a593Smuzhiyun regulator-name = "vdd_mpu"; 567*4882a593Smuzhiyun regulator-min-microvolt = <912500>; 568*4882a593Smuzhiyun regulator-max-microvolt = <1312500>; 569*4882a593Smuzhiyun regulator-boot-on; 570*4882a593Smuzhiyun regulator-always-on; 571*4882a593Smuzhiyun }; 572*4882a593Smuzhiyun 573*4882a593Smuzhiyun vdd2_reg: regulator@3 { 574*4882a593Smuzhiyun /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ 575*4882a593Smuzhiyun regulator-name = "vdd_core"; 576*4882a593Smuzhiyun regulator-min-microvolt = <912500>; 577*4882a593Smuzhiyun regulator-max-microvolt = <1150000>; 578*4882a593Smuzhiyun regulator-boot-on; 579*4882a593Smuzhiyun regulator-always-on; 580*4882a593Smuzhiyun }; 581*4882a593Smuzhiyun 582*4882a593Smuzhiyun vdd3_reg: regulator@4 { 583*4882a593Smuzhiyun regulator-always-on; 584*4882a593Smuzhiyun }; 585*4882a593Smuzhiyun 586*4882a593Smuzhiyun vdig1_reg: regulator@5 { 587*4882a593Smuzhiyun regulator-always-on; 588*4882a593Smuzhiyun }; 589*4882a593Smuzhiyun 590*4882a593Smuzhiyun vdig2_reg: regulator@6 { 591*4882a593Smuzhiyun regulator-always-on; 592*4882a593Smuzhiyun }; 593*4882a593Smuzhiyun 594*4882a593Smuzhiyun vpll_reg: regulator@7 { 595*4882a593Smuzhiyun regulator-always-on; 596*4882a593Smuzhiyun }; 597*4882a593Smuzhiyun 598*4882a593Smuzhiyun vdac_reg: regulator@8 { 599*4882a593Smuzhiyun regulator-always-on; 600*4882a593Smuzhiyun }; 601*4882a593Smuzhiyun 602*4882a593Smuzhiyun vaux1_reg: regulator@9 { 603*4882a593Smuzhiyun regulator-always-on; 604*4882a593Smuzhiyun }; 605*4882a593Smuzhiyun 606*4882a593Smuzhiyun vaux2_reg: regulator@10 { 607*4882a593Smuzhiyun regulator-always-on; 608*4882a593Smuzhiyun }; 609*4882a593Smuzhiyun 610*4882a593Smuzhiyun vaux33_reg: regulator@11 { 611*4882a593Smuzhiyun regulator-always-on; 612*4882a593Smuzhiyun }; 613*4882a593Smuzhiyun 614*4882a593Smuzhiyun vmmc_reg: regulator@12 { 615*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 616*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 617*4882a593Smuzhiyun regulator-always-on; 618*4882a593Smuzhiyun }; 619*4882a593Smuzhiyun }; 620*4882a593Smuzhiyun}; 621*4882a593Smuzhiyun 622*4882a593Smuzhiyun&mac { 623*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 624*4882a593Smuzhiyun pinctrl-0 = <&cpsw_default>; 625*4882a593Smuzhiyun pinctrl-1 = <&cpsw_sleep>; 626*4882a593Smuzhiyun dual_emac = <1>; 627*4882a593Smuzhiyun status = "okay"; 628*4882a593Smuzhiyun}; 629*4882a593Smuzhiyun 630*4882a593Smuzhiyun&davinci_mdio { 631*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 632*4882a593Smuzhiyun pinctrl-0 = <&davinci_mdio_default>; 633*4882a593Smuzhiyun pinctrl-1 = <&davinci_mdio_sleep>; 634*4882a593Smuzhiyun status = "okay"; 635*4882a593Smuzhiyun}; 636*4882a593Smuzhiyun 637*4882a593Smuzhiyun&cpsw_emac0 { 638*4882a593Smuzhiyun phy_id = <&davinci_mdio>, <0>; 639*4882a593Smuzhiyun phy-mode = "rgmii-txid"; 640*4882a593Smuzhiyun dual_emac_res_vlan = <1>; 641*4882a593Smuzhiyun}; 642*4882a593Smuzhiyun 643*4882a593Smuzhiyun&cpsw_emac1 { 644*4882a593Smuzhiyun phy_id = <&davinci_mdio>, <1>; 645*4882a593Smuzhiyun phy-mode = "rgmii-txid"; 646*4882a593Smuzhiyun dual_emac_res_vlan = <2>; 647*4882a593Smuzhiyun}; 648*4882a593Smuzhiyun 649*4882a593Smuzhiyun&mmc1 { 650*4882a593Smuzhiyun status = "okay"; 651*4882a593Smuzhiyun vmmc-supply = <&vmmc_reg>; 652*4882a593Smuzhiyun bus-width = <4>; 653*4882a593Smuzhiyun pinctrl-names = "default"; 654*4882a593Smuzhiyun pinctrl-0 = <&mmc1_pins>; 655*4882a593Smuzhiyun cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; 656*4882a593Smuzhiyun}; 657*4882a593Smuzhiyun 658*4882a593Smuzhiyun&sham { 659*4882a593Smuzhiyun status = "okay"; 660*4882a593Smuzhiyun}; 661*4882a593Smuzhiyun 662*4882a593Smuzhiyun&aes { 663*4882a593Smuzhiyun status = "okay"; 664*4882a593Smuzhiyun}; 665*4882a593Smuzhiyun 666*4882a593Smuzhiyun&gpio0 { 667*4882a593Smuzhiyun ti,no-reset-on-init; 668*4882a593Smuzhiyun}; 669*4882a593Smuzhiyun 670*4882a593Smuzhiyun&mmc2 { 671*4882a593Smuzhiyun status = "okay"; 672*4882a593Smuzhiyun vmmc-supply = <&wl12xx_vmmc>; 673*4882a593Smuzhiyun ti,non-removable; 674*4882a593Smuzhiyun bus-width = <4>; 675*4882a593Smuzhiyun cap-power-off-card; 676*4882a593Smuzhiyun pinctrl-names = "default"; 677*4882a593Smuzhiyun pinctrl-0 = <&mmc2_pins>; 678*4882a593Smuzhiyun 679*4882a593Smuzhiyun #address-cells = <1>; 680*4882a593Smuzhiyun #size-cells = <0>; 681*4882a593Smuzhiyun wlcore: wlcore@2 { 682*4882a593Smuzhiyun compatible = "ti,wl1271"; 683*4882a593Smuzhiyun reg = <2>; 684*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 685*4882a593Smuzhiyun interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; /* gpio 31 */ 686*4882a593Smuzhiyun ref-clock-frequency = <38400000>; 687*4882a593Smuzhiyun }; 688*4882a593Smuzhiyun}; 689*4882a593Smuzhiyun 690*4882a593Smuzhiyun&mcasp1 { 691*4882a593Smuzhiyun #sound-dai-cells = <0>; 692*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 693*4882a593Smuzhiyun pinctrl-0 = <&mcasp1_pins>; 694*4882a593Smuzhiyun pinctrl-1 = <&mcasp1_pins_sleep>; 695*4882a593Smuzhiyun 696*4882a593Smuzhiyun status = "okay"; 697*4882a593Smuzhiyun 698*4882a593Smuzhiyun op-mode = <0>; /* MCASP_IIS_MODE */ 699*4882a593Smuzhiyun tdm-slots = <2>; 700*4882a593Smuzhiyun /* 4 serializers */ 701*4882a593Smuzhiyun serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 702*4882a593Smuzhiyun 0 0 1 2 703*4882a593Smuzhiyun >; 704*4882a593Smuzhiyun tx-num-evt = <32>; 705*4882a593Smuzhiyun rx-num-evt = <32>; 706*4882a593Smuzhiyun}; 707*4882a593Smuzhiyun 708*4882a593Smuzhiyun&tscadc { 709*4882a593Smuzhiyun status = "okay"; 710*4882a593Smuzhiyun tsc { 711*4882a593Smuzhiyun ti,wires = <4>; 712*4882a593Smuzhiyun ti,x-plate-resistance = <200>; 713*4882a593Smuzhiyun ti,coordinate-readouts = <5>; 714*4882a593Smuzhiyun ti,wire-config = <0x00 0x11 0x22 0x33>; 715*4882a593Smuzhiyun }; 716*4882a593Smuzhiyun}; 717*4882a593Smuzhiyun 718*4882a593Smuzhiyun&lcdc { 719*4882a593Smuzhiyun status = "okay"; 720*4882a593Smuzhiyun}; 721