Lines Matching +full:0 +full:x850
31 { 249600000, 2000000000, 0 },
35 .l = 0x14,
36 .alpha = 0xD555,
37 .config_ctl_val = 0x20485699,
38 .config_ctl_hi_val = 0x00002267,
39 .config_ctl_hi1_val = 0x00000024,
40 .user_ctl_val = 0x00000000,
41 .user_ctl_hi_val = 0x00000805,
42 .user_ctl_hi1_val = 0x000000D0,
46 .offset = 0x42c,
63 { P_BI_TCXO, 0 },
73 F(19200000, P_BI_TCXO, 1, 0, 0),
74 F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
75 F(240000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
76 F(338000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
77 F(365000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
78 F(444000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
79 F(533000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
84 .cmd_rcgr = 0x7f0,
85 .mnd_width = 0,
99 .halt_reg = 0x8f4,
102 .enable_reg = 0x8f4,
103 .enable_mask = BIT(0),
117 .halt_reg = 0x890,
120 .enable_reg = 0x890,
121 .enable_mask = BIT(0),
135 .halt_reg = 0x8d0,
138 .enable_reg = 0x8d0,
139 .enable_mask = BIT(0),
153 .halt_reg = 0x850,
156 .enable_reg = 0x850,
157 .enable_mask = BIT(0),
171 .gdscr = 0x814,
175 .flags = 0,
180 .gdscr = 0x874,
189 .gdscr = 0x8b4,
215 .max_register = 0xb94,
220 [VIDEO_CC_MVSC_CORE_CLK_BCR] = { 0x850, 2 },
250 regmap_update_bits(regmap, 0x984, 0x1, 0x1); in video_cc_sm8150_probe()