Lines Matching +full:0 +full:x850

13 	u8 res4[4];			/* 0xd0 */
15 	u8 res5[0x1e];
17 	u8 serial[0x0b];		/* 0xf5 */
18 	u8 vid;				/* 0x100 */
22 	u8 mac_addr[ETH_ALEN];		/* 0x107 */
24 	u8 vendor_name[0x07];
26 	u8 device_name[0x14];
27 	u8 res11[0xcf];
28 	u8 package_type;		/* 0x1fb */
29 	u8 res12[0x4];
33 	u8 mac_addr[ETH_ALEN];		/* 0xd0 */
41 	u8 ltr_cap;			/* 0xe3 */
46 	u8 res0:2;			/* 0xf4 */
70 	u8 res0[0x0e];
75 	u8 channel_plan;		/* 0xb8 */
79 	u8 pa_type;			/* 0xbc */
80 	u8 lna_type_2g[2];		/* 0xbd */
90 	u8 rf_antenna_option;		/* 0xc9 */
103 	/* 0xC00-0xCFF and 0xE00-0xEFF have the same layout */  in _rtw_write32s_mask()
105 	rtw_write32_mask(rtwdev, addr + 0x200, mask, data);  in _rtw_write32s_mask()
110 		BUILD_BUG_ON((addr) < 0xC00 || (addr) >= 0xD00);	       \
113 	} while (0)
117 	le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
121 	le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
123 	le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
125 	le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
127 	le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
129 	le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
131 	le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
133 	le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
135 	le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
137 	le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
139 	le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
141 	le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
143 #define REG_HTSTFWT	0x800
144 #define REG_RXPSEL	0x808
146 #define REG_TXPSEL	0x80c
147 #define REG_RXCCAMSK	0x814
148 #define REG_CCASEL	0x82c
149 #define REG_PDMFTH	0x830
150 #define REG_CCA2ND	0x838
151 #define REG_L1WT	0x83c
152 #define REG_L1PKWT	0x840
153 #define REG_MRC		0x850
154 #define REG_CLKTRK	0x860
155 #define REG_ADCCLK	0x8ac
156 #define REG_ADC160	0x8c4
157 #define REG_ADC40	0x8c8
158 #define REG_CDDTXP	0x93c
159 #define REG_TXPSEL1	0x940
160 #define REG_ACBB0	0x948
161 #define REG_ACBBRXFIR	0x94c
162 #define REG_ACGG2TBL	0x958
163 #define REG_RXSB	0xa00
164 #define REG_ADCINI	0xa04
165 #define REG_TXSF2	0xa24
166 #define REG_TXSF6	0xa28
167 #define REG_RXDESC	0xa2c
168 #define REG_ENTXCCK	0xa80
169 #define REG_AGCTR_A	0xc08
170 #define REG_TXDFIR	0xc20
171 #define REG_RXIGI_A	0xc50
172 #define REG_TRSW	0xca0
173 #define REG_RFESEL0	0xcb0
174 #define REG_RFESEL8	0xcb4
175 #define REG_RFECTL	0xcb8
176 #define REG_RFEINV	0xcbc
177 #define REG_AGCTR_B	0xe08
178 #define REG_RXIGI_B	0xe50
179 #define REG_ANTWT	0x1904
180 #define REG_IQKFAILMSK	0x1bf0