xref: /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-s32v234/mmdc.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * (C) Copyright 2015, Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_S32V234_MMDC_H__
8*4882a593Smuzhiyun #define __ARCH_ARM_MACH_S32V234_MMDC_H__
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #define MMDC0				0
11*4882a593Smuzhiyun #define MMDC1				1
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #define MMDC_MDCTL			0x0
14*4882a593Smuzhiyun #define MMDC_MDPDC			0x4
15*4882a593Smuzhiyun #define MMDC_MDOTC			0x8
16*4882a593Smuzhiyun #define MMDC_MDCFG0			0xC
17*4882a593Smuzhiyun #define MMDC_MDCFG1			0x10
18*4882a593Smuzhiyun #define MMDC_MDCFG2			0x14
19*4882a593Smuzhiyun #define MMDC_MDMISC			0x18
20*4882a593Smuzhiyun #define MMDC_MDSCR			0x1C
21*4882a593Smuzhiyun #define MMDC_MDREF			0x20
22*4882a593Smuzhiyun #define MMDC_MDRWD			0x2C
23*4882a593Smuzhiyun #define MMDC_MDOR			0x30
24*4882a593Smuzhiyun #define MMDC_MDMRR			0x34
25*4882a593Smuzhiyun #define MMDC_MDCFG3LP		0x38
26*4882a593Smuzhiyun #define MMDC_MDMR4			0x3C
27*4882a593Smuzhiyun #define MMDC_MDASP			0x40
28*4882a593Smuzhiyun #define MMDC_MAARCR			0x400
29*4882a593Smuzhiyun #define MMDC_MAPSR			0x404
30*4882a593Smuzhiyun #define MMDC_MAEXIDR0		0x408
31*4882a593Smuzhiyun #define MMDC_MAEXIDR1		0x40C
32*4882a593Smuzhiyun #define MMDC_MADPCR0		0x410
33*4882a593Smuzhiyun #define MMDC_MADPCR1		0x414
34*4882a593Smuzhiyun #define MMDC_MADPSR0		0x418
35*4882a593Smuzhiyun #define MMDC_MADPSR1		0x41C
36*4882a593Smuzhiyun #define MMDC_MADPSR2		0x420
37*4882a593Smuzhiyun #define MMDC_MADPSR3		0x424
38*4882a593Smuzhiyun #define MMDC_MADPSR4		0x428
39*4882a593Smuzhiyun #define MMDC_MADPSR5		0x42C
40*4882a593Smuzhiyun #define MMDC_MASBS0			0x430
41*4882a593Smuzhiyun #define MMDC_MASBS1			0x434
42*4882a593Smuzhiyun #define MMDC_MAGENP			0x440
43*4882a593Smuzhiyun #define MMDC_MPZQHWCTRL		0x800
44*4882a593Smuzhiyun #define MMDC_MPWLGCR		0x808
45*4882a593Smuzhiyun #define MMDC_MPWLDECTRL0	0x80C
46*4882a593Smuzhiyun #define MMDC_MPWLDECTRL1	0x810
47*4882a593Smuzhiyun #define MMDC_MPWLDLST		0x814
48*4882a593Smuzhiyun #define MMDC_MPODTCTRL		0x818
49*4882a593Smuzhiyun #define MMDC_MPRDDQBY0DL	0x81C
50*4882a593Smuzhiyun #define MMDC_MPRDDQBY1DL	0x820
51*4882a593Smuzhiyun #define MMDC_MPRDDQBY2DL	0x824
52*4882a593Smuzhiyun #define MMDC_MPRDDQBY3DL	0x828
53*4882a593Smuzhiyun #define MMDC_MPDGCTRL0		0x83C
54*4882a593Smuzhiyun #define MMDC_MPDGCTRL1		0x840
55*4882a593Smuzhiyun #define MMDC_MPDGDLST0		0x844
56*4882a593Smuzhiyun #define MMDC_MPRDDLCTL		0x848
57*4882a593Smuzhiyun #define MMDC_MPRDDLST		0x84C
58*4882a593Smuzhiyun #define MMDC_MPWRDLCTL		0x850
59*4882a593Smuzhiyun #define MMDC_MPWRDLST		0x854
60*4882a593Smuzhiyun #define MMDC_MPZQLP2CTL		0x85C
61*4882a593Smuzhiyun #define MMDC_MPRDDLHWCTL	0x860
62*4882a593Smuzhiyun #define MMDC_MPWRDLHWCTL	0x864
63*4882a593Smuzhiyun #define MMDC_MPRDDLHWST0	0x868
64*4882a593Smuzhiyun #define MMDC_MPRDDLHWST1	0x86C
65*4882a593Smuzhiyun #define MMDC_MPWRDLHWST1	0x870
66*4882a593Smuzhiyun #define MMDC_MPWRDLHWST2	0x874
67*4882a593Smuzhiyun #define MMDC_MPWLHWERR		0x878
68*4882a593Smuzhiyun #define MMDC_MPDGHWST0		0x87C
69*4882a593Smuzhiyun #define MMDC_MPDGHWST1		0x880
70*4882a593Smuzhiyun #define MMDC_MPDGHWST2		0x884
71*4882a593Smuzhiyun #define MMDC_MPDGHWST3		0x888
72*4882a593Smuzhiyun #define MMDC_MPPDCMPR1		0x88C
73*4882a593Smuzhiyun #define MMDC_MPPDCMPR2		0x890
74*4882a593Smuzhiyun #define MMDC_MPSWDAR0		0x894
75*4882a593Smuzhiyun #define MMDC_MPSWDRDR0		0x898
76*4882a593Smuzhiyun #define MMDC_MPSWDRDR1		0x89C
77*4882a593Smuzhiyun #define MMDC_MPSWDRDR2		0x8A0
78*4882a593Smuzhiyun #define MMDC_MPSWDRDR3		0x8A4
79*4882a593Smuzhiyun #define MMDC_MPSWDRDR4		0x8A8
80*4882a593Smuzhiyun #define MMDC_MPSWDRDR5		0x8AC
81*4882a593Smuzhiyun #define MMDC_MPSWDRDR6		0x8B0
82*4882a593Smuzhiyun #define MMDC_MPSWDRDR7		0x8B4
83*4882a593Smuzhiyun #define MMDC_MPMUR0			0x8B8
84*4882a593Smuzhiyun #define MMDC_MPDCCR			0x8C0
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun #define MMDC_MPMUR0_FRC_MSR			(1 << 11)
87*4882a593Smuzhiyun #define MMDC_MPZQHWCTRL_ZQ_HW_FOR	(1 << 16)
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun #endif
90