fix(rcar5): enable missing FEAT_AMUv1p1 on R-Car Gen5 to fix the build

Since commit 6edbd2d6a8ae ("fix(cpufeat): require FEAT_AMUv1p1 to
enable the auxiliary counters") the ENABLE_AMU_AUXILIARY_COUN

fix(rcar5): enable missing FEAT_AMUv1p1 on R-Car Gen5 to fix the build

Since commit 6edbd2d6a8ae ("fix(cpufeat): require FEAT_AMUv1p1 to
enable the auxiliary counters") the ENABLE_AMU_AUXILIARY_COUNTERS
requires ENABLE_FEAT_AMUv1p1 to be enabled as well. Enable missing
ENABLE_FEAT_AMUv1p1 to fix the build, which was broken because the
R-Car Gen5 and FEAT_AMUv1p1 commits landed in reverse order.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I834aff7798d7a5e10014fbd9f1ac8a97908b9aab

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feat(rcar): add initial BL31 support for Renesas R-Car X5H

This patch introduces initial BL31 (EL3 firmware) support for the
Renesas R-Car Gen5 (X5H) platform.

Key features and changes include:
- P

feat(rcar): add initial BL31 support for Renesas R-Car X5H

This patch introduces initial BL31 (EL3 firmware) support for the
Renesas R-Car Gen5 (X5H) platform.

Key features and changes include:
- Platform definitions and memory map for R-Car X5H
(Cortex-A720AE, 8 clusters x 4 cores)
- Platform-specific PSCI power management and topology
- SCMI-based power domain and system power management
- GICv4/Fainlight-AE interrupt controller initialization and support
- Trusted SRAM, shared memory, and crash log region setup
- SCIF console support
- Stack protector implementation for enhanced security
- Platform-specific linker script and build integration
- Various helper and initialization routines for MMU, GIC, and SCMI
- Platform-specific mailbox and boot flow handling
- Basic suspend implementation via SCP-FW
- AMU counters, SVE, PAUTH accessible to EL1

Signed-off-by: Hieu Nguyen <hieu.nguyen.dn@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I04be48a55a618fe952b28283d2f85f48f7761c9a

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Merge changes I82beb663,Ie970984e,Ia13f8e09,Ib498832d into integration

* changes:
feat(rcar): deduplicate plat_crash_print_regs
feat(rcar): split common SCIF code
feat(rcar): replace static rc

Merge changes I82beb663,Ie970984e,Ia13f8e09,Ib498832d into integration

* changes:
feat(rcar): deduplicate plat_crash_print_regs
feat(rcar): split common SCIF code
feat(rcar): replace static rcar_putc pointer with static register offsets
feat(rcar): deduplicate SCIF console_rcar_register

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Merge "feat(rcar): deduplicate PWRC timer" into integration

Merge changes I24209ac0,I1caf6cc6 into integration

* changes:
feat(rcar): deduplicate PWRC SRAM trampoline
feat(rcar): deduplicate stack protector

Merge "fix(rcar3): clear TCR_EL1 at the BL2 entry point" into integration

feat(rcar): deduplicate plat_crash_print_regs

The plat_crash_print_regs code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code. Split
plat_crash_print_regs in

feat(rcar): deduplicate plat_crash_print_regs

The plat_crash_print_regs code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code. Split
plat_crash_print_regs into plat_macros_cci.S and move the Gen3
specific plat_print_gic_regs macro into plat_macros_gic.S so it
can be pulled in only on R-Car Gen3.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I82beb663e769e7b33a79b992da9f70db7bad2d51

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refactor(build): make it standard to request a custom linker script

Hoist the add_define to a global location so that platforms only have to
declare its usage. Fix up #ifdef to #if since we will now

refactor(build): make it standard to request a custom linker script

Hoist the add_define to a global location so that platforms only have to
declare its usage. Fix up #ifdef to #if since we will now always pass a
definition.

Change-Id: Ia52ad5ed4dcbd157d139c8ca2fb3d35b32343b93
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(rcar): split common SCIF code

Move common SCIF code into drivers/renesas/common/scif/scif-common.c
and retain only SoC-specific console_rcar_init() in
drivers/renesas/rcar_gen4/scif/scif.c. Thi

feat(rcar): split common SCIF code

Move common SCIF code into drivers/renesas/common/scif/scif-common.c
and retain only SoC-specific console_rcar_init() in
drivers/renesas/rcar_gen4/scif/scif.c. This allows other SoCs to
reuse the common code and add only SoC specific glue code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Ie970984ea551e482479af91524974b281923f813

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feat(rcar): deduplicate SCIF console_rcar_register

The console_rcar_register assembler macro is functionally identical
between Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by

feat(rcar): deduplicate SCIF console_rcar_register

The console_rcar_register assembler macro is functionally identical
between Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Ib498832dbed9063efdb9979e89e53d119303d9df

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feat(rcar): deduplicate PWRC timer

The PWRC timer code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mai

feat(rcar): deduplicate PWRC timer

The PWRC timer code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Id50a730ea58faedaa24380fd3171be171ecd7269

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feat(rcar): deduplicate PWRC SRAM trampoline

The PWRC SRAM trampoline code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <mar

feat(rcar): deduplicate PWRC SRAM trampoline

The PWRC SRAM trampoline code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I24209ac0277fa12898bbeea69d93a8f057e76ed4

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feat(rcar): deduplicate stack protector

The stack protector code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <marek.vasut+r

feat(rcar): deduplicate stack protector

The stack protector code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I1caf6cc6a9ace678b50013eee1a5506fba9acccc

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fix(rcar3): clear TCR_EL1 at the BL2 entry point

According to ARM DDI0601 2025-06 [1] TCR_EL1, Translation Control
Register (EL1), all fields of TCR_EL1 do, on a Warm reset, (this
field) resets to a

fix(rcar3): clear TCR_EL1 at the BL2 entry point

According to ARM DDI0601 2025-06 [1] TCR_EL1, Translation Control
Register (EL1), all fields of TCR_EL1 do, on a Warm reset, (this
field) resets to an architecturally UNKNOWN value.

On some SoCs, after reset, this TCR_EL1 may not be 0, which in itself
is perfectly valid behavior. However, existing software may depend on
TCR_EL1 being 0, and the UNKNOWN value may confuse such software.

Reset TCR_EL1 to well defined value 0 at BL2 entrypoint to achieve
maximum compatibility.

[1] https://developer.arm.com/documentation/ddi0601/2025-06/AArch64-Registers/TCR-EL1--Translation-Control-Register--EL1-

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # update commit message
Change-Id: If3a1d40291b9b9768a8fc55e750bd742f3cc4ddc
---
Note: This is related to MR 25532 , but with reworked commit message
and broken out from the large work-in-progress series.

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Merge "fix(rcar3): add missing image_base/size assignment to BL33 image loading path" into integration

fix(rcar3): add missing image_base/size assignment to BL33 image loading path

Align BL33 image loading behavior in BL2 with BL3x image
loading behavior. BL31/BL32 image load already assigns
bl_mem_p

fix(rcar3): add missing image_base/size assignment to BL33 image loading path

Align BL33 image loading behavior in BL2 with BL3x image
loading behavior. BL31/BL32 image load already assigns
bl_mem_params->image_info.image_base and
bl_mem_params->image_info.image_size, but this assignment
is missing for BL33 image load.

This assignment is essential after retrieving the destination
address and size via rcar_get_dest_addr_from_cert(), so that
the parameters are passed correctly to the next stage. Without
this assignment, the BL33 image might not be loaded or validated
properly.

This change is not considered a vulnerability fix, but rather
a correction to ensure consistency and completeness in the BL2
image load logic.

Fixes: 4f7e0fa38fdb ("fix(rcar3): fix load address range check")
Signed-off-by: Hieu Nguyen <hieu.nguyen.dn@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Commit message update
Change-Id: I3c7c70f7f8d64b53e8c0f5ed61c71031b99fcde0

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fix: remove unused cpu_data related macros

There are no uses for CPU_DATA_PSCI_LOCK_OFFSET so it is removed.

PLAT_PCPU_DATA_SIZE is also unused in ST platforms and causes offsets
to mismatch when t

fix: remove unused cpu_data related macros

There are no uses for CPU_DATA_PSCI_LOCK_OFFSET so it is removed.

PLAT_PCPU_DATA_SIZE is also unused in ST platforms and causes offsets
to mismatch when the linker garbage collects it. It is also removed.

CPU_DATA_PLAT_PCPU_OFFSET is also removed as its only use is in
rcar_lock_get() and related macros which are never called since all
calls of these macros lack an argument.

Change-Id: I883ab58c56b4082e0e8b19a8d8f6186945bcc58e
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(rcar4): drop unused plat_pm_scmi

Drop unused plat_pm_scmi.c and related platform.mk entries.
If this is ever going to be used, this can be reinstated.

Signed-off-by: Marek Vasut <marek.vasut+re

fix(rcar4): drop unused plat_pm_scmi

Drop unused plat_pm_scmi.c and related platform.mk entries.
If this is ever going to be used, this can be reinstated.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Icdb5188cba97be5dfccb240f773288a54662e977

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feat(rcar): add support for Renesas R-Car S4 / V4H / V4M

Add support for Renesas R-Car S4 / V4H / V4M , which are Gen4 SoC.
Add platform code, BL31 setup code, platform specific PSCI handlers,
CPU p

feat(rcar): add support for Renesas R-Car S4 / V4H / V4M

Add support for Renesas R-Car S4 / V4H / V4M , which are Gen4 SoC.
Add platform code, BL31 setup code, platform specific PSCI handlers,
CPU power driver, Gen4 (H)SCIF driver, and function to get canary for
stack protector. Unlike Gen3, the Gen4 uses only TFA BL31 during boot.

Change-Id: Ic0eb8638a85757f997f29fc524c118c3e5d5135a
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.dn@renesas.com>
Signed-off-by: Jing Dan <jing.dan.nx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Masashi Ozaki <masashi.ozaki.te@renesas.com>
Signed-off-by: Taichiro Yokoyama <taichiro.yokoyama.ns@hitachi.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Tsukasa Kawaguchi <tsukasa.kawaguchi.aw@hitachi.com>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Vincent Bryce <vincent.bryce@cogentembedded.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
---
NOTE: This patch is squashed and cleaned up from large stack of patches
from multiple authors. SoB line from each author is included here,
the author of this commit is set to myself although that is most
certainly not accurate.

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chore(docs): drop the "wfi" from `pwr_domain_pwr_down_wfi`

To allow for generic handling of a wakeup, this hook is no longer
expected to call wfi itself. Update the name everywhere to reflect this
e

chore(docs): drop the "wfi" from `pwr_domain_pwr_down_wfi`

To allow for generic handling of a wakeup, this hook is no longer
expected to call wfi itself. Update the name everywhere to reflect this
expectation so that future platform implementers don't get misled.

Change-Id: Ic33f0b6da74592ad6778fd802c2f0b85223af614
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(rcar3-drivers): disable A/B loader support by default

The A/B loader [1] meant to be used for convenient CI testing.
The tool is installed into the same location as SA0, where it
conveniently fi

fix(rcar3-drivers): disable A/B loader support by default

The A/B loader [1] meant to be used for convenient CI testing.
The tool is installed into the same location as SA0, where it
conveniently fits due to its size, and where it makes use of
non-volatile PMIC registers to alternate between loading and
starting A or B copy of the BL2. The PMIC registers are used
because CPU registers are lost across reset.

In case the B copy is loaded, it is loaded from 8 MiB offset
from start of HF. In case the B copy fails to boot, a simple
reset of the system will switch back to booting previously
known working A copy and allow recovery.

The A/B loader sets MFIS bit MFISBTSTSR_BOOT_PARTITION to
pass the information which A/B copy is currently booting on
to TFA, which then loads the follow up components from 0 MiB
or 8 MiB offset, depending on whether the A or B copy is being
booted.

The MFISBTSTSR_BOOT_PARTITION interferes with regular A/B
switching during boot from eMMC as the boot media, where
the BootROM also sets MFISBTSTSR_BOOT_PARTITION bit in case
the system boots from SECOND eMMC HW BOOT partition.

Since the A/B loader is meant as a development and CI tool,
isolate the A/B loader use to RPC HF only and furthermore
isolate it behind new RCAR_RPC_HYPERFLASH_ABLOADER option
which is disabled by default.

[1] https://github.com/marex/abloader

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I04ecd50fa1405b78e1ba3949d54029034d4f22d8

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feat(rcar3): populate kaslr-seed in next stage DT

The SCEG CC6.3S which contains TRNG is only accessible from secure
world. Pull 8 random bytes out of the TRNG and pass them to the next
stage via DT

feat(rcar3): populate kaslr-seed in next stage DT

The SCEG CC6.3S which contains TRNG is only accessible from secure
world. Pull 8 random bytes out of the TRNG and pass them to the next
stage via DT fragment as /chosen/kaslr-seed property, so Linux can
use those random bytes to initialize KASLR in case it is compiled
with CONFIG_RANDOMIZE_BASE .

Linux before this patch prints early on boot:
KASLR disabled due to lack of seed

Linux after this patch prints early on boot:
KASLR enabled

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Ie05473e4e15d348febaca208247541e8a1532534

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