1# 2# Copyright (c) 2025, Renesas Electronics Corporation. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Cortex A720 is ARMv9.2A and will enable all features we want 8ARM_ARCH_MAJOR := 9 9ARM_ARCH_MINOR := 2 10 11PROGRAMMABLE_RESET_ADDRESS := 0 12COLD_BOOT_SINGLE_CPU := 1 13ARM_CCI_PRODUCT_ID := 500 14TRUSTED_BOARD_BOOT := 1 15RESET_TO_BL31 := 1 16GENERATE_COT := 1 17ENABLE_SVE_FOR_NS := 1 18ENABLE_SVE_FOR_SWD := 0 19MULTI_CONSOLE_API := 1 20INIT_UNUSED_NS_EL2 := 1 21 22ENABLE_FEAT_AMU := 1 23ENABLE_AMU_AUXILIARY_COUNTERS := 1 24 25ENABLE_PAUTH := 1 26CTX_INCLUDE_PAUTH_REGS := 1 27 28CRASH_REPORTING := 1 29HANDLE_EA_EL3_FIRST_NS := 1 30ENABLE_STACK_PROTECTOR := strong 31 32CTX_INCLUDE_AARCH32_REGS := 0 33 34# Process SET_SCMI_PARAM flag 35# 0:Disable(default), 1:Enable 36ifndef SET_SCMI_PARAM 37 SET_SCMI_PARAM := 0 38 $(eval $(call add_define,SET_SCMI_PARAM)) 39else 40 ifeq (${SET_SCMI_PARAM}, 0) 41 $(eval $(call add_define,SET_SCMI_PARAM)) 42 else ifeq (${SET_SCMI_PARAM},1) 43 $(eval $(call add_define,SET_SCMI_PARAM)) 44 else 45 $(error "Error:SET_SCMI_PARAM=${SET_SCMI_PARAM} is not supported.") 46 endif 47endif 48 49ifeq (${SPD},none) 50 SPD_NONE:=1 51 $(eval $(call add_define,SPD_NONE)) 52endif 53 54# LSI setting common define 55RCAR_X5H:=10 56RCAR_AUTO:=99 57$(eval $(call add_define,RCAR_X5H)) 58$(eval $(call add_define,RCAR_AUTO)) 59$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 60 61ifndef LSI 62 $(error "Error: Unknown LSI. Please use LSI=<LSI name> to specify the LSI") 63else 64 ifeq (${LSI},AUTO) 65 RCAR_LSI:=${RCAR_AUTO} 66 else ifeq (${LSI},X5H) 67 RCAR_LSI:=${RCAR_X5H} 68 else 69 $(error "Error: ${LSI} is not supported.") 70 endif 71 $(eval $(call add_define,RCAR_LSI)) 72endif 73 74# Disable workarounds unnecessary for Cortex-A720AE 75WORKAROUND_CVE_2017_5715 := 0 76WORKAROUND_CVE_2022_23960 := 0 77ERRATA_A720_AE_3699562 := 1 78 79USE_COHERENT_MEM := 0 80HW_ASSISTED_COHERENCY := 1 81 82PLAT_INCLUDES := -Iplat/renesas/rcar_gen5/include \ 83 -Iplat/renesas/rcar_gen5 \ 84 -Iplat/renesas/common/include \ 85 -Idrivers/renesas/common/scif \ 86 -Idrivers/renesas/common/timer \ 87 -Idrivers/renesas/rcar_gen5/pwrc \ 88 -Idrivers/arm/css/scmi \ 89 -Iinclude/drivers 90 91ifneq (${ENABLE_STACK_PROTECTOR},0) 92BL_COMMON_SOURCES += plat/renesas/common/rcar_stack_protector.c 93endif 94 95# R-Car Gen5 platform uses Arm GIC-Fainlight-AE, 96# which is successor of GIC-700 based on GICv4.1 97GIC_ENABLE_V4_EXTN := 1 98GIC_EXT_INTID := 1 99 100# GIC-600 configuration 101GICV3_SUPPORT_GIC600 := 1 102# Include GICv3 driver files 103USE_GIC_DRIVER := 3 104 105BL31_SOURCES += ${RCAR_GIC_SOURCES} \ 106 lib/cpus/aarch64/cortex_a720_ae.S \ 107 plat/common/plat_psci_common.c \ 108 plat/renesas/rcar_gen5/plat_topology.c \ 109 plat/renesas/rcar_gen5/aarch64/plat_helpers.S \ 110 plat/renesas/rcar_gen5/aarch64/platform_common.c \ 111 plat/renesas/rcar_gen5/bl31_plat_setup.c \ 112 plat/renesas/rcar_gen5/plat_pm.c \ 113 plat/renesas/rcar_gen5/plat_pm_scmi.c \ 114 plat/renesas/rcar_gen5/rcar_common.c \ 115 drivers/delay_timer/delay_timer.c \ 116 drivers/delay_timer/generic_delay_timer.c \ 117 drivers/renesas/common/scif/scif-common.c \ 118 drivers/renesas/common/scif/scif_helpers.S \ 119 drivers/renesas/common/timer/timer.c \ 120 drivers/renesas/rcar_gen5/pwrc/pwrc.c \ 121 drivers/renesas/rcar_gen5/scif/scif.c \ 122 drivers/arm/cci/cci.c \ 123 drivers/arm/css/scmi/scmi_common.c \ 124 drivers/arm/css/scmi/scmi_pwr_dmn_proto.c \ 125 drivers/arm/css/scmi/scmi_sys_pwr_proto.c 126 127include lib/xlat_tables_v2/xlat_tables.mk 128PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} 129 130# Pointer Authentication sources 131ifeq (${ENABLE_PAUTH}, 1) 132PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c 133endif 134 135# build the layout images for the bootrom and the necessary srecords 136rcar: rcar_srecord 137distclean realclean clean: clean_srecord 138 139# srecords 140SREC_PATH = ${BUILD_PLAT} 141BL31_ELF_SRC = ${SREC_PATH}/bl31/bl31.elf 142 143clean_srecord: 144 @echo "clean bl31 srecs" 145 rm -f ${SREC_PATH}/bl31.srec 146 147.PHONY: rcar_srecord 148rcar_srecord: $(BL31_ELF_SRC) 149 @echo "generating srec: ${SREC_PATH}/bl31.srec" 150 $(Q)$($(ARCH)-oc) -O srec --srec-forceS3 ${BL31_ELF_SRC} ${SREC_PATH}/bl31.srec 151 152