Merge changes Ic8700325,I6a3a9f28,I91a28b5f,Ia69289bf,I81d9b73a, ... into integration

* changes:
feat(cpufeat): constrain RAS_TRAP_NS_ERR_REC_ACCESS on ENABLE_FEAT_RAS
fix(build): set defaults t

Merge changes Ic8700325,I6a3a9f28,I91a28b5f,Ia69289bf,I81d9b73a, ... into integration

* changes:
feat(cpufeat): constrain RAS_TRAP_NS_ERR_REC_ACCESS on ENABLE_FEAT_RAS
fix(build): set defaults to feature flags before platform.mk
refactor(cpufeat): unify FEAT_IDTE3's definitions with arch.h
refactor(el3-runtime): generalise sysreg trapping
refactor(el3-runtime): use contexted SCR_EL3 instead of the register
build: rename default_ones to set_ones

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feat: enable FEATURE_DETECTION on FVP

FEATURE_DETECTION has received a lot of attention since its introduction
and at this point is quite reliable. Its experimental designation is no
longer appropri

feat: enable FEATURE_DETECTION on FVP

FEATURE_DETECTION has received a lot of attention since its introduction
and at this point is quite reliable. Its experimental designation is no
longer appropriate and it would be quite reasonable to use this feature
by default.

Always enable the feature for FVP so that we can have confidence that
the SW view of HW is up to date.

This patch also drops the mention of errata reporting around
FEATURE_DETECTION as this hasn't been true for some time.

Change-Id: I4a94dce243e430d5d3528c66154075b4352cd520
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(el3-runtime): generalise sysreg trapping

On a first look, the system register trapping code is quite
straightforward - match the register and call a handler. But looking a
bit more closely,

refactor(el3-runtime): generalise sysreg trapping

On a first look, the system register trapping code is quite
straightforward - match the register and call a handler. But looking a
bit more closely, with the intention of adding a new one, it isn't -
matching is based on opaque magic numbers and handlers have a lot of
duplication.

This patch tries to resolve both of these by hoisting common
functionality up towards common code and using S3 encodings for the
register matching. It also moves things around a bit to make them more
reusable in future.

Change-Id: Ia69289bfb16615312cc7adcc5cc3e319174b1bf0
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(gpt): move gpt support under ENABLE_FEAT_RME

Granule Protection Tables (GPT) library support is enabled only when
ENABLE_RMM is set (previously this build option was ENABLE_RME). Since
RME rela

feat(gpt): move gpt support under ENABLE_FEAT_RME

Granule Protection Tables (GPT) library support is enabled only when
ENABLE_RMM is set (previously this build option was ENABLE_RME). Since
RME related support is now enabled using feature detection option
ENABLE_FEAT_RME, this patch moves GPT support under ENABLE_FEAT_RME.

This change brings in below benefits:
- single TF-A build that works for RME and non-RME systems, when
build with ENABLE_FEAT_RME=2 (FEAT_STATE_CHECK)
- RMM loading is optional on RME systems
- SiP calls that leverages RME features to change the PAS of a memory
range from non-secure to secure is supported without need to enable
Realm PAS or RMM.
- FIRME Granule Management Interface (GMI) ABIs that handles
FEAT_RME_GPC2/FEAT_RME_GDI can be enabled without need to enable RMM

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I88d9d4e0491af2b4ae0307c018f2d4a71ee6693f

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feat(rmmd): replace ENABLE_RME with ENABLE_RMM

RME architectural requirements are now handled under the feature
detection option ENABLE_FEAT_RME. However, the existing ENABLE_RME build
option perfor

feat(rmmd): replace ENABLE_RME with ENABLE_RMM

RME architectural requirements are now handled under the feature
detection option ENABLE_FEAT_RME. However, the existing ENABLE_RME build
option performs RMM-specific tasks such as GPT setup, loading the RMM,
and enabling RMMD support.

Since ENABLE_RME now only controls RMM-related functionality, rename it
to ENABLE_RMM to better reflect its purpose and avoid confusion with
ENABLE_FEAT_RME.

For backward compatibility, setting the legacy ENABLE_RME=1 (until it is
deprecated) will automatically enable both ENABLE_FEAT_RME and
ENABLE_RMM.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Iac945bdffe5002161bf1161b81a5aa7abec68192

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Merge "fix(cpus)!: make ERRATA_SME_POWER_DOWN work with the recommended state ID" into integration

fix(cpus)!: make ERRATA_SME_POWER_DOWN work with the recommended state ID

The ERRATA_SME_POWER_DOWN flag doesn't account for the recommended state
ID encoding, only for the default one. This patch m

fix(cpus)!: make ERRATA_SME_POWER_DOWN work with the recommended state ID

The ERRATA_SME_POWER_DOWN flag doesn't account for the recommended state
ID encoding, only for the default one. This patch makes it work by
removing the generic flag and incorporating the functionality into the
CPU and platform layers.

The ERRATA_SME_POWER_DOWN is an awkward fix in generic code to a
platform problem. The PSCI layer shouldn't care about any CPU's inner
workings but it does. This isn't ideal once the issue is fixed since
we'll have to carry the "legacy" fix in generic code.

This patch is marked as breaking since the ERRATA_SME_POWER_DOWN flag is
removed and a couple of lines are required if CPU hotplug encounters a
powerdown with live SME state (CPU suspend will work as before). This
will get discovered with a panic at EL3 so this patch leaves a comment
to be able to trace it back.

Change-Id: Ia52865f527e81a8be3727093ed370901e55c5fef
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(gic): init the GIC before the platform with a hook

While GIC setup is generic across platforms, its usage is not. Some
platforms won't use it at EL3, while others need to configure interrupts
(l

fix(gic): init the GIC before the platform with a hook

While GIC setup is generic across platforms, its usage is not. Some
platforms won't use it at EL3, while others need to configure interrupts
(like RAS) in the standard platform hooks. To do that, the GIC needs to
be set up and ready to use before calling the platform hooks but
currently that is only done after. Annoyingly, a handful of platforms
need to set their GIC up before initialising it necessitating the
platform hooks to be called before GIC init.

This patch resolves this contradiction by moving the general GIC setup
calls to before the platform hooks and adding a GIC-specific platform
hook just before GIC per CPU init. This way both types of platforms can
do their business at the same time.

Change-Id: I361f587ab4603162ee880addb074800cbbb97b49
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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chore: bump eventlog library and interface changes

The eventlog library exposed macros TPM_ALG_SHA*. These will clash
with libTPM, so must be namespaced by prefixing them with EVLOG_

Change-Id: Id4

chore: bump eventlog library and interface changes

The eventlog library exposed macros TPM_ALG_SHA*. These will clash
with libTPM, so must be namespaced by prefixing them with EVLOG_

Change-Id: Id498d5882edda056c2d78c916193053655b3eb89
Signed-off-by: Matthew Ellis <Matthew.Ellis@arm.com>

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feat(fvp): implement SP live activation callback

This patch implements the callback for orchestrating live activation
of Secure Partition based on the guidance provided in the Appendix
18.10 of the

feat(fvp): implement SP live activation callback

This patch implements the callback for orchestrating live activation
of Secure Partition based on the guidance provided in the Appendix
18.10 of the FF-A v1.3 ALP2 specification.

The callback relies on helper utilities that enable the LSP to send
live activation framework messages to SPMC after performing several
sanity checks.

Change-Id: I2730433ec57c0c1163281eff9de729c6e93f3366
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(fvp): enable discovery of two Secure Partitions for live activation

This patch helps the LFA host to discover the presence of two Secure
Partitions for FVP platform that are capable of being li

feat(fvp): enable discovery of two Secure Partitions for live activation

This patch helps the LFA host to discover the presence of two Secure
Partitions for FVP platform that are capable of being live activated.
Necessary attributes of these two Secure Partitions are defined to
allow the LFA agent to report them to the host when the host performs
initial discovery of LFA support.

BREAKING CHANGE: Temporarily failing to build

Change-Id: Ibf0405559543cf19aaf45637c11ba5cf2e3a1619
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(fvp): introduce SP live activation component manager

This patch introduces SP LFA component manager which provides callbacks
necessary for live activation. Currently, the callbacks are just
pla

feat(fvp): introduce SP live activation component manager

This patch introduces SP LFA component manager which provides callbacks
necessary for live activation. Currently, the callbacks are just
placeholders.

Subsequent patches will implement the required functionality.

BREAKING CHANGE: Temporarily fails to build

Change-Id: Id733eaa0e7a300386b720fcce99ea265fd382ab6
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(spmd): helpers for SP live activation framework messages

This patch provides helper functions that enable an LSP to send
appropriate framework messages to SPMC in order to orchestrate
live acti

feat(spmd): helpers for SP live activation framework messages

This patch provides helper functions that enable an LSP to send
appropriate framework messages to SPMC in order to orchestrate
live activation of a physical SP.

BREAKING CHANGE: Temporarily fails to build

Change-Id: I1b7dcf91e08fc7d85b47f2b39330d1351f8294dd
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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chore(fvp): remove the dummy function fvp_get_partition_info

The functionality in this function will be ported to SP live
activation callback implemented in subsequent patches.

BREAKING CHANGE: Tem

chore(fvp): remove the dummy function fvp_get_partition_info

The functionality in this function will be ported to SP live
activation callback implemented in subsequent patches.

BREAKING CHANGE: Temporary fails to build

Change-Id: I49a6941a18d2357092dcebf3e882a86e5ac8991f
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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fix(romlib): gate RSA jump table entries

This fixes undefined reference to mbedtls_x509_get_rsassa_pss_params
in jump table when build with USE_ROMLIB=1 and KEY_ALG=ecdsa

Change-Id: Ib1d88acf00812

fix(romlib): gate RSA jump table entries

This fixes undefined reference to mbedtls_x509_get_rsassa_pss_params
in jump table when build with USE_ROMLIB=1 and KEY_ALG=ecdsa

Change-Id: Ib1d88acf008126752faec2ab7986e4b1a566b717
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes from topic "bk/new_feats" into integration

* changes:
feat(cpufeat): add support for FEAT_HACDBS
feat(cpufeat): add support for FEAT_HDBSS
feat(cpufeat): add support for FEAT_STE

Merge changes from topic "bk/new_feats" into integration

* changes:
feat(cpufeat): add support for FEAT_HACDBS
feat(cpufeat): add support for FEAT_HDBSS
feat(cpufeat): add support for FEAT_STEP2
feat(docs): update the feature guide to mention FEAT_IDTE3
fix(cpufeat): remove the feature list from arch_features.h
docs(cpufeat): add analysis of 2022 features
fix(cpus): use hint instruction instead of the psb mnemonic

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feat(cpufeat): add support for FEAT_HACDBS

The Hardware accelerator for cleaning Dirty state feature also has two
register just like FEAT_HDBSS. They are guarded by a SCR_EL3 bit which
set for NS wo

feat(cpufeat): add support for FEAT_HACDBS

The Hardware accelerator for cleaning Dirty state feature also has two
register just like FEAT_HDBSS. They are guarded by a SCR_EL3 bit which
set for NS world only and are not context switched as a result. There is
no use for this feature at EL3.

Change-Id: Ica7a312d891a1671df8e9f2adbfe464d96bbcd4d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): add support for FEAT_HDBSS

The Hardware Dirty state tracking structure feature has two registers to
enable tracking at lower ELs which are guarded by an SCR_EL3 bit. Set
that bit for

feat(cpufeat): add support for FEAT_HDBSS

The Hardware Dirty state tracking structure feature has two registers to
enable tracking at lower ELs which are guarded by an SCR_EL3 bit. Set
that bit for NS only and do not context switch the registers. There is
no use of the feature at EL3.

Change-Id: I174a256d70a99abfafc65eed3a2fbdaea5ea946d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): add support for FEAT_STEP2

This feature only needs MDCR_EL3.EnSTEPOP to be written and mdstepop_el1
to be context switched when the next EL is EL1.

Change-Id: I70e2a488f4e50da4b181a0

feat(cpufeat): add support for FEAT_STEP2

This feature only needs MDCR_EL3.EnSTEPOP to be written and mdstepop_el1
to be context switched when the next EL is EL1.

Change-Id: I70e2a488f4e50da4b181a00648c4f608e1da451c
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(fvp): fix PLAT_ARM_FW_HANDOFF_SIZE

commit 8a583b978355 (“refactor(fvp): use crypto-agile measured boot”)
changes the event log entry size calculation in BL2.
Specifically, it updates the logic

feat(fvp): fix PLAT_ARM_FW_HANDOFF_SIZE

commit 8a583b978355 (“refactor(fvp): use crypto-agile measured boot”)
changes the event log entry size calculation in BL2.
Specifically, it updates the logic from using PLAT_ARM_EVENT_LOG_MAX_SIZE
defined in BL2 to using the sum of the BL1 event log size and
PLAT_ARM_EVENT_LOG_MAX_SIZE in BL2.

As a result of this change, allocation of the xferlist entry
for SPMC_MANIFEST fails, because PLAT_ARM_FW_HANDOFF_SIZE still
uses PLAT_ARM_EVENT_LOG_MAX_SIZE based on the BL1-defined value.

To resolve this issue, use the correct event log size
when calculating PLAT_ARM_FW_HANDOFF_SIZE.

Fixes: 8a583b978355 ("refactor(fvp): use crypto-agile measured boot")
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: Ie6e9d5a15ee4784feef566716847c9a97abc9f94

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feat(fvp): pack/load tb-fw cert with ARM_FW_CONFIG_LOAD_ENABLE

Add support for packing tb-fw-cert into the FIP and loading it on AEM
FVP during RESET_TO_BL2 when ARM_FW_CONFIG_LOAD_ENABLE is enabled

feat(fvp): pack/load tb-fw cert with ARM_FW_CONFIG_LOAD_ENABLE

Add support for packing tb-fw-cert into the FIP and loading it on AEM
FVP during RESET_TO_BL2 when ARM_FW_CONFIG_LOAD_ENABLE is enabled.

Change-Id: I10409c0016cca9ab6d1191c96bf4dfbd740073a9
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(bl2): support RESET_TO_BL2 and ENABLE_RME

When RSE is used as the root of trust along with CPU that supports RME
there is a need to enable both RESET_TO_BL2 and ENABLE_RME.

In current bl2_main

feat(bl2): support RESET_TO_BL2 and ENABLE_RME

When RSE is used as the root of trust along with CPU that supports RME
there is a need to enable both RESET_TO_BL2 and ENABLE_RME.

In current bl2_main there are two different code paths for RESET_BL2,
one handles BL2 running in EL1 and other for BL2 running in EL3.

When RME is enabled, BL2 always runs at EL3 but the current flow calls
bl2_early_platform_setup2, bl2_plat_arch_setup instead of
bl2_el3_early_platform_setup, bl2_el3_plat_arch_setup. Adding RME,
TRANSFER_LIST, ROMLIB support in bl2_el3_* helpers makes
arm_bl2_el3_setup.c almost identical to arm_bl2_setup.c.

This patch removes bl2_el3_plat helpers and related files. Now different
combinations of RESET_TO_BL2, ENABLE_RME are handled in common bl2_setup
routines in arm_bl2_setup.c. This helps to have common place to support
new features and build flags for BL2 irrespective of which EL the BL2
runs.

BREAKING-CHANGE: This patch also changes all existing platform files and
functions that use format bl2_el3_* to bl2_plat helpers. If any platform
or out-of-tree platforms that need to support running BL2 in EL1 or EL3
must now handle it in bl2_early_platform_setup2 and bl2_plat_arch_setup.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I8d332dbe2de1db3b69319496c8d04626cdcf4140

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fix(fvp): increase resident text size of BL2

Enabling new CPU library code like Venom requires to set build flags
HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0. When build along with
RESET_TO_BL=1 (BL2

fix(fvp): increase resident text size of BL2

Enabling new CPU library code like Venom requires to set build flags
HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0. When build along with
RESET_TO_BL=1 (BL2 in EL3 case) causes increase in resident text size
of BL2.

This is applicable in case of PLAT=fvp as it includes a lot of CPU_LIBS
and might not be the case of other platforms as it includes only
specific CPU libs.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I2fd7eecebd9a2bdcbdc9fbbf4cecc2d659740931

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fix(arm): support FCONF when TRANSFER_LIST and RESET_BL2 is set

Enable reading HW_CONFIG device tree from transfer list entry when
RESET_BL2 is enabled.

Signed-off-by: Arunachalam Ganapathy <arunac

fix(arm): support FCONF when TRANSFER_LIST and RESET_BL2 is set

Enable reading HW_CONFIG device tree from transfer list entry when
RESET_BL2 is enabled.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ibcd65f3946924670ede3ba354db5bc574c70b4be

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fix(arm): update next image's ep info with the FW config address

When RESET_TO_BL2=1 and ARM_FW_CONFIG_LOAD_ENABLE=1, BL2 loads FW_CONFIG
but it fails to update the next image entry point with FW co

fix(arm): update next image's ep info with the FW config address

When RESET_TO_BL2=1 and ARM_FW_CONFIG_LOAD_ENABLE=1, BL2 loads FW_CONFIG
but it fails to update the next image entry point with FW config
address.

This fix also enables populating HW_CONFIG from platform setup routines
in BL31.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I86cc5e97cfdb0f18be647b867b1e1d82d53cdafd

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