1# 2# Copyright (c) 2013-2026, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 26# the FVP platform. 27FVP_TRUSTED_SRAM_SIZE := 384 28 29# Macro to enable helpers for running SPM tests. Disabled by default. 30PLAT_TEST_SPM := 0 31 32 33# Enable passing the DT to BL33 in x0 by default. 34USE_KERNEL_DT_CONVENTION := 1 35 36# By default dont build CPUs with no FVP model. 37BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 38 39# Enable CRC instructions via extension for ARMv8-A CPUs. 40# For ARMv8.1-A, and onwards CRC instructions are default enabled. 41ifeq (${ARM_ARCH_MAJOR},8) 42ifeq (${ARM_ARCH_MINOR},0) 43 ARM_ARCH_FEATURE := crc 44endif 45endif 46ENABLE_FEAT_AMU := 2 47ENABLE_FEAT_AMUv1p1 := 2 48ENABLE_FEAT_HCX := 2 49ENABLE_FEAT_RNG := 2 50ENABLE_FEAT_TWED := 2 51ENABLE_FEAT_GCS := 2 52ENABLE_FEAT_RAS := 2 53ENABLE_FEAT_SB := 2 54 55ifeq (${ARCH}, aarch64) 56 57ifeq (${SPM_MM}, 0) 58ifeq (${CTX_INCLUDE_FPREGS}, 0) 59 ENABLE_SME_FOR_NS := 2 60 ENABLE_SME2_FOR_NS := 2 61else 62 ENABLE_SVE_FOR_NS := 0 63 ENABLE_SME_FOR_NS := 0 64 ENABLE_SME2_FOR_NS := 0 65endif 66endif 67 68 ENABLE_BRBE_FOR_NS := 2 69 ENABLE_TRBE_FOR_NS := 2 70 ENABLE_FEAT_D128 := 2 71 ENABLE_FEAT_FPMR := 2 72 ENABLE_FEAT_MOPS := 2 73 ENABLE_FEAT_FGWTE3 := 2 74 ENABLE_FEAT_MPAM_PE_BW_CTRL := 2 75 ENABLE_FEAT_CPA2 := 2 76 ENABLE_FEAT_UINJ := 2 77endif 78 79ENABLE_SYS_REG_TRACE_FOR_NS := 2 80ENABLE_FEAT_CSV2_2 := 2 81ENABLE_FEAT_CSV2_3 := 2 82ENABLE_FEAT_CLRBHB := 2 83ENABLE_FEAT_DEBUGV8P9 := 2 84ENABLE_FEAT_DIT := 2 85ENABLE_FEAT_PAN := 2 86ENABLE_FEAT_VHE := 2 87CTX_INCLUDE_NEVE_REGS := 2 88ENABLE_FEAT_SEL2 := 2 89ENABLE_TRF_FOR_NS := 2 90ENABLE_FEAT_ECV := 2 91ENABLE_FEAT_FGT := 2 92ENABLE_FEAT_FGT2 := 2 93ENABLE_FEAT_THE := 2 94ENABLE_FEAT_TCR2 := 2 95ENABLE_FEAT_S2PIE := 2 96ENABLE_FEAT_S1PIE := 2 97ENABLE_FEAT_S2POE := 2 98ENABLE_FEAT_S1POE := 2 99ENABLE_FEAT_SCTLR2 := 2 100ENABLE_FEAT_MTE2 := 2 101ENABLE_FEAT_LS64_ACCDATA := 2 102ENABLE_FEAT_AIE := 2 103ENABLE_FEAT_PFAR := 2 104ENABLE_FEAT_EBEP := 2 105 106ifeq (${ENABLE_RME},1) 107 ENABLE_FEAT_MEC := 2 108 RMMD_ENABLE_IDE_KEY_PROG := 1 109endif 110 111# The FVP platform depends on this macro to build with correct GIC driver. 112$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 113 114# Pass FVP_CLUSTER_COUNT to the build system. 115$(eval $(call add_define,FVP_CLUSTER_COUNT)) 116 117# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 118$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 119 120# Pass FVP_MAX_PE_PER_CPU to the build system. 121$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 122 123# Pass FVP_GICR_REGION_PROTECTION to the build system. 124$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 125 126# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 127$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 128 129ifeq (${DRTM_SUPPORT},1) 130MBOOT_EL_HASH_ALG := sha256 131endif 132 133# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 134# choose the CCI driver , else the CCN driver 135ifeq ($(FVP_CLUSTER_COUNT), 0) 136$(error "Incorrect cluster count specified for FVP port") 137else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 138FVP_INTERCONNECT_DRIVER := FVP_CCI 139else 140FVP_INTERCONNECT_DRIVER := FVP_CCN 141endif 142 143$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 144 145# Choose the GIC sources depending upon the how the FVP will be invoked 146ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 147USE_GIC_DRIVER := 3 148 149# The GIC model (GIC-600 or GIC-500) will be detected at runtime 150GICV3_SUPPORT_GIC600 := 1 151GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 152 153FVP_SECURITY_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 154ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 155BL31_SOURCES += plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c 156endif 157 158ifeq (${HW_ASSISTED_COHERENCY}, 0) 159FVP_DT_PREFIX := fvp-base-gicv3-psci 160else 161FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 162endif 163else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV5) 164USE_GIC_DRIVER := 5 165ENABLE_FEAT_GCIE := 1 166BL31_SOURCES += plat/arm/board/fvp/fvp_gicv5.c 167FVP_DT_PREFIX := fvp-base-gicv5-psci 168ifneq ($(SPD),none) 169 $(error Error: GICv5 is not compatible with SPDs) 170endif 171ifeq ($(ENABLE_RME),1) 172 $(error Error: GICv5 is not compatible with RME) 173endif 174else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 175USE_GIC_DRIVER := 2 176 177# No GICv4 extension 178GIC_ENABLE_V4_EXTN := 0 179$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 180 181FVP_DT_PREFIX := fvp-base-gicv2-psci 182else 183$(error "Incorrect GIC driver chosen on FVP port") 184endif 185 186ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 187FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 188else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 189FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 190 plat/arm/common/arm_ccn.c 191else 192$(error "Incorrect CCN driver chosen on FVP port") 193endif 194 195FVP_SECURITY_SOURCES += drivers/arm/tzc/tzc400.c \ 196 plat/arm/board/fvp/fvp_security.c \ 197 plat/arm/common/arm_tzc400.c 198 199 200PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 201 -Iinclude/lib/psa 202 203 204PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 205 206FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 207 208ifeq (${ARCH}, aarch64) 209 210# select a different set of CPU files, depending on whether we compile for 211# hardware assisted coherency cores or not 212ifeq (${HW_ASSISTED_COHERENCY}, 0) 213# Cores used without DSU 214 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 215 lib/cpus/aarch64/cortex_a53.S \ 216 lib/cpus/aarch64/cortex_a57.S \ 217 lib/cpus/aarch64/cortex_a72.S \ 218 lib/cpus/aarch64/cortex_a73.S 219else 220# Cores used with DSU only 221 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 222 # AArch64-only cores 223 # TODO: add all cores to the appropriate lists 224 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 225 lib/cpus/aarch64/cortex_a65ae.S \ 226 lib/cpus/aarch64/cortex_a76.S \ 227 lib/cpus/aarch64/cortex_a76ae.S \ 228 lib/cpus/aarch64/cortex_a77.S \ 229 lib/cpus/aarch64/cortex_a78.S \ 230 lib/cpus/aarch64/cortex_a78_ae.S \ 231 lib/cpus/aarch64/cortex_a78c.S \ 232 lib/cpus/aarch64/cortex_a710.S \ 233 lib/cpus/aarch64/cortex_a715.S \ 234 lib/cpus/aarch64/cortex_a720.S \ 235 lib/cpus/aarch64/cortex_a720_ae.S \ 236 lib/cpus/aarch64/neoverse_n1.S \ 237 lib/cpus/aarch64/neoverse_n2.S \ 238 lib/cpus/aarch64/neoverse_v1.S \ 239 lib/cpus/aarch64/neoverse_e1.S \ 240 lib/cpus/aarch64/cortex_x2.S \ 241 lib/cpus/aarch64/cortex_x4.S 242 endif 243 # AArch64/AArch32 cores 244 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 245 lib/cpus/aarch64/cortex_a75.S 246endif 247 248#Include all CPUs to build to support all-errata build. 249ifeq (${ENABLE_ERRATA_ALL},1) 250 BUILD_CPUS_WITH_NO_FVP_MODEL = 1 251 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a320.S \ 252 lib/cpus/aarch64/cortex_a510.S \ 253 lib/cpus/aarch64/cortex_a520.S \ 254 lib/cpus/aarch64/cortex_a725.S \ 255 lib/cpus/aarch64/cortex_x1.S \ 256 lib/cpus/aarch64/cortex_x3.S \ 257 lib/cpus/aarch64/cortex_x925.S \ 258 lib/cpus/aarch64/neoverse_n3.S \ 259 lib/cpus/aarch64/neoverse_v2.S \ 260 lib/cpus/aarch64/neoverse_v3.S 261endif 262 263#Build AArch64-only CPUs with no FVP model yet. 264ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 265 ERRATA_SME_POWER_DOWN := 1 266 FVP_CPU_LIBS += lib/cpus/aarch64/c1_pro.S \ 267 lib/cpus/aarch64/c1_nano.S \ 268 lib/cpus/aarch64/c1_ultra.S \ 269 lib/cpus/aarch64/c1_premium.S \ 270 lib/cpus/aarch64/canyon.S \ 271 lib/cpus/aarch64/caddo.S \ 272 lib/cpus/aarch64/veymont.S \ 273 lib/cpus/aarch64/dionysus.S \ 274 lib/cpus/aarch64/venom.S \ 275 lib/cpus/aarch64/lsc25_p_core.S \ 276 lib/cpus/aarch64/lsc25_e_core.S 277endif 278 279else 280FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 281 lib/cpus/aarch32/cortex_a57.S \ 282 lib/cpus/aarch32/cortex_a53.S 283endif 284 285BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 286 drivers/arm/sp805/sp805.c \ 287 drivers/delay_timer/delay_timer.c \ 288 drivers/io/io_semihosting.c \ 289 lib/semihosting/semihosting.c \ 290 lib/semihosting/${ARCH}/semihosting_call.S \ 291 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 292 plat/arm/board/fvp/fvp_bl1_setup.c \ 293 plat/arm/board/fvp/fvp_cpu_pwr.c \ 294 plat/arm/board/fvp/fvp_err.c \ 295 plat/arm/board/fvp/fvp_io_storage.c \ 296 plat/arm/board/fvp/fvp_topology.c \ 297 ${FVP_CPU_LIBS} \ 298 ${FVP_INTERCONNECT_SOURCES} 299 300ifeq (${USE_SP804_TIMER},1) 301BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 302else 303BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 304endif 305 306 307BL2_SOURCES += drivers/arm/sp805/sp805.c \ 308 drivers/io/io_semihosting.c \ 309 lib/utils/mem_region.c \ 310 lib/semihosting/semihosting.c \ 311 lib/semihosting/${ARCH}/semihosting_call.S \ 312 plat/arm/board/fvp/fvp_bl2_setup.c \ 313 plat/arm/board/fvp/fvp_err.c \ 314 plat/arm/board/fvp/fvp_io_storage.c \ 315 plat/arm/common/arm_nor_psci_mem_protect.c \ 316 ${FVP_SECURITY_SOURCES} 317 318 319ifeq (${COT_DESC_IN_DTB},1) 320BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 321endif 322 323ifeq (${ENABLE_RME},1) 324BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 325 plat/arm/board/fvp/fvp_cpu_pwr.c 326 327BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 328 plat/arm/board/fvp/fvp_realm_attest_key.c \ 329 plat/arm/board/fvp/fvp_el3_token_sign.c \ 330 plat/arm/board/fvp/fvp_ide_keymgmt.c \ 331 plat/arm/common/plat_rmm_mem_carveout.c 332endif 333 334ifneq (${ENABLE_FEAT_RNG_TRAP},0) 335BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 336endif 337 338ifeq (${RESET_TO_BL2},1) 339BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 340 plat/arm/board/fvp/fvp_cpu_pwr.c \ 341 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 342 ${FVP_CPU_LIBS} \ 343 ${FVP_INTERCONNECT_SOURCES} 344endif 345 346ifeq (${USE_SP804_TIMER},1) 347BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 348endif 349 350BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 351 ${FVP_SECURITY_SOURCES} 352 353ifeq (${USE_SP804_TIMER},1) 354BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 355endif 356 357BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 358 drivers/arm/smmu/smmu_v3.c \ 359 drivers/delay_timer/delay_timer.c \ 360 drivers/cfi/v2m/v2m_flash.c \ 361 lib/utils/mem_region.c \ 362 plat/arm/board/fvp/fvp_bl31_setup.c \ 363 plat/arm/board/fvp/fvp_console.c \ 364 plat/arm/board/fvp/fvp_pm.c \ 365 plat/arm/board/fvp/fvp_topology.c \ 366 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 367 plat/arm/board/fvp/fvp_cpu_pwr.c \ 368 plat/arm/common/arm_nor_psci_mem_protect.c \ 369 ${FVP_CPU_LIBS} \ 370 ${FVP_INTERCONNECT_SOURCES} \ 371 ${FVP_SECURITY_SOURCES} 372 373# Support for fconf in BL31 374# Added separately from the above list for better readability 375ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 376BL31_SOURCES += lib/fconf/fconf.c \ 377 lib/fconf/fconf_dyn_cfg_getter.c \ 378 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 379 380BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 381 382ifeq (${SEC_INT_DESC_IN_FCONF},1) 383BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 384endif 385 386endif 387 388ifeq (${USE_SP804_TIMER},1) 389BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 390else 391BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 392endif 393 394# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 395FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 396 397FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 398$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 399HW_CONFIG := ${FVP_HW_CONFIG} 400 401HW_CONFIG_BASE ?= 0x82000000 402 403# Set default initrd base 128MiB offset of the default kernel address in FVP 404INITRD_BASE ?= 0x90000000 405 406# Kernel base address supports Linux kernels before v5.7 407# DTB base 1MiB before normal base kernel address in FVP (0x88000000) 408ifeq (${ARM_LINUX_KERNEL_AS_BL33},1) 409 PRELOADED_BL33_BASE ?= 0x80080000 410 ifeq (${RESET_TO_BL31},1) 411 ARM_PRELOADED_DTB_BASE ?= 0x87F00000 412 endif 413endif 414 415ifeq (${TRANSFER_LIST}, 0) 416FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 417 ${PLAT}_fw_config.dts \ 418 ${PLAT}_tb_fw_config.dts \ 419 ${PLAT}_soc_fw_config.dts \ 420 ${PLAT}_nt_fw_config.dts \ 421 ) 422 423FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 424FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 425FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 426FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 427 428ifeq (${SPD},tspd) 429FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 430FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 431 432# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 433$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 434endif 435 436# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 437$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 438# Add the NT_FW_CONFIG to FIP and specify the same to certtool 439$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 440endif 441 442ifeq (${SPD},spmd) 443 444ifeq ($(ARM_SPMC_MANIFEST_DTS),) 445ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 446endif 447 448FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 449FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 450 451# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 452$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 453endif 454 455# Add the HW_CONFIG to FIP and specify the same to certtool 456$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 457 458ifeq (${TRANSFER_LIST}, 1) 459 460ifeq ($(RESET_TO_BL31), 1) 461FW_HANDOFF_SIZE := 20000 462 463TRANSFER_LIST_DTB_OFFSET := 0x20 464$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 465endif 466 467# 468# To load SP_PKGs with TRANSFER_LIST, FVP_TB_FW_CONFIG is required. 469# 470ifeq (${BL2_ENABLE_SP_LOAD}, 1) 471 FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 472 ${PLAT}_tb_fw_config.dts \ 473 ) 474 475 FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 476 477 # Add the TB_FW_CONFIG to FIP and specify the same to certtool 478 $(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 479endif 480 481endif 482 483ifeq (${HOB_LIST}, 1) 484include lib/hob/hob.mk 485endif 486 487# Enable dynamic mitigation support by default 488DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 489 490ifneq (${ENABLE_FEAT_AMU},0) 491BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 492 lib/cpus/aarch64/cpuamu_helpers.S 493 494ifeq (${HW_ASSISTED_COHERENCY}, 1) 495BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 496 lib/cpus/aarch64/neoverse_n1_pubsub.c 497endif 498endif 499 500ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 501 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 502 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 503 endif 504 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c \ 505 plat/arm/board/fvp/aarch64/fvp_ea.c 506endif 507 508ifneq (${ENABLE_STACK_PROTECTOR},0) 509PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 510endif 511 512# Enable the dynamic translation tables library. 513ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 514 ifeq (${ARCH},aarch32) 515 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 516 else # AArch64 517 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 518 endif 519endif 520 521ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 522 ifeq (${ARCH},aarch32) 523 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 524 else # AArch64 525 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 526 ifeq (${SPD},tspd) 527 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 528 endif 529 endif 530endif 531 532ifeq (${USE_DEBUGFS},1) 533 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 534endif 535 536# Add support for platform supplied linker script for BL31 build 537PLAT_EXTRA_LD_SCRIPT := 1 538 539ifneq (${RESET_TO_BL2}, 0) 540 override BL1_SOURCES = 541endif 542 543include plat/arm/board/common/board_common.mk 544include plat/arm/common/arm_common.mk 545 546ifeq (${MEASURED_BOOT},1) 547BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 548 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 549 lib/psa/measured_boot.c \ 550 common/measured_boot_helpers.c 551 552BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 553 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 554 lib/psa/measured_boot.c \ 555 common/measured_boot_helpers.c 556endif 557 558ifeq (${DRTM_SUPPORT}, 1) 559BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 560 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 561 plat/arm/board/fvp/fvp_drtm_err.c \ 562 plat/arm/board/fvp/fvp_drtm_measurement.c \ 563 plat/arm/board/fvp/fvp_drtm_stub.c \ 564 plat/arm/common/arm_dyn_cfg.c \ 565 plat/arm/board/fvp/fvp_err.c 566endif 567 568ifeq (${TRUSTED_BOARD_BOOT}, 1) 569BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 570BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 571 572# FVP being a development platform, enable capability to disable Authentication 573# dynamically if TRUSTED_BOARD_BOOT is set. 574DYN_DISABLE_AUTH := 1 575endif 576 577ifeq (${SPMC_AT_EL3}, 1) 578PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 579endif 580 581PSCI_OS_INIT_MODE := 1 582 583ifeq (${SPD},spmd) 584BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 585endif 586 587# Test specific macros, keep them at bottom of this file 588$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 589ifeq (${PLATFORM_TEST_EA_FFH}, 1) 590 ifeq (${FFH_SUPPORT}, 0) 591 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 592 endif 593 594endif 595 596PLATFORM_TEST_RAS_FFH ?= 0 597$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 598ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 599 ifeq (${ENABLE_FEAT_RAS}, 0) 600 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 601 endif 602 ifeq (${SDEI_SUPPORT}, 0) 603 $(error "PLATFORM_TEST_RAS_FFH expects SDEI_SUPPORT to be 1") 604 endif 605 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 606 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 607 endif 608endif 609 610$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 611ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 612 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 613 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 614 endif 615 ifeq (${ENABLE_SPMD_LP}, 0) 616 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 617 endif 618 ifeq (${ENABLE_FEAT_RAS}, 0) 619 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 620 endif 621 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 622 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 623 endif 624endif 625 626ifeq (${ERRATA_ABI_SUPPORT}, 1) 627include plat/arm/board/fvp/fvp_cpu_errata.mk 628endif 629 630# Build macro necessary for running SPM tests on FVP platform 631$(eval $(call add_define,PLAT_TEST_SPM)) 632 633ifeq (${LFA_SUPPORT},1) 634BL31_SOURCES += plat/arm/board/fvp/fvp_lfa.c 635endif 636 637# This is set to 1 by default when the firmware update 638# support is enabled. Since the BL2 image is not updatable 639ifeq ($(PSA_FWU_SUPPORT),1) 640 SEPARATE_BL2_FIP := 1 641endif 642 643ifeq (${TRANSFER_LIST}, 0) 644ifeq (${SEPARATE_BL2_FIP},1) 645$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG},BL2_)) 646$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG},BL2_)) 647else 648$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 649$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 650endif 651endif 652