1/* 2 * Copyright (c) 2023-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_ultra.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12#include <wa_cve_2025_0647_cpprctx.h> 13 14#include <plat_macros.S> 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Arm C1-Ultra must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Arm C1-Ultra supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26#if ERRATA_SME_POWER_DOWN == 0 27#error "Arm C1-Ultra needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 28#endif 29 30cpu_reset_prologue c1_ultra 31 32workaround_runtime_start c1_ultra, ERRATUM(3324333), ERRATA_C1ULTRA_3324333 33 speculation_barrier 34workaround_runtime_end c1_ultra, ERRATUM(3324333) 35 36check_erratum_ls c1_ultra, ERRATUM(3324333), CPU_REV(0, 0) 37 38workaround_reset_start c1_ultra, ERRATUM(3502731), ERRATA_C1ULTRA_3502731 39 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR4_EL1, BIT(23) 40workaround_reset_end c1_ultra, ERRATUM(3502731) 41 42check_erratum_ls c1_ultra, ERRATUM(3502731), CPU_REV(0, 0) 43 44workaround_reset_start c1_ultra, ERRATUM(3651221), ERRATA_C1ULTRA_3651221 45 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR6_EL1, BIT(41) 46workaround_reset_end c1_ultra, ERRATUM(3651221) 47 48check_erratum_ls c1_ultra, ERRATUM(3651221), CPU_REV(0, 0) 49 50.global check_erratum_c1_ultra_3658374 51add_erratum_entry c1_ultra, ERRATUM(3658374), ERRATA_C1ULTRA_3658374 52check_erratum_ls c1_ultra, ERRATUM(3658374), CPU_REV(1, 0) 53 54workaround_reset_start c1_ultra, ERRATUM(3684152), ERRATA_C1ULTRA_3684152 55 sysreg_bitfield_insert C1_ULTRA_IMP_CPUACTLR_EL1, C1_ULTRA_IMP_CPUACTLR_EL1_LOAD_BIT, \ 56 C1_ULTRA_IMP_CPUACTLR_EL1_LOAD_SHIFT, C1_ULTRA_IMP_CPUACTLR_EL1_LOAD_WIDTH 57workaround_reset_end c1_ultra, ERRATUM(3684152) 58 59check_erratum_ls c1_ultra, ERRATUM(3684152), CPU_REV(0, 0) 60 61workaround_reset_start c1_ultra, ERRATUM(3705939), ERRATA_C1ULTRA_3705939 62 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR_EL1, BIT(48) 63workaround_reset_end c1_ultra, ERRATUM(3705939) 64 65check_erratum_ls c1_ultra, ERRATUM(3705939), CPU_REV(1, 0) 66 67workaround_reset_start c1_ultra, ERRATUM(3815514), ERRATA_C1ULTRA_3815514 68 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR5_EL1, BIT(13) 69workaround_reset_end c1_ultra, ERRATUM(3815514) 70 71check_erratum_ls c1_ultra, ERRATUM(3815514), CPU_REV(1, 0) 72 73workaround_reset_start c1_ultra, ERRATUM(3865171), ERRATA_C1ULTRA_3865171 74 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR2_EL1, BIT(22) 75workaround_reset_end c1_ultra, ERRATUM(3865171) 76 77check_erratum_ls c1_ultra, ERRATUM(3865171), CPU_REV(1, 0) 78 79workaround_reset_start c1_ultra, ERRATUM(3926381), ERRATA_C1ULTRA_3926381 80 /* Convert WFx to NOP */ 81 ldr x0,=0x0 82 msr C1_ULTRA_IMP_CPUPSELR_EL3, x0 83 ldr x0,=0xD503205f 84 msr C1_ULTRA_IMP_CPUPOR_EL3, x0 85 ldr x0,=0xFFFFFFDF 86 msr C1_ULTRA_IMP_CPUPMR_EL3, x0 87 ldr x0,=0x1000002043ff 88 msr C1_ULTRA_IMP_CPUPCR_EL3, x0 89 /* Convert WFxT to NOP */ 90 ldr x0,=0x1 91 msr C1_ULTRA_IMP_CPUPSELR_EL3, x0 92 ldr x0,=0xD5031000 93 msr C1_ULTRA_IMP_CPUPOR_EL3, x0 94 ldr x0,=0xFFFFFFC0 95 msr C1_ULTRA_IMP_CPUPMR_EL3, x0 96 ldr x0,=0x1000002043ff 97 msr C1_ULTRA_IMP_CPUPCR_EL3, x0 98 isb 99workaround_reset_end c1_ultra, ERRATUM(3926381) 100 101check_erratum_range c1_ultra, ERRATUM(3926381), CPU_REV(1, 0), CPU_REV(1, 0) 102 103workaround_reset_start c1_ultra, ERRATUM(4102704), ERRATA_C1ULTRA_4102704 104 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR4_EL1, BIT(23) 105workaround_reset_end c1_ultra, ERRATUM(4102704) 106 107check_erratum_ls c1_ultra, ERRATUM(4102704), CPU_REV(1, 0) 108 109 /* ------------------------------------------------------------- 110 * CVE-2024-7881 is mitigated for C1-Ultra using erratum 3651221 111 * workaround by disabling the affected prefetcher setting 112 * CPUACTLR6_EL1[41]. 113 * ------------------------------------------------------------- 114 */ 115workaround_reset_start c1_ultra, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 116 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR6_EL1, BIT(41) 117workaround_reset_end c1_ultra, CVE(2024, 7881) 118 119check_erratum_ls c1_ultra, CVE(2024, 7881), CPU_REV(0, 0) 120 121 /* 122 * Instruction patch sequence to trap 'cpp rctx' instructions to EL3. 123 * Enables mitigation for CVE-2025-0647. 124 */ 125workaround_reset_start c1_ultra, CVE(2025, 647), WORKAROUND_CVE_2025_0647 126 mov x0, #WA_PATCH_SLOT(3) 127 bl wa_cve_2025_0647_instruction_patch 128workaround_reset_end c1_ultra, CVE(2025, 647) 129 130check_erratum_chosen c1_ultra, CVE(2025, 647), WORKAROUND_CVE_2025_0647 131 132#if WORKAROUND_CVE_2025_0647 133func c1_ultra_impl_defined_el3_handler 134 mov x0, #WA_LS_RCG_EN 135 136 /* See if this call came from trap handler. */ 137 cmp x1, #EC_IMP_DEF_EL3 138 bne wa_cve_2025_0647_do_cpp_wa 139 orr x0, x0, #WA_IS_TRAP_HANDLER 140 b wa_cve_2025_0647_do_cpp_wa 141endfunc c1_ultra_impl_defined_el3_handler 142#endif 143 144cpu_reset_func_start c1_ultra 145 /* ---------------------------------------------------- 146 * Disable speculative loads 147 * ---------------------------------------------------- 148 */ 149 msr SSBS, xzr 150 apply_erratum c1_ultra, ERRATUM(3324333), ERRATA_C1ULTRA_3324333 151 /* model bug: not cleared on reset */ 152 sysreg_bit_clear C1_ULTRA_IMP_CPUPWRCTLR_EL1, \ 153 C1_ULTRA_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 154 enable_mpmm 155cpu_reset_func_end c1_ultra 156 157func c1_ultra_core_pwr_dwn 158 /* --------------------------------------------------- 159 * Flip CPU power down bit in power control register. 160 * It will be set on powerdown and cleared on wakeup 161 * --------------------------------------------------- 162 */ 163 sysreg_bit_toggle C1_ULTRA_IMP_CPUPWRCTLR_EL1, \ 164 C1_ULTRA_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 165 isb 166 signal_pabandon_handled 167 ret 168endfunc c1_ultra_core_pwr_dwn 169 170.section .rodata.c1_ultra_regs, "aS" 171c1_ultra_regs: /* The ASCII list of register names to be reported */ 172 .asciz "cpuectlr_el1", "" 173 174func c1_ultra_cpu_reg_dump 175 adr x6, c1_ultra_regs 176 mrs x8, C1_ULTRA_IMP_CPUECTLR_EL1 177 ret 178endfunc c1_ultra_cpu_reg_dump 179 180#if WORKAROUND_CVE_2025_0647 181declare_cpu_ops_eh c1_ultra, C1_ULTRA_MIDR, \ 182 c1_ultra_reset_func, \ 183 c1_ultra_impl_defined_el3_handler, \ 184 c1_ultra_core_pwr_dwn 185#else 186declare_cpu_ops c1_ultra, C1_ULTRA_MIDR, \ 187 c1_ultra_reset_func, \ 188 c1_ultra_core_pwr_dwn 189#endif 190