1 /* 2 * Copyright (c) 2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_features.h> 9 #include <arch_helpers.h> 10 #include <context.h> 11 #include <lib/el3_runtime/context_mgmt.h> 12 #include <lib/el3_runtime/cpu_data.h> 13 #include <lib/extensions/idte3.h> 14 15 void idte3_init_percpu_once_regs(size_t security_state) 16 { 17 assert(security_state < CPU_CONTEXT_NUM); 18 19 percpu_idregs_t * const reg = 20 &get_cpu_data(idregs[security_state]); 21 22 reg->id_aa64dfr0_el1 = read_id_aa64dfr0_el1(); 23 reg->id_aa64dfr1_el1 = read_id_aa64dfr1_el1(); 24 25 update_feat_spe_idreg_field(security_state); 26 update_feat_brbe_idreg_field(security_state); 27 update_feat_trbe_idreg_field(security_state); 28 update_feat_trf_idreg_field(security_state); 29 update_feat_mtpmu_idreg_field(security_state); 30 update_feat_sebep_idreg_field(security_state); 31 update_feat_sys_reg_trace_idreg_field(security_state); 32 update_feat_debugv8p9_idreg_field(security_state); 33 update_feat_ebep_idreg_field(security_state); 34 } 35 36 void idte3_init_cached_idregs_per_world(size_t security_state) 37 { 38 39 assert(security_state < CPU_CONTEXT_NUM); 40 41 per_world_context_t *per_world_ctx = &per_world_context[security_state]; 42 perworld_idregs_t *reg = &(per_world_ctx->idregs); 43 44 reg->id_aa64pfr0_el1 = read_id_aa64pfr0_el1(); 45 reg->id_aa64pfr1_el1 = read_id_aa64pfr1_el1(); 46 reg->id_aa64pfr2_el1 = read_id_aa64pfr2_el1(); 47 reg->id_aa64smfr0_el1 = read_id_aa64smfr0_el1(); 48 reg->id_aa64isar0_el1 = read_id_aa64isar0_el1(); 49 reg->id_aa64isar1_el1 = read_id_aa64isar1_el1(); 50 reg->id_aa64isar2_el1 = read_id_aa64isar2_el1(); 51 reg->id_aa64isar3_el1 = read_id_aa64isar3_el1(); 52 reg->id_aa64mmfr0_el1 = read_id_aa64mmfr0_el1(); 53 reg->id_aa64mmfr1_el1 = read_id_aa64mmfr1_el1(); 54 reg->id_aa64mmfr2_el1 = read_id_aa64mmfr2_el1(); 55 reg->id_aa64mmfr3_el1 = read_id_aa64mmfr3_el1(); 56 reg->id_aa64mmfr4_el1 = read_id_aa64mmfr4_el1(); 57 58 update_feat_pan_idreg_field(security_state); 59 update_feat_vhe_idreg_field(security_state); 60 update_feat_ttcnp_idreg_field(security_state); 61 update_feat_uao_idreg_field(security_state); 62 update_feat_pacqarma3_idreg_field(security_state); 63 update_feat_pauth_idreg_field(security_state); 64 update_feat_ttst_idreg_field(security_state); 65 update_feat_bti_idreg_field(security_state); 66 update_feat_mte2_idreg_field(security_state); 67 update_feat_ssbs_idreg_field(security_state); 68 update_feat_nmi_idreg_field(security_state); 69 update_feat_gcs_idreg_field(security_state); 70 update_feat_ebep_idreg_field(security_state); 71 update_feat_sel2_idreg_field(security_state); 72 update_feat_twed_idreg_field(security_state); 73 update_feat_fgt_idreg_field(security_state); 74 update_feat_ecv_idreg_field(security_state); 75 update_feat_rng_idreg_field(security_state); 76 update_feat_tcr2_idreg_field(security_state); 77 update_feat_s2poe_idreg_field(security_state); 78 update_feat_s1poe_idreg_field(security_state); 79 update_feat_s2pie_idreg_field(security_state); 80 update_feat_s1pie_idreg_field(security_state); 81 update_feat_amu_idreg_field(security_state); 82 update_feat_mpam_idreg_field(security_state); 83 update_feat_hcx_idreg_field(security_state); 84 update_feat_rng_trap_idreg_field(security_state); 85 update_feat_sb_idreg_field(security_state); 86 update_feat_csv2_2_idreg_field(security_state); 87 update_feat_sve_idreg_field(security_state); 88 update_feat_ras_idreg_field(security_state); 89 update_feat_dit_idreg_field(security_state); 90 update_feat_trbe_idreg_field(security_state); 91 update_feat_sme_idreg_field(security_state); 92 update_feat_fgt2_idreg_field(security_state); 93 update_feat_the_idreg_field(security_state); 94 update_feat_sctlr2_idreg_field(security_state); 95 update_feat_d128_idreg_field(security_state); 96 update_feat_ls64_accdata_idreg_field(security_state); 97 update_feat_fpmr_idreg_field(security_state); 98 update_feat_mops_idreg_field(security_state); 99 update_feat_fgwte3_idreg_field(security_state); 100 update_feat_cpa2_idreg_field(security_state); 101 update_feat_idte3_idreg_field(security_state); 102 update_feat_uinj_idreg_field(security_state); 103 } 104 105 int handle_idreg_trap(uint64_t esr_el3, cpu_context_t *ctx, u_register_t flags) 106 { 107 uint32_t iss = (uint32_t) ESR_ELx_ISS(esr_el3); 108 uint8_t rt = (uint8_t) ISS_SYS64_RT(iss); 109 uint8_t op0 = (uint8_t) ISS_SYS64_OP0(iss); 110 uint8_t op1 = (uint8_t) ISS_SYS64_OP1(iss); 111 uint8_t CRn = (uint8_t) ISS_SYS64_CRN(iss); 112 uint8_t CRm = (uint8_t) ISS_SYS64_CRM(iss); 113 uint8_t op2 = (uint8_t) ISS_SYS64_OP2(iss); 114 115 u_register_t idreg = esr_el3 & ESR_EL3_SYSREG_MASK; 116 117 u_register_t value = 0ULL; 118 size_t security_state = GET_SECURITY_STATE(flags); 119 percpu_idregs_t *percpu_reg = &(get_cpu_data(idregs[security_state])); 120 121 per_world_context_t *per_world_ctx = 122 &per_world_context[get_cpu_context_index(security_state)]; 123 perworld_idregs_t *perworld_reg = &(per_world_ctx->idregs); 124 125 switch (idreg) { 126 case ESR_EL3_IDREG_ID_AA64PFR0_EL1: 127 value = perworld_reg->id_aa64pfr0_el1; 128 break; 129 case ESR_EL3_IDREG_ID_AA64PFR1_EL1: 130 value = perworld_reg->id_aa64pfr1_el1; 131 break; 132 case ESR_EL3_IDREG_ID_AA64PFR2_EL1: 133 value = perworld_reg->id_aa64pfr2_el1; 134 break; 135 case ESR_EL3_IDREG_ID_AA64SMFR0_EL1: 136 value = perworld_reg->id_aa64smfr0_el1; 137 break; 138 case ESR_EL3_IDREG_ID_AA64ISAR0_EL1: 139 value = perworld_reg->id_aa64isar0_el1; 140 break; 141 case ESR_EL3_IDREG_ID_AA64ISAR1_EL1: 142 value = perworld_reg->id_aa64isar1_el1; 143 break; 144 case ESR_EL3_IDREG_ID_AA64ISAR2_EL1: 145 value = perworld_reg->id_aa64isar2_el1; 146 break; 147 case ESR_EL3_IDREG_ID_AA64ISAR3_EL1: 148 value = perworld_reg->id_aa64isar3_el1; 149 break; 150 case ESR_EL3_IDREG_ID_AA64MMFR0_EL1: 151 value = perworld_reg->id_aa64mmfr0_el1; 152 break; 153 case ESR_EL3_IDREG_ID_AA64MMFR1_EL1: 154 value = perworld_reg->id_aa64mmfr1_el1; 155 break; 156 case ESR_EL3_IDREG_ID_AA64MMFR2_EL1: 157 value = perworld_reg->id_aa64mmfr2_el1; 158 break; 159 case ESR_EL3_IDREG_ID_AA64MMFR3_EL1: 160 value = perworld_reg->id_aa64mmfr3_el1; 161 break; 162 case ESR_EL3_IDREG_ID_AA64MMFR4_EL1: 163 value = perworld_reg->id_aa64mmfr4_el1; 164 break; 165 case ESR_EL3_IDREG_ID_AA64DFR0_EL1: 166 value = percpu_reg->id_aa64dfr0_el1; 167 break; 168 case ESR_EL3_IDREG_ID_AA64DFR1_EL1: 169 value = percpu_reg->id_aa64dfr1_el1; 170 break; 171 case ESR_EL3_IDREG_ID_AA64ZFR0_EL1: 172 value = read_id_aa64zfr0_el1(); 173 break; 174 case ESR_EL3_IDREG_ID_AA64FPFR0_EL1: 175 value = read_id_aa64fpfr0_el1(); 176 break; 177 case ESR_EL3_IDREG_ID_AA64DFR2_EL1: 178 value = read_id_aa64dfr2_el1(); 179 break; 180 case ESR_EL3_IDREG_ID_AA64AFR0_EL1: 181 value = read_id_aa64afr0_el1(); 182 break; 183 case ESR_EL3_IDREG_ID_AA64AFR1_EL1: 184 value = read_id_aa64afr1_el1(); 185 break; 186 case ESR_EL3_IDREG_GMID_EL1: 187 value = read_gmid_el1(); 188 break; 189 case ESR_EL3_IDREG_ID_PFR0_EL1: 190 value = read_id_pfr0_el1(); 191 break; 192 case ESR_EL3_IDREG_ID_PFR1_EL1: 193 value = read_id_pfr1_el1(); 194 break; 195 case ESR_EL3_IDREG_ID_DFR0_EL1: 196 value = read_id_dfr0_el1(); 197 break; 198 case ESR_EL3_IDREG_ID_AFR0_EL1: 199 value = read_id_afr0_el1(); 200 break; 201 case ESR_EL3_IDREG_ID_PFR2_EL1: 202 value = read_id_pfr2_el1(); 203 break; 204 case ESR_EL3_IDREG_ID_DFR1_EL1: 205 value = read_id_dfr1_el1(); 206 break; 207 case ESR_EL3_IDREG_ID_MMFR0_EL1: 208 value = read_id_mmfr0_el1(); 209 break; 210 case ESR_EL3_IDREG_ID_MMFR1_EL1: 211 value = read_id_mmfr1_el1(); 212 break; 213 case ESR_EL3_IDREG_ID_MMFR2_EL1: 214 value = read_id_mmfr2_el1(); 215 break; 216 case ESR_EL3_IDREG_ID_MMFR3_EL1: 217 value = read_id_mmfr3_el1(); 218 break; 219 case ESR_EL3_IDREG_ID_MMFR4_EL1: 220 value = read_id_mmfr4_el1(); 221 break; 222 case ESR_EL3_IDREG_ID_MMFR5_EL1: 223 value = read_id_mmfr5_el1(); 224 break; 225 case ESR_EL3_IDREG_ID_ISAR0_EL1: 226 value = read_id_isar0_el1(); 227 break; 228 case ESR_EL3_IDREG_ID_ISAR1_EL1: 229 value = read_id_isar1_el1(); 230 break; 231 case ESR_EL3_IDREG_ID_ISAR2_EL1: 232 value = read_id_isar2_el1(); 233 break; 234 case ESR_EL3_IDREG_ID_ISAR3_EL1: 235 value = read_id_isar3_el1(); 236 break; 237 case ESR_EL3_IDREG_ID_ISAR4_EL1: 238 value = read_id_isar4_el1(); 239 break; 240 case ESR_EL3_IDREG_ID_ISAR5_EL1: 241 value = read_id_isar5_el1(); 242 break; 243 case ESR_EL3_IDREG_ID_ISAR6_EL1: 244 value = read_id_isar6_el1(); 245 break; 246 case ESR_EL3_IDREG_MVFR0_EL1: 247 value = read_mvfr0_el1(); 248 break; 249 case ESR_EL3_IDREG_MVFR1_EL1: 250 value = read_mvfr1_el1(); 251 break; 252 case ESR_EL3_IDREG_MVFR2_EL1: 253 value = read_mvfr2_el1(); 254 break; 255 256 /* 257 * Any ID register access that falls within the Group 3 258 * ID space (op0 == 3, op1 == 0, CRn == 0, CRm == {2-7}, op2 == {0-7}) 259 * but is not explicitly handled here will return 0. 260 * This covers newly introduced ID registers that were previously 261 * reserved or unknown. 262 * 263 * When new ID registers are added in future revisions of 264 * the architecture, they must be explicitly handled in this 265 * switch statement to return their actual value instead of 266 * Res0. 267 */ 268 default: 269 WARN("Unknown ID register: S%u_%u_C%u_C%u_%u is trapped\n", 270 op0, op1, CRn, CRm, op2); 271 value = 0UL; 272 } 273 274 ctx->gpregs_ctx.ctx_regs[rt] = value; 275 return TRAP_RET_CONTINUE; 276 } 277 278 void idte3_enable(cpu_context_t *context) 279 { 280 u_register_t reg; 281 el3_state_t *state; 282 283 state = get_el3state_ctx(context); 284 285 /* 286 * Setting the TID3 & TID5 bits enables trapping for 287 * group 3 ID registers and group 5 288 * ID register - GMID_EL1. 289 */ 290 291 reg = read_ctx_reg(state, CTX_SCR_EL3); 292 reg |= (SCR_TID3_BIT | SCR_TID5_BIT); 293 write_ctx_reg(state, CTX_SCR_EL3, reg); 294 } 295