1 2 /* 3 * Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved. 4 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 5 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 6 * 7 * SPDX-License-Identifier: BSD-3-Clause 8 */ 9 10 #include <assert.h> 11 #include <common/debug.h> 12 #include <common/runtime_svc.h> 13 #include <drivers/delay_timer.h> 14 #include <lib/mmio.h> 15 #include <tools_share/uuid.h> 16 17 #include "lib/utils/alignment_utils.h" 18 #include "socfpga_fcs.h" 19 #include "socfpga_mailbox.h" 20 #include "socfpga_plat_def.h" 21 #include "socfpga_reset_manager.h" 22 #include "socfpga_sip_svc.h" 23 #include "socfpga_system_manager.h" 24 25 /* Total buffer the driver can hold */ 26 #define FPGA_CONFIG_BUFFER_SIZE 4 27 28 static config_type request_type = NO_REQUEST; 29 static int current_block, current_buffer; 30 static int read_block, max_blocks; 31 static uint32_t send_id, rcv_id; 32 static uint32_t bytes_per_block, blocks_submitted; 33 static bool bridge_disable; 34 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 35 static uint32_t g_remapper_bypass; 36 #endif 37 38 /* RSU static variables */ 39 static uint32_t rsu_dcmf_ver[4] = {0}; 40 static uint16_t rsu_dcmf_stat[4] = {0}; 41 static uint32_t rsu_max_retry; 42 43 /* SiP Service UUID */ 44 DEFINE_SVC_UUID2(intl_svc_uid, 45 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 46 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 47 48 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 49 uint64_t x1, 50 uint64_t x2, 51 uint64_t x3, 52 uint64_t x4, 53 void *cookie, 54 void *handle, 55 uint64_t flags) 56 { 57 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 58 SMC_RET1(handle, SMC_UNK); 59 } 60 61 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 62 63 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 64 { 65 uint32_t args[3]; 66 67 while (max_blocks > 0 && buffer->size > buffer->size_written) { 68 args[0] = (1<<8); 69 args[1] = buffer->addr + buffer->size_written; 70 if (buffer->size - buffer->size_written <= bytes_per_block) { 71 args[2] = buffer->size - buffer->size_written; 72 current_buffer++; 73 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 74 } else { 75 args[2] = bytes_per_block; 76 } 77 78 buffer->size_written += args[2]; 79 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 80 3U, CMD_INDIRECT); 81 82 buffer->subblocks_sent++; 83 max_blocks--; 84 } 85 86 return !max_blocks; 87 } 88 89 static int intel_fpga_sdm_write_all(void) 90 { 91 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 92 if (intel_fpga_sdm_write_buffer( 93 &fpga_config_buffers[current_buffer])) { 94 break; 95 } 96 } 97 return 0; 98 } 99 100 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t *err_states) 101 { 102 uint32_t ret; 103 104 if (err_states == NULL) 105 return INTEL_SIP_SMC_STATUS_REJECTED; 106 107 switch (request_type) { 108 case RECONFIGURATION: 109 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 110 true, err_states); 111 break; 112 case BITSTREAM_AUTH: 113 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 114 false, err_states); 115 break; 116 default: 117 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 118 false, err_states); 119 break; 120 } 121 122 if (ret != 0U) { 123 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 124 return INTEL_SIP_SMC_STATUS_BUSY; 125 } else { 126 request_type = NO_REQUEST; 127 return INTEL_SIP_SMC_STATUS_ERROR; 128 } 129 } 130 131 if (bridge_disable != 0U) { 132 socfpga_bridges_enable(~0); /* Enable bridge */ 133 bridge_disable = false; 134 } 135 request_type = NO_REQUEST; 136 137 return INTEL_SIP_SMC_STATUS_OK; 138 } 139 140 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 141 { 142 int i; 143 144 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 145 if (fpga_config_buffers[i].block_number == current_block) { 146 fpga_config_buffers[i].subblocks_sent--; 147 if (fpga_config_buffers[i].subblocks_sent == 0 148 && fpga_config_buffers[i].size <= 149 fpga_config_buffers[i].size_written) { 150 fpga_config_buffers[i].write_requested = 0; 151 current_block++; 152 *buffer_addr_completed = 153 fpga_config_buffers[i].addr; 154 return 0; 155 } 156 } 157 } 158 159 return -1; 160 } 161 162 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 163 uint32_t *count, uint32_t *job_id) 164 { 165 uint32_t resp[5]; 166 unsigned int resp_len = ARRAY_SIZE(resp); 167 int status = INTEL_SIP_SMC_STATUS_OK; 168 int all_completed = 1; 169 *count = 0; 170 171 while (*count < 3) { 172 173 status = mailbox_read_response(job_id, 174 resp, &resp_len); 175 176 if (status < 0) { 177 break; 178 } 179 180 max_blocks++; 181 182 if (mark_last_buffer_xfer_completed( 183 &completed_addr[*count]) == 0) { 184 *count = *count + 1; 185 } else { 186 break; 187 } 188 } 189 190 if (*count <= 0) { 191 if (status != MBOX_NO_RESPONSE && 192 status != MBOX_TIMEOUT && resp_len != 0) { 193 mailbox_clear_response(); 194 request_type = NO_REQUEST; 195 return INTEL_SIP_SMC_STATUS_ERROR; 196 } 197 198 *count = 0; 199 } 200 201 intel_fpga_sdm_write_all(); 202 203 if (*count > 0) { 204 status = INTEL_SIP_SMC_STATUS_OK; 205 } else if (*count == 0) { 206 status = INTEL_SIP_SMC_STATUS_BUSY; 207 } 208 209 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 210 if (fpga_config_buffers[i].write_requested != 0) { 211 all_completed = 0; 212 break; 213 } 214 } 215 216 if (all_completed == 1) { 217 return INTEL_SIP_SMC_STATUS_OK; 218 } 219 220 return status; 221 } 222 223 static int intel_fpga_config_start(uint32_t flag) 224 { 225 uint32_t argument = 0x1; 226 uint32_t response[3]; 227 int status = 0; 228 unsigned int size = 0; 229 unsigned int resp_len = ARRAY_SIZE(response); 230 231 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 232 /* 233 * To trigger isolation 234 * FPGA configuration complete signal should be de-asserted 235 */ 236 INFO("SOCFPGA: Request SDM to trigger isolation\n"); 237 status = mailbox_send_fpga_config_comp(); 238 239 if (status < 0) { 240 INFO("SOCFPGA: Isolation for FPGA configuration complete is not executed\n"); 241 } 242 #endif 243 244 request_type = RECONFIGURATION; 245 246 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 247 bridge_disable = true; 248 } 249 250 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 251 size = 1; 252 bridge_disable = false; 253 request_type = BITSTREAM_AUTH; 254 } 255 256 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 257 intel_smmu_hps_remapper_init(0U); 258 #endif 259 260 mailbox_clear_response(); 261 262 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 263 CMD_CASUAL, NULL, NULL); 264 265 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 266 CMD_CASUAL, response, &resp_len); 267 268 if (status < 0) { 269 bridge_disable = false; 270 request_type = NO_REQUEST; 271 return INTEL_SIP_SMC_STATUS_ERROR; 272 } 273 274 max_blocks = response[0]; 275 bytes_per_block = response[1]; 276 277 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 278 fpga_config_buffers[i].size = 0; 279 fpga_config_buffers[i].size_written = 0; 280 fpga_config_buffers[i].addr = 0; 281 fpga_config_buffers[i].write_requested = 0; 282 fpga_config_buffers[i].block_number = 0; 283 fpga_config_buffers[i].subblocks_sent = 0; 284 } 285 286 blocks_submitted = 0; 287 current_block = 0; 288 read_block = 0; 289 current_buffer = 0; 290 291 /* Disable bridge on full reconfiguration */ 292 if (bridge_disable) { 293 socfpga_bridges_disable(~0); 294 } 295 296 return INTEL_SIP_SMC_STATUS_OK; 297 } 298 299 static bool is_fpga_config_buffer_full(void) 300 { 301 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 302 if (!fpga_config_buffers[i].write_requested) { 303 return false; 304 } 305 } 306 return true; 307 } 308 309 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 310 { 311 uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE; 312 uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size; 313 314 if (!addr && !size) { 315 return true; 316 } 317 if (size > (UINT64_MAX - addr)) { 318 return false; 319 } 320 if (addr < BL31_LIMIT) { 321 return false; 322 } 323 if (dram_region_end > dram_max_sz) { 324 return false; 325 } 326 327 return true; 328 } 329 330 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 331 { 332 int i; 333 334 intel_fpga_sdm_write_all(); 335 336 if (!is_address_in_ddr_range(mem, size) || 337 is_fpga_config_buffer_full()) { 338 return INTEL_SIP_SMC_STATUS_REJECTED; 339 } 340 341 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 342 intel_smmu_hps_remapper_init(&mem); 343 #endif 344 345 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 346 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 347 348 if (!fpga_config_buffers[j].write_requested) { 349 fpga_config_buffers[j].addr = mem; 350 fpga_config_buffers[j].size = size; 351 fpga_config_buffers[j].size_written = 0; 352 fpga_config_buffers[j].write_requested = 1; 353 fpga_config_buffers[j].block_number = 354 blocks_submitted++; 355 fpga_config_buffers[j].subblocks_sent = 0; 356 break; 357 } 358 } 359 360 if (is_fpga_config_buffer_full()) { 361 return INTEL_SIP_SMC_STATUS_BUSY; 362 } 363 364 return INTEL_SIP_SMC_STATUS_OK; 365 } 366 367 static int is_out_of_sec_range(uint64_t reg_addr) 368 { 369 #if DEBUG 370 return 0; 371 #endif 372 373 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 374 if (is_agilex5_A5F4() == true) { 375 switch (reg_addr) { 376 /* TSN stream control registers — only accessible on Agilex5 B0 */ 377 case SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN0): 378 case SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN1): 379 case SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN2): 380 return 0; 381 382 default: 383 break; 384 } 385 } 386 #endif 387 388 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 389 switch (reg_addr) { 390 case(0xF8011100): /* ECCCTRL1 */ 391 case(0xF8011104): /* ECCCTRL2 */ 392 case(0xF8011110): /* ERRINTEN */ 393 case(0xF8011114): /* ERRINTENS */ 394 case(0xF8011118): /* ERRINTENR */ 395 case(0xF801111C): /* INTMODE */ 396 case(0xF8011120): /* INTSTAT */ 397 case(0xF8011124): /* DIAGINTTEST */ 398 case(0xF801112C): /* DERRADDRA */ 399 case(0xFA000000): /* SMMU SCR0 */ 400 case(0xFA000004): /* SMMU SCR1 */ 401 case(0xFA000400): /* SMMU NSCR0 */ 402 case(0xFA004000): /* SMMU SSD0_REG */ 403 case(0xFA000820): /* SMMU SMR8 */ 404 case(0xFA000c20): /* SMMU SCR8 */ 405 case(0xFA028000): /* SMMU CB8_SCTRL */ 406 case(0xFA001020): /* SMMU CBAR8 */ 407 case(0xFA028030): /* SMMU TCR_LPAE */ 408 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 409 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 410 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 411 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 412 case(0xFA028010): /* SMMU_CB8)TCR2 */ 413 case(0xFA001820): /* SMMU_CBA2R8 */ 414 case(0xFA000074): /* SMMU_STLBGSTATUS */ 415 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 416 case(0xFA000060): /* SMMU_STLBIALL */ 417 case(0xFA000070): /* SMMU_STLBGSYNC */ 418 case(0xFA028618): /* CB8_TLBALL */ 419 case(0xFA0287F0): /* CB8_TLBSYNC */ 420 case(0xFFD12028): /* SDMMCGRP_CTRL */ 421 case(0xFFD12044): /* EMAC0 */ 422 case(0xFFD12048): /* EMAC1 */ 423 case(0xFFD1204C): /* EMAC2 */ 424 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 425 case(0xFFD12094): /* ECC_INT_MASK_SET */ 426 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 427 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 428 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 429 case(0xFFD120C0): /* NOC_TIMEOUT */ 430 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 431 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 432 case(0xFFD120D0): /* NOC_IDLEACK */ 433 case(0xFFD120D4): /* NOC_IDLESTATUS */ 434 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 435 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 436 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 437 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 438 return 0; 439 #else 440 switch (reg_addr) { 441 442 case(0xF8011104): /* ECCCTRL2 */ 443 case(0xFFD12028): /* SDMMCGRP_CTRL */ 444 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 445 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 446 case(0xFFD120D0): /* NOC_IDLEACK */ 447 448 449 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */ 450 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */ 451 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */ 452 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */ 453 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */ 454 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */ 455 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */ 456 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */ 457 458 case(SOCFPGA_ECC_QSPI(INITSTAT)): /* ECC_QSPI_INITSTAT */ 459 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */ 460 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */ 461 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */ 462 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */ 463 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */ 464 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */ 465 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */ 466 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */ 467 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */ 468 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */ 469 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */ 470 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */ 471 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */ 472 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */ 473 #endif 474 case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */ 475 case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */ 476 case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */ 477 case(SOCFPGA_ECC_QSPI(ERRINTENR)): /* ECC_QSPI_ERRINTENR */ 478 case(SOCFPGA_ECC_QSPI(INTMODE)): /* ECC_QSPI_INTMODE */ 479 case(SOCFPGA_ECC_QSPI(ECC_ACCCTRL)): /* ECC_QSPI_ECC_ACCCTRL */ 480 case(SOCFPGA_ECC_QSPI(ECC_STARTACC)): /* ECC_QSPI_ECC_STARTACC */ 481 case(SOCFPGA_ECC_QSPI(ECC_WDCTRL)): /* ECC_QSPI_ECC_WDCTRL */ 482 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 483 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 484 return 0; 485 486 default: 487 break; 488 } 489 490 return -1; 491 } 492 493 /* Secure register access */ 494 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 495 { 496 if (is_out_of_sec_range(reg_addr)) { 497 return INTEL_SIP_SMC_STATUS_ERROR; 498 } 499 500 *retval = mmio_read_32(reg_addr); 501 502 return INTEL_SIP_SMC_STATUS_OK; 503 } 504 505 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 506 uint32_t *retval) 507 { 508 if (is_out_of_sec_range(reg_addr)) { 509 return INTEL_SIP_SMC_STATUS_ERROR; 510 } 511 512 switch (reg_addr) { 513 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 514 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 515 mmio_write_16(reg_addr, val); 516 break; 517 default: 518 mmio_write_32(reg_addr, val); 519 break; 520 } 521 522 return intel_secure_reg_read(reg_addr, retval); 523 } 524 525 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 526 uint32_t val, uint32_t *retval) 527 { 528 if (!intel_secure_reg_read(reg_addr, retval)) { 529 *retval &= ~mask; 530 *retval |= val & mask; 531 return intel_secure_reg_write(reg_addr, *retval, retval); 532 } 533 534 return INTEL_SIP_SMC_STATUS_ERROR; 535 } 536 537 /* Intel Remote System Update (RSU) services */ 538 uint64_t intel_rsu_update_address; 539 540 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 541 { 542 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 543 return INTEL_SIP_SMC_RSU_ERROR; 544 } 545 546 return INTEL_SIP_SMC_STATUS_OK; 547 } 548 549 static uint32_t intel_rsu_get_device_info(uint32_t *respbuf, 550 unsigned int respbuf_sz) 551 { 552 if (mailbox_rsu_get_device_info((uint32_t *)respbuf, respbuf_sz) < 0) { 553 return INTEL_SIP_SMC_RSU_ERROR; 554 } 555 556 return INTEL_SIP_SMC_STATUS_OK; 557 } 558 559 uint32_t intel_rsu_update(uint64_t update_address) 560 { 561 if (update_address > SIZE_MAX) { 562 return INTEL_SIP_SMC_STATUS_REJECTED; 563 } 564 565 intel_rsu_update_address = update_address; 566 return INTEL_SIP_SMC_STATUS_OK; 567 } 568 569 static uint32_t intel_rsu_notify(uint32_t execution_stage) 570 { 571 if (mailbox_hps_stage_notify(execution_stage) < 0) { 572 return INTEL_SIP_SMC_RSU_ERROR; 573 } 574 575 return INTEL_SIP_SMC_STATUS_OK; 576 } 577 578 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 579 uint32_t *ret_stat) 580 { 581 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 582 return INTEL_SIP_SMC_RSU_ERROR; 583 } 584 585 *ret_stat = respbuf[8]; 586 return INTEL_SIP_SMC_STATUS_OK; 587 } 588 589 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 590 uint64_t dcmf_ver_3_2) 591 { 592 rsu_dcmf_ver[0] = dcmf_ver_1_0; 593 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 594 rsu_dcmf_ver[2] = dcmf_ver_3_2; 595 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 596 597 return INTEL_SIP_SMC_STATUS_OK; 598 } 599 600 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 601 { 602 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 603 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 604 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 605 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 606 607 return INTEL_SIP_SMC_STATUS_OK; 608 } 609 610 /* Intel HWMON services */ 611 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 612 { 613 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 614 return INTEL_SIP_SMC_STATUS_ERROR; 615 } 616 617 return INTEL_SIP_SMC_STATUS_OK; 618 } 619 620 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 621 { 622 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 623 return INTEL_SIP_SMC_STATUS_ERROR; 624 } 625 626 return INTEL_SIP_SMC_STATUS_OK; 627 } 628 629 /* Mailbox services */ 630 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 631 { 632 int status; 633 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 634 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 635 636 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 637 CMD_CASUAL, resp_data, &resp_len); 638 639 if (status < 0) { 640 return INTEL_SIP_SMC_STATUS_ERROR; 641 } 642 643 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 644 return INTEL_SIP_SMC_STATUS_ERROR; 645 } 646 647 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 648 649 return INTEL_SIP_SMC_STATUS_OK; 650 } 651 652 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 653 unsigned int len, uint32_t urgent, uint64_t response, 654 unsigned int resp_len, int *mbox_status, 655 unsigned int *len_in_resp) 656 { 657 *len_in_resp = 0; 658 *mbox_status = GENERIC_RESPONSE_ERROR; 659 660 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 661 return INTEL_SIP_SMC_STATUS_REJECTED; 662 } 663 664 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 665 (uint32_t *) response, &resp_len); 666 667 if (status < 0) { 668 *mbox_status = -status; 669 return INTEL_SIP_SMC_STATUS_ERROR; 670 } 671 672 *mbox_status = 0; 673 *len_in_resp = resp_len; 674 675 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 676 677 return INTEL_SIP_SMC_STATUS_OK; 678 } 679 680 static int intel_smc_get_usercode(uint32_t *user_code) 681 { 682 int status; 683 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 684 685 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 686 0U, CMD_CASUAL, user_code, &resp_len); 687 688 if (status < 0) { 689 return INTEL_SIP_SMC_STATUS_ERROR; 690 } 691 692 return INTEL_SIP_SMC_STATUS_OK; 693 } 694 695 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 696 uint32_t mode, uint32_t *job_id, 697 uint32_t *ret_size, uint32_t *mbox_error) 698 { 699 int status = 0; 700 uint32_t resp_len = size / MBOX_WORD_BYTE; 701 702 if (resp_len > MBOX_DATA_MAX_LEN) { 703 return INTEL_SIP_SMC_STATUS_REJECTED; 704 } 705 706 if (!is_address_in_ddr_range(addr, size)) { 707 return INTEL_SIP_SMC_STATUS_REJECTED; 708 } 709 710 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 711 status = mailbox_read_response_async(job_id, 712 NULL, (uint32_t *) addr, &resp_len, 0); 713 } else { 714 status = mailbox_read_response(job_id, 715 (uint32_t *) addr, &resp_len); 716 717 if (status == MBOX_NO_RESPONSE) { 718 status = MBOX_BUSY; 719 } 720 } 721 722 if (status == MBOX_NO_RESPONSE) { 723 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 724 } 725 726 if (status == MBOX_BUSY) { 727 return INTEL_SIP_SMC_STATUS_BUSY; 728 } 729 730 *ret_size = resp_len * MBOX_WORD_BYTE; 731 flush_dcache_range(addr, *ret_size); 732 733 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || 734 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { 735 *mbox_error = -status; 736 } else if (status != MBOX_RET_OK) { 737 *mbox_error = -status; 738 return INTEL_SIP_SMC_STATUS_ERROR; 739 } 740 741 return INTEL_SIP_SMC_STATUS_OK; 742 } 743 744 /* Miscellaneous HPS services */ 745 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 746 { 747 int status = 0; 748 749 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 750 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 751 status = socfpga_bridges_enable((uint32_t)mask); 752 } else { 753 status = socfpga_bridges_enable(~0); 754 } 755 } else { 756 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 757 status = socfpga_bridges_disable((uint32_t)mask); 758 } else { 759 status = socfpga_bridges_disable(~0); 760 } 761 } 762 763 if (status < 0) { 764 return INTEL_SIP_SMC_STATUS_ERROR; 765 } 766 767 return INTEL_SIP_SMC_STATUS_OK; 768 } 769 770 /* SDM SEU Error services */ 771 static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz) 772 { 773 if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) { 774 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 775 } 776 777 return INTEL_SIP_SMC_STATUS_OK; 778 } 779 780 /* SDM SAFE SEU Error inject services */ 781 static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len) 782 { 783 if (mailbox_safe_inject_seu_err(command, len) < 0) { 784 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 785 } 786 787 return INTEL_SIP_SMC_STATUS_OK; 788 } 789 790 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 791 /* SMMU HPS Remapper */ 792 void intel_smmu_hps_remapper_init(uint64_t *mem) 793 { 794 /* Read out Bit 1 value */ 795 uint32_t remap = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_1)) & 0x02); 796 797 if ((remap == 0x00) && (g_remapper_bypass == 0x00)) { 798 /* Update DRAM Base address for SDM SMMU */ 799 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), DRAM_BASE); 800 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), DRAM_BASE); 801 *mem = *mem - DRAM_BASE; 802 } else { 803 *mem = *mem - DRAM_BASE; 804 } 805 } 806 807 int intel_smmu_hps_remapper_config(uint32_t remapper_bypass) 808 { 809 /* Read out the JTAG-ID from boot scratch register */ 810 if (is_agilex5_A5C0() || is_agilex5_A5C4()) { 811 if (remapper_bypass == 0x01) { 812 g_remapper_bypass = remapper_bypass; 813 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), 0); 814 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), 0); 815 } 816 } 817 return INTEL_SIP_SMC_STATUS_OK; 818 } 819 820 static void intel_inject_io96b_ecc_err(const uint32_t *syndrome, const uint32_t command) 821 { 822 volatile uint64_t atf_ddr_buffer; 823 volatile uint64_t val; 824 825 mmio_write_32(IOSSM_CMD_PARAM, *syndrome); 826 mmio_write_32(IOSSM_CMD_TRIG_OP, command); 827 udelay(IOSSM_ECC_ERR_INJ_DELAY_USECS); 828 atf_ddr_buffer = 0xCAFEBABEFEEDFACE; /* Write data */ 829 memcpy_s((void *)&val, sizeof(val), 830 (void *)&atf_ddr_buffer, sizeof(atf_ddr_buffer)); 831 832 /* Clear response_ready BIT0 of status_register before sending next command. */ 833 mmio_clrbits_32(IOSSM_CMD_RESP_STATUS, IOSSM_CMD_STATUS_RESP_READY); 834 } 835 #endif 836 837 #if SIP_SVC_V3 838 uint8_t sip_smc_cmd_cb_ret2(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 839 { 840 uint8_t ret_args_len = 0U; 841 sdm_response_t *resp = (sdm_response_t *)resp_desc; 842 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 843 844 (void)cmd; 845 /* Returns 3 SMC arguments for SMC_RET3 */ 846 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 847 ret_args[ret_args_len++] = resp->err_code; 848 849 return ret_args_len; 850 } 851 852 uint8_t sip_smc_cmd_cb_ret3(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 853 { 854 uint8_t ret_args_len = 0U; 855 sdm_response_t *resp = (sdm_response_t *)resp_desc; 856 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 857 858 (void)cmd; 859 /* Returns 3 SMC arguments for SMC_RET3 */ 860 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 861 ret_args[ret_args_len++] = resp->err_code; 862 ret_args[ret_args_len++] = resp->resp_data[0]; 863 864 return ret_args_len; 865 } 866 867 uint8_t sip_smc_ret_nbytes_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 868 { 869 uint8_t ret_args_len = 0U; 870 sdm_response_t *resp = (sdm_response_t *)resp_desc; 871 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 872 873 INFO("MBOX: %s: mailbox_err 0%x, nbytes_ret %d\n", 874 __func__, resp->err_code, resp->rcvd_resp_len * MBOX_WORD_BYTE); 875 876 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 877 ret_args[ret_args_len++] = resp->err_code; 878 ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE; 879 880 /* Flush the response data buffer. */ 881 flush_dcache_range((uintptr_t)cmd->cb_args, resp->rcvd_resp_len * MBOX_WORD_BYTE); 882 883 return ret_args_len; 884 } 885 886 uint8_t sip_smc_get_chipid_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 887 { 888 uint8_t ret_args_len = 0U; 889 sdm_response_t *resp = (sdm_response_t *)resp_desc; 890 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 891 892 (void)cmd; 893 INFO("MBOX: %s: mailbox_err 0%x, data[0] 0x%x, data[1] 0x%x\n", 894 __func__, resp->err_code, resp->resp_data[0], resp->resp_data[1]); 895 896 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 897 ret_args[ret_args_len++] = resp->err_code; 898 ret_args[ret_args_len++] = resp->resp_data[0]; 899 ret_args[ret_args_len++] = resp->resp_data[1]; 900 901 return ret_args_len; 902 } 903 904 uint8_t sip_smc_cmd_cb_rsu_status(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 905 { 906 uint8_t ret_args_len = 0U; 907 uint32_t retry_counter = ~0U; 908 uint32_t failure_source = 0U; 909 sdm_response_t *resp = (sdm_response_t *)resp_desc; 910 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 911 912 (void)cmd; 913 /* Get the failure source and current image retry counter value from the response. */ 914 failure_source = resp->resp_data[5] & RSU_VERSION_ACMF_MASK; 915 retry_counter = resp->resp_data[8]; 916 917 if ((retry_counter != ~0U) && (failure_source == 0U)) 918 resp->resp_data[5] |= RSU_VERSION_ACMF; 919 920 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 921 ret_args[ret_args_len++] = resp->err_code; 922 /* Current CMF */ 923 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[1], resp->resp_data[0]); 924 /* Last Failing CMF Address */ 925 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[3], resp->resp_data[2]); 926 /* Config State */ 927 ret_args[ret_args_len++] = resp->resp_data[4]; 928 /* Version */ 929 ret_args[ret_args_len++] = resp->resp_data[5]; 930 /* Failure Source */ 931 ret_args[ret_args_len++] = ((GENMASK(32, 17) & resp->resp_data[5]) >> 16); 932 /* Error location */ 933 ret_args[ret_args_len++] = resp->resp_data[6]; 934 /* Error details */ 935 ret_args[ret_args_len++] = resp->resp_data[7]; 936 /* Current image retry counter */ 937 ret_args[ret_args_len++] = resp->resp_data[8]; 938 939 return ret_args_len; 940 } 941 942 uint8_t sip_smc_cmd_cb_rsu_spt(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 943 { 944 uint8_t ret_args_len = 0U; 945 sdm_response_t *resp = (sdm_response_t *)resp_desc; 946 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 947 948 (void)cmd; 949 950 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 951 ret_args[ret_args_len++] = resp->err_code; 952 /* Sub Partition Table (SPT) 0 address */ 953 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[0], resp->resp_data[1]); 954 /* Sub Partition Table (SPT) 1 address */ 955 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[2], resp->resp_data[3]); 956 957 return ret_args_len; 958 } 959 960 static uintptr_t smc_ret(void *handle, uint64_t *ret_args, uint32_t ret_args_len) 961 { 962 963 switch (ret_args_len) { 964 case SMC_RET_ARGS_ONE: 965 VERBOSE("SVC V3: %s: x0 0x%lx\n", __func__, ret_args[0]); 966 SMC_RET1(handle, ret_args[0]); 967 break; 968 969 case SMC_RET_ARGS_TWO: 970 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx\n", __func__, ret_args[0], ret_args[1]); 971 SMC_RET2(handle, ret_args[0], ret_args[1]); 972 break; 973 974 case SMC_RET_ARGS_THREE: 975 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx\n", 976 __func__, ret_args[0], ret_args[1], ret_args[2]); 977 SMC_RET3(handle, ret_args[0], ret_args[1], ret_args[2]); 978 break; 979 980 case SMC_RET_ARGS_FOUR: 981 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx\n", 982 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3]); 983 SMC_RET4(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3]); 984 break; 985 986 case SMC_RET_ARGS_FIVE: 987 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx\n", 988 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]); 989 SMC_RET5(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]); 990 break; 991 992 case SMC_RET_ARGS_SIX: 993 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx x3 0x%lx, x4 0x%lx x5 0x%lx\n", 994 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 995 ret_args[5]); 996 SMC_RET6(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 997 ret_args[5]); 998 break; 999 1000 case SMC_RET_ARGS_SEVEN: 1001 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t" 1002 "x6 0x%lx\n", 1003 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1004 ret_args[5], ret_args[6]); 1005 SMC_RET7(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1006 ret_args[5], ret_args[6]); 1007 break; 1008 1009 case SMC_RET_ARGS_EIGHT: 1010 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t" 1011 "x6 0x%lx, x7 0x%lx\n", 1012 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1013 ret_args[5], ret_args[6], ret_args[7]); 1014 SMC_RET8(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1015 ret_args[5], ret_args[6], ret_args[7]); 1016 break; 1017 1018 case SMC_RET_ARGS_NINE: 1019 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t" 1020 "x6 0x%lx, x7 0x%lx, x8 0x%lx\n", 1021 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1022 ret_args[5], ret_args[6], ret_args[7], ret_args[8]); 1023 SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1024 ret_args[5], ret_args[6], ret_args[7], ret_args[8], 1025 0, 0, 0, 0, 0, 0, 0, 0, 0); 1026 break; 1027 1028 case SMC_RET_ARGS_TEN: 1029 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t" 1030 "x6 0x%lx, x7 0x%lx x8 0x%lx, x9 0x%lx, x10 0x%lx\n", 1031 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], 1032 ret_args[4], ret_args[5], ret_args[6], ret_args[7], ret_args[8], 1033 ret_args[9], ret_args[10]); 1034 SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1035 ret_args[5], ret_args[6], ret_args[7], ret_args[8], ret_args[9], 1036 0, 0, 0, 0, 0, 0, 0, 0); 1037 break; 1038 1039 default: 1040 VERBOSE("SVC V3: %s ret_args_len is wrong, please check %d\n ", 1041 __func__, ret_args_len); 1042 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 1043 break; 1044 } 1045 } 1046 1047 static inline bool is_gen_mbox_cmd_allowed(uint32_t cmd) 1048 { 1049 /* Check if the command is allowed to be executed in generic mbox format */ 1050 bool is_cmd_allowed = false; 1051 1052 switch (cmd) { 1053 case MBOX_FCS_OPEN_CS_SESSION: 1054 case MBOX_FCS_CLOSE_CS_SESSION: 1055 case MBOX_FCS_IMPORT_CS_KEY: 1056 case MBOX_FCS_EXPORT_CS_KEY: 1057 case MBOX_FCS_REMOVE_CS_KEY: 1058 case MBOX_FCS_GET_CS_KEY_INFO: 1059 case MBOX_FCS_CREATE_CS_KEY: 1060 case MBOX_FCS_GET_DIGEST_REQ: 1061 case MBOX_FCS_MAC_VERIFY_REQ: 1062 case MBOX_FCS_ECDSA_HASH_SIGN_REQ: 1063 case MBOX_FCS_GET_PROVISION: 1064 case MBOX_FCS_CNTR_SET_PREAUTH: 1065 case MBOX_FCS_ENCRYPT_REQ: 1066 case MBOX_FCS_DECRYPT_REQ: 1067 case MBOX_FCS_RANDOM_GEN: 1068 case MBOX_FCS_AES_CRYPT_REQ: 1069 case MBOX_FCS_ECDSA_SHA2_DATA_SIGN_REQ: 1070 case MBOX_FCS_ECDSA_HASH_SIG_VERIFY: 1071 case MBOX_FCS_ECDSA_SHA2_DATA_SIGN_VERIFY: 1072 case MBOX_FCS_ECDSA_GET_PUBKEY: 1073 case MBOX_FCS_ECDH_REQUEST: 1074 case MBOX_FCS_HKDF_REQUEST: 1075 /* These mailbox commands are not supported in the generic mailbox format. */ 1076 break; 1077 1078 default: 1079 is_cmd_allowed = true; 1080 break; 1081 } /* switch */ 1082 1083 return is_cmd_allowed; 1084 } 1085 1086 /* 1087 * This function is responsible for handling all SiP SVC V3 calls from the 1088 * non-secure world. 1089 */ 1090 static uintptr_t sip_smc_handler_v3(uint32_t smc_fid, 1091 u_register_t x1, 1092 u_register_t x2, 1093 u_register_t x3, 1094 u_register_t x4, 1095 void *cookie, 1096 void *handle, 1097 u_register_t flags) 1098 { 1099 int status = 0; 1100 uint32_t mbox_error = 0U; 1101 u_register_t x5, x6, x7, x8, x9, x10, x11; 1102 1103 /* Get all the SMC call arguments */ 1104 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1105 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1106 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1107 x8 = SMC_GET_GP(handle, CTX_GPREG_X8); 1108 x9 = SMC_GET_GP(handle, CTX_GPREG_X9); 1109 x10 = SMC_GET_GP(handle, CTX_GPREG_X10); 1110 x11 = SMC_GET_GP(handle, CTX_GPREG_X11); 1111 1112 INFO("MBOX: SVC_V3: x0 0x%x, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\n", 1113 smc_fid, x1, x2, x3, x4, x5); 1114 INFO("MBOX: SVC_V3: x6 0x%lx, x7 0x%lx, x8 0x%lx, x9 0x%lx, x10 0x%lx x11 0x%lx\n", 1115 x6, x7, x8, x9, x10, x11); 1116 1117 switch (smc_fid) { 1118 case ALTERA_SIP_SMC_ASYNC_RESP_POLL: 1119 { 1120 uint64_t ret_args[16] = {0}; 1121 uint32_t ret_args_len = 0; 1122 1123 status = mailbox_response_poll_v3(GET_CLIENT_ID(x1), 1124 GET_JOB_ID(x1), 1125 ret_args, 1126 &ret_args_len); 1127 /* Always reserve [0] index for command status. */ 1128 ret_args[0] = status; 1129 1130 /* Return SMC call based on the number of return arguments */ 1131 return smc_ret(handle, ret_args, ret_args_len); 1132 } 1133 1134 case ALTERA_SIP_SMC_ASYNC_RESP_POLL_ON_INTR: 1135 { 1136 /* TBD: Here now we don't need these CID and JID?? */ 1137 uint8_t client_id = 0U; 1138 uint8_t job_id = 0U; 1139 uint64_t trans_id_bitmap[4] = {0U}; 1140 1141 status = mailbox_response_poll_on_intr_v3(&client_id, 1142 &job_id, 1143 trans_id_bitmap); 1144 1145 SMC_RET5(handle, status, trans_id_bitmap[0], trans_id_bitmap[1], 1146 trans_id_bitmap[2], trans_id_bitmap[3]); 1147 break; 1148 } 1149 1150 case ALTERA_SIP_SMC_ASYNC_GET_DEVICE_IDENTITY: 1151 { 1152 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1153 GET_JOB_ID(x1), 1154 MBOX_CMD_GET_DEVICEID, 1155 NULL, 1156 0U, 1157 MBOX_CMD_FLAG_CASUAL, 1158 sip_smc_ret_nbytes_cb, 1159 (uint32_t *)x2, 1160 2); 1161 1162 SMC_RET1(handle, status); 1163 } 1164 1165 case ALTERA_SIP_SMC_ASYNC_GET_IDCODE: 1166 { 1167 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1168 GET_JOB_ID(x1), 1169 MBOX_CMD_GET_IDCODE, 1170 NULL, 1171 0U, 1172 MBOX_CMD_FLAG_CASUAL, 1173 sip_smc_cmd_cb_ret3, 1174 NULL, 1175 0); 1176 1177 SMC_RET1(handle, status); 1178 } 1179 1180 case ALTERA_SIP_SMC_ASYNC_QSPI_OPEN: 1181 { 1182 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1183 GET_JOB_ID(x1), 1184 MBOX_CMD_QSPI_OPEN, 1185 NULL, 1186 0U, 1187 MBOX_CMD_FLAG_CASUAL, 1188 sip_smc_cmd_cb_ret2, 1189 NULL, 1190 0U); 1191 1192 SMC_RET1(handle, status); 1193 } 1194 1195 case ALTERA_SIP_SMC_ASYNC_QSPI_CLOSE: 1196 { 1197 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1198 GET_JOB_ID(x1), 1199 MBOX_CMD_QSPI_CLOSE, 1200 NULL, 1201 0U, 1202 MBOX_CMD_FLAG_CASUAL, 1203 sip_smc_cmd_cb_ret2, 1204 NULL, 1205 0U); 1206 1207 SMC_RET1(handle, status); 1208 } 1209 1210 case ALTERA_SIP_SMC_ASYNC_QSPI_SET_CS: 1211 { 1212 uint32_t cmd_data = 0U; 1213 uint32_t chip_sel = (uint32_t)x2; 1214 uint32_t comb_addr_mode = (uint32_t)x3; 1215 uint32_t ext_dec_mode = (uint32_t)x4; 1216 1217 cmd_data = (chip_sel << MBOX_QSPI_SET_CS_OFFSET) | 1218 (comb_addr_mode << MBOX_QSPI_SET_CS_CA_OFFSET) | 1219 (ext_dec_mode << MBOX_QSPI_SET_CS_MODE_OFFSET); 1220 1221 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1222 GET_JOB_ID(x1), 1223 MBOX_CMD_QSPI_SET_CS, 1224 &cmd_data, 1225 1U, 1226 MBOX_CMD_FLAG_CASUAL, 1227 sip_smc_cmd_cb_ret2, 1228 NULL, 1229 0U); 1230 1231 SMC_RET1(handle, status); 1232 } 1233 1234 case ALTERA_SIP_SMC_ASYNC_QSPI_ERASE: 1235 { 1236 uint32_t qspi_addr = (uint32_t)x2; 1237 uint32_t qspi_nwords = (uint32_t)x3; 1238 1239 /* QSPI address offset to start erase, must be 4K aligned */ 1240 if (MBOX_IS_4K_ALIGNED(qspi_addr)) { 1241 ERROR("MBOX: 0x%x: QSPI address not 4K aligned\n", 1242 smc_fid); 1243 status = INTEL_SIP_SMC_STATUS_REJECTED; 1244 SMC_RET1(handle, status); 1245 } 1246 1247 /* Number of words to erase, multiples of 0x400 or 4K */ 1248 if (qspi_nwords % MBOX_QSPI_ERASE_SIZE_GRAN) { 1249 ERROR("MBOX: 0x%x: Given words not in multiples of 4K\n", 1250 smc_fid); 1251 status = INTEL_SIP_SMC_STATUS_REJECTED; 1252 SMC_RET1(handle, status); 1253 } 1254 1255 uint32_t cmd_data[2] = {qspi_addr, qspi_nwords}; 1256 1257 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1258 GET_JOB_ID(x1), 1259 MBOX_CMD_QSPI_ERASE, 1260 cmd_data, 1261 sizeof(cmd_data) / MBOX_WORD_BYTE, 1262 MBOX_CMD_FLAG_CASUAL, 1263 sip_smc_cmd_cb_ret2, 1264 NULL, 1265 0U); 1266 1267 SMC_RET1(handle, status); 1268 } 1269 1270 case ALTERA_SIP_SMC_ASYNC_QSPI_WRITE: 1271 { 1272 uint32_t *qspi_payload = (uint32_t *)x2; 1273 uint32_t qspi_total_nwords = (((uint32_t)x3) / MBOX_WORD_BYTE); 1274 uint32_t qspi_addr = qspi_payload[0]; 1275 uint32_t qspi_nwords = qspi_payload[1]; 1276 1277 if (!MBOX_IS_WORD_ALIGNED(qspi_addr)) { 1278 ERROR("MBOX: 0x%x: Given address is not WORD aligned\n", 1279 smc_fid); 1280 status = INTEL_SIP_SMC_STATUS_REJECTED; 1281 SMC_RET1(handle, status); 1282 } 1283 1284 if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) { 1285 ERROR("MBOX: 0x%x: Number of words exceeds max limit\n", 1286 smc_fid); 1287 status = INTEL_SIP_SMC_STATUS_REJECTED; 1288 SMC_RET1(handle, status); 1289 } 1290 1291 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1292 GET_JOB_ID(x1), 1293 MBOX_CMD_QSPI_WRITE, 1294 qspi_payload, 1295 qspi_total_nwords, 1296 MBOX_CMD_FLAG_CASUAL, 1297 sip_smc_cmd_cb_ret2, 1298 NULL, 1299 0U); 1300 1301 SMC_RET1(handle, status); 1302 } 1303 1304 case ALTERA_SIP_SMC_ASYNC_QSPI_READ: 1305 { 1306 uint32_t qspi_addr = (uint32_t)x2; 1307 uint32_t qspi_nwords = (((uint32_t)x4) / MBOX_WORD_BYTE); 1308 1309 if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) { 1310 ERROR("MBOX: 0x%x: Number of words exceeds max limit\n", 1311 smc_fid); 1312 status = INTEL_SIP_SMC_STATUS_REJECTED; 1313 SMC_RET1(handle, status); 1314 } 1315 1316 uint32_t cmd_data[2] = {qspi_addr, qspi_nwords}; 1317 1318 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1319 GET_JOB_ID(x1), 1320 MBOX_CMD_QSPI_READ, 1321 cmd_data, 1322 sizeof(cmd_data) / MBOX_WORD_BYTE, 1323 MBOX_CMD_FLAG_CASUAL, 1324 sip_smc_ret_nbytes_cb, 1325 (uint32_t *)x3, 1326 2); 1327 1328 SMC_RET1(handle, status); 1329 } 1330 1331 case ALTERA_SIP_SMC_ASYNC_QSPI_GET_DEV_INFO: 1332 { 1333 uint32_t *dst_addr = (uint32_t *)x2; 1334 1335 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1336 GET_JOB_ID(x1), 1337 MBOX_CMD_QSPI_GET_DEV_INFO, 1338 NULL, 1339 0U, 1340 MBOX_CMD_FLAG_CASUAL, 1341 sip_smc_ret_nbytes_cb, 1342 (uint32_t *)dst_addr, 1343 2); 1344 1345 SMC_RET1(handle, status); 1346 } 1347 1348 case ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT: 1349 case ALTERA_SIP_SMC_ASYNC_HWMON_READTEMP: 1350 { 1351 uint32_t channel = (uint32_t)x2; 1352 uint32_t mbox_cmd = ((smc_fid == ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT) ? 1353 MBOX_HWMON_READVOLT : MBOX_HWMON_READTEMP); 1354 1355 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1356 GET_JOB_ID(x1), 1357 mbox_cmd, 1358 &channel, 1359 1U, 1360 MBOX_CMD_FLAG_CASUAL, 1361 sip_smc_cmd_cb_ret3, 1362 NULL, 1363 0); 1364 1365 SMC_RET1(handle, status); 1366 } 1367 1368 case ALTERA_SIP_SMC_ASYNC_RSU_GET_SPT: 1369 { 1370 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1371 GET_JOB_ID(x1), 1372 MBOX_GET_SUBPARTITION_TABLE, 1373 NULL, 1374 0, 1375 MBOX_CMD_FLAG_CASUAL, 1376 sip_smc_cmd_cb_rsu_spt, 1377 NULL, 1378 0); 1379 1380 SMC_RET1(handle, status); 1381 } 1382 1383 case ALTERA_SIP_SMC_ASYNC_RSU_GET_STATUS: 1384 { 1385 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1386 GET_JOB_ID(x1), 1387 MBOX_RSU_STATUS, 1388 NULL, 1389 0, 1390 MBOX_CMD_FLAG_CASUAL, 1391 sip_smc_cmd_cb_rsu_status, 1392 NULL, 1393 0); 1394 1395 SMC_RET1(handle, status); 1396 } 1397 1398 case ALTERA_SIP_SMC_ASYNC_RSU_NOTIFY: 1399 { 1400 uint32_t notify_code = (uint32_t)x2; 1401 1402 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1403 GET_JOB_ID(x1), 1404 MBOX_HPS_STAGE_NOTIFY, 1405 ¬ify_code, 1406 1U, 1407 MBOX_CMD_FLAG_CASUAL, 1408 sip_smc_cmd_cb_ret2, 1409 NULL, 1410 0); 1411 1412 SMC_RET1(handle, status); 1413 } 1414 1415 case ALTERA_SIP_SMC_ASYNC_GEN_MBOX_CMD: 1416 { 1417 /* Collect all the args passed in, and send the mailbox command. */ 1418 uint32_t mbox_cmd = (uint32_t)x2; 1419 uint32_t *cmd_payload_addr = NULL; 1420 uint32_t cmd_payload_len = (uint32_t)x4 / MBOX_WORD_BYTE; 1421 uint32_t *resp_payload_addr = NULL; 1422 uint32_t resp_payload_len = (uint32_t)x6 / MBOX_WORD_BYTE; 1423 1424 /* Filter the required commands here. */ 1425 if (!is_gen_mbox_cmd_allowed(mbox_cmd)) { 1426 status = INTEL_SIP_SMC_STATUS_REJECTED; 1427 SMC_RET1(handle, status); 1428 } 1429 1430 if ((cmd_payload_len > MBOX_GEN_CMD_MAX_WORDS) || 1431 (resp_payload_len > MBOX_GEN_CMD_MAX_WORDS)) { 1432 ERROR("MBOX: 0x%x: Command/Response payload length exceeds max limit\n", 1433 smc_fid); 1434 status = INTEL_SIP_SMC_STATUS_REJECTED; 1435 SMC_RET1(handle, status); 1436 } 1437 1438 /* Make sure we have valid command payload length and buffer */ 1439 if (cmd_payload_len != 0U) { 1440 cmd_payload_addr = (uint32_t *)x3; 1441 if (cmd_payload_addr == NULL) { 1442 ERROR("MBOX: 0x%x: Command payload address is NULL\n", 1443 smc_fid); 1444 status = INTEL_SIP_SMC_STATUS_REJECTED; 1445 SMC_RET1(handle, status); 1446 } 1447 } 1448 1449 /* Make sure we have valid response payload length and buffer */ 1450 if (resp_payload_len != 0U) { 1451 resp_payload_addr = (uint32_t *)x5; 1452 if (resp_payload_addr == NULL) { 1453 ERROR("MBOX: 0x%x: Response payload address is NULL\n", 1454 smc_fid); 1455 status = INTEL_SIP_SMC_STATUS_REJECTED; 1456 SMC_RET1(handle, status); 1457 } 1458 } 1459 1460 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1461 GET_JOB_ID(x1), 1462 mbox_cmd, 1463 (uint32_t *)cmd_payload_addr, 1464 cmd_payload_len, 1465 MBOX_CMD_FLAG_CASUAL, 1466 sip_smc_ret_nbytes_cb, 1467 (uint32_t *)resp_payload_addr, 1468 resp_payload_len); 1469 1470 SMC_RET1(handle, status); 1471 } 1472 1473 case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT: 1474 { 1475 uint32_t session_id = (uint32_t)x2; 1476 uint32_t context_id = (uint32_t)x3; 1477 uint64_t ret_random_addr = (uint64_t)x4; 1478 uint32_t random_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1479 uint32_t crypto_header = 0U; 1480 1481 if ((random_len > (FCS_RANDOM_EXT_MAX_WORD_SIZE * MBOX_WORD_BYTE)) || 1482 (random_len == 0U) || 1483 (!is_size_4_bytes_aligned(random_len))) { 1484 ERROR("MBOX: 0x%x is rejected\n", smc_fid); 1485 status = INTEL_SIP_SMC_STATUS_REJECTED; 1486 SMC_RET1(handle, status); 1487 } 1488 1489 crypto_header = ((FCS_CS_FIELD_FLAG_INIT | FCS_CS_FIELD_FLAG_FINALIZE) << 1490 FCS_CS_FIELD_FLAG_OFFSET); 1491 fcs_rng_payload payload = {session_id, context_id, 1492 crypto_header, random_len}; 1493 1494 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1495 GET_JOB_ID(x1), 1496 MBOX_FCS_RANDOM_GEN, 1497 (uint32_t *)&payload, 1498 sizeof(payload) / MBOX_WORD_BYTE, 1499 MBOX_CMD_FLAG_CASUAL, 1500 sip_smc_ret_nbytes_cb, 1501 (uint32_t *)ret_random_addr, 1502 2); 1503 SMC_RET1(handle, status); 1504 } 1505 1506 case ALTERA_SIP_SMC_ASYNC_FCS_GET_PROVISION_DATA: 1507 { 1508 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1509 GET_JOB_ID(x1), 1510 MBOX_FCS_GET_PROVISION, 1511 NULL, 1512 0U, 1513 MBOX_CMD_FLAG_CASUAL, 1514 sip_smc_ret_nbytes_cb, 1515 (uint32_t *)x2, 1516 2); 1517 SMC_RET1(handle, status); 1518 } 1519 1520 case ALTERA_SIP_SMC_ASYNC_FCS_CNTR_SET_PREAUTH: 1521 { 1522 status = intel_fcs_cntr_set_preauth(smc_fid, x1, x2, x3, 1523 x4, &mbox_error); 1524 SMC_RET1(handle, status); 1525 } 1526 1527 case ALTERA_SIP_SMC_ASYNC_FCS_CHIP_ID: 1528 { 1529 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1530 GET_JOB_ID(x1), 1531 MBOX_CMD_GET_CHIPID, 1532 NULL, 1533 0U, 1534 MBOX_CMD_FLAG_CASUAL, 1535 sip_smc_get_chipid_cb, 1536 NULL, 1537 0); 1538 SMC_RET1(handle, status); 1539 } 1540 1541 case ALTERA_SIP_SMC_ASYNC_FCS_GET_ATTESTATION_CERT: 1542 { 1543 status = intel_fcs_get_attestation_cert(smc_fid, x1, x2, x3, 1544 (uint32_t *) &x4, &mbox_error); 1545 SMC_RET1(handle, status); 1546 } 1547 1548 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CERT_ON_RELOAD: 1549 { 1550 status = intel_fcs_create_cert_on_reload(smc_fid, x1, 1551 x2, &mbox_error); 1552 SMC_RET1(handle, status); 1553 } 1554 1555 case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT: 1556 { 1557 if (x4 == FCS_MODE_ENCRYPT) { 1558 status = intel_fcs_encryption_ext(smc_fid, x1, x2, x3, 1559 x5, x6, x7, (uint32_t *) &x8, 1560 &mbox_error, x10, x11); 1561 } else if (x4 == FCS_MODE_DECRYPT) { 1562 status = intel_fcs_decryption_ext(smc_fid, x1, x2, x3, 1563 x5, x6, x7, (uint32_t *) &x8, 1564 &mbox_error, x9, x10, x11); 1565 } else { 1566 ERROR("MBOX: 0x%x: Wrong crypto mode\n", smc_fid); 1567 status = INTEL_SIP_SMC_STATUS_REJECTED; 1568 } 1569 SMC_RET1(handle, status); 1570 } 1571 1572 case ALTERA_SIP_SMC_ASYNC_FCS_SEND_CERTIFICATE: 1573 { 1574 status = intel_fcs_send_cert(smc_fid, x1, x2, x3, &mbox_error); 1575 SMC_RET1(handle, status); 1576 } 1577 1578 case ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION: 1579 { 1580 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1581 GET_JOB_ID(x1), 1582 MBOX_FCS_OPEN_CS_SESSION, 1583 NULL, 1584 0U, 1585 MBOX_CMD_FLAG_CASUAL, 1586 sip_smc_cmd_cb_ret3, 1587 NULL, 1588 0); 1589 SMC_RET1(handle, status); 1590 } 1591 1592 case ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION: 1593 { 1594 uint32_t session_id = (uint32_t)x2; 1595 1596 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1597 GET_JOB_ID(x1), 1598 MBOX_FCS_CLOSE_CS_SESSION, 1599 &session_id, 1600 1U, 1601 MBOX_CMD_FLAG_CASUAL, 1602 sip_smc_cmd_cb_ret2, 1603 NULL, 1604 0); 1605 SMC_RET1(handle, status); 1606 } 1607 1608 case ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY: 1609 { 1610 uint64_t key_addr = x2; 1611 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE; 1612 1613 if ((key_len_words > FCS_CS_KEY_OBJ_MAX_WORD_SIZE) || 1614 (!is_address_in_ddr_range(key_addr, key_len_words * 4))) { 1615 ERROR("MBOX: 0x%x: Addr not in DDR range or key len exceeds\n", 1616 smc_fid); 1617 status = INTEL_SIP_SMC_STATUS_REJECTED; 1618 SMC_RET1(handle, status); 1619 } 1620 1621 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1622 GET_JOB_ID(x1), 1623 MBOX_FCS_IMPORT_CS_KEY, 1624 (uint32_t *)key_addr, 1625 key_len_words, 1626 MBOX_CMD_FLAG_CASUAL, 1627 sip_smc_cmd_cb_ret3, 1628 NULL, 1629 0); 1630 SMC_RET1(handle, status); 1631 } 1632 1633 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY: 1634 { 1635 uint64_t key_addr = x2; 1636 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE; 1637 1638 if (!is_address_in_ddr_range(key_addr, key_len_words * 4)) { 1639 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1640 status = INTEL_SIP_SMC_STATUS_REJECTED; 1641 SMC_RET1(handle, status); 1642 } 1643 1644 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1645 GET_JOB_ID(x1), 1646 MBOX_FCS_CREATE_CS_KEY, 1647 (uint32_t *)key_addr, 1648 key_len_words, 1649 MBOX_CMD_FLAG_CASUAL, 1650 sip_smc_cmd_cb_ret3, 1651 NULL, 1652 0); 1653 SMC_RET1(handle, status); 1654 } 1655 1656 case ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY: 1657 { 1658 uint32_t session_id = (uint32_t)x2; 1659 uint32_t key_uid = (uint32_t)x3; 1660 uint64_t ret_key_addr = (uint64_t)x4; 1661 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1662 1663 if (!is_address_in_ddr_range(ret_key_addr, key_len)) { 1664 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1665 status = INTEL_SIP_SMC_STATUS_REJECTED; 1666 SMC_RET1(handle, status); 1667 } 1668 1669 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1670 RESERVED_AS_ZERO, key_uid}; 1671 1672 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1673 GET_JOB_ID(x1), 1674 MBOX_FCS_EXPORT_CS_KEY, 1675 (uint32_t *)&payload, 1676 sizeof(payload) / MBOX_WORD_BYTE, 1677 MBOX_CMD_FLAG_CASUAL, 1678 sip_smc_ret_nbytes_cb, 1679 (uint32_t *)ret_key_addr, 1680 2); 1681 SMC_RET1(handle, status); 1682 } 1683 1684 case ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY: 1685 { 1686 uint32_t session_id = (uint32_t)x2; 1687 uint32_t key_uid = (uint32_t)x3; 1688 1689 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1690 RESERVED_AS_ZERO, key_uid}; 1691 1692 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1693 GET_JOB_ID(x1), 1694 MBOX_FCS_REMOVE_CS_KEY, 1695 (uint32_t *)&payload, 1696 sizeof(payload) / MBOX_WORD_BYTE, 1697 MBOX_CMD_FLAG_CASUAL, 1698 sip_smc_cmd_cb_ret3, 1699 NULL, 1700 0); 1701 SMC_RET1(handle, status); 1702 } 1703 1704 case ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO: 1705 { 1706 uint32_t session_id = (uint32_t)x2; 1707 uint32_t key_uid = (uint32_t)x3; 1708 uint64_t ret_key_addr = (uint64_t)x4; 1709 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1710 1711 if (!is_address_in_ddr_range(ret_key_addr, key_len)) { 1712 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1713 status = INTEL_SIP_SMC_STATUS_REJECTED; 1714 SMC_RET1(handle, status); 1715 } 1716 1717 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1718 RESERVED_AS_ZERO, key_uid}; 1719 1720 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1721 GET_JOB_ID(x1), 1722 MBOX_FCS_GET_CS_KEY_INFO, 1723 (uint32_t *)&payload, 1724 sizeof(payload) / MBOX_WORD_BYTE, 1725 MBOX_CMD_FLAG_CASUAL, 1726 sip_smc_ret_nbytes_cb, 1727 (uint32_t *)ret_key_addr, 1728 2); 1729 SMC_RET1(handle, status); 1730 } 1731 1732 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_INIT: 1733 { 1734 status = intel_fcs_aes_crypt_init(x2, x3, x4, x5, 1735 x6, &mbox_error); 1736 SMC_RET1(handle, status); 1737 } 1738 1739 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_UPDATE: 1740 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE: 1741 { 1742 uint32_t job_id = 0U; 1743 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE) ? 1744 true : false; 1745 1746 status = intel_fcs_aes_crypt_update_finalize(smc_fid, x1, x2, 1747 x3, x4, x5, x6, x7, x8, is_final, 1748 &job_id, x9, x10); 1749 SMC_RET1(handle, status); 1750 } 1751 1752 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT: 1753 { 1754 status = intel_fcs_get_digest_init(x2, x3, x4, x5, x6, 1755 &mbox_error); 1756 SMC_RET1(handle, status); 1757 } 1758 1759 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE: 1760 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE: 1761 { 1762 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE) ? 1763 true : false; 1764 1765 status = intel_fcs_get_digest_update_finalize(smc_fid, x1, x2, 1766 x3, x4, x5, x6, (uint32_t *) &x7, 1767 is_final, &mbox_error, x8); 1768 1769 SMC_RET1(handle, status); 1770 } 1771 1772 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT: 1773 { 1774 status = intel_fcs_mac_verify_init(x2, x3, x4, x5, x6, 1775 &mbox_error); 1776 SMC_RET1(handle, status); 1777 } 1778 1779 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE: 1780 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE: 1781 { 1782 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE) ? 1783 true : false; 1784 1785 status = intel_fcs_mac_verify_update_finalize(smc_fid, x1, x2, 1786 x3, x4, x5, x6, (uint32_t *) &x7, x8, 1787 is_final, &mbox_error, x9); 1788 SMC_RET1(handle, status); 1789 } 1790 1791 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT: 1792 { 1793 status = intel_fcs_ecdsa_hash_sign_init(x2, x3, x4, x5, x6, 1794 &mbox_error); 1795 SMC_RET1(handle, status); 1796 } 1797 1798 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1799 { 1800 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, x1, x2, x3, 1801 x4, x5, x6, (uint32_t *) &x7, 1802 &mbox_error); 1803 SMC_RET1(handle, status); 1804 } 1805 1806 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1807 { 1808 status = intel_fcs_ecdsa_sha2_data_sign_init(x2, x3, x4, x5, x6, 1809 &mbox_error); 1810 SMC_RET1(handle, status); 1811 } 1812 1813 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1814 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1815 { 1816 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE) 1817 ? true : false; 1818 1819 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 1820 x1, x2, x3, x4, x5, x6, (uint32_t *) &x7, 1821 is_final, &mbox_error, x8); 1822 SMC_RET1(handle, status); 1823 } 1824 1825 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1826 { 1827 status = intel_fcs_ecdsa_hash_sig_verify_init(x2, x3, x4, x5, 1828 x6, &mbox_error); 1829 SMC_RET1(handle, status); 1830 } 1831 1832 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1833 { 1834 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, x1, 1835 x2, x3, x4, x5, x6, (uint32_t *) &x7, 1836 &mbox_error); 1837 SMC_RET1(handle, status); 1838 } 1839 1840 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1841 { 1842 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x2, x3, x4, 1843 x5, x6, &mbox_error); 1844 SMC_RET1(handle, status); 1845 } 1846 1847 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1848 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1849 { 1850 bool is_final = (smc_fid == 1851 ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE) ? 1852 true : false; 1853 1854 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1855 smc_fid, x1, x2, x3, x4, x5, x6, 1856 (uint32_t *) &x7, x8, is_final, 1857 &mbox_error, x9); 1858 SMC_RET1(handle, status); 1859 } 1860 1861 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT: 1862 { 1863 status = intel_fcs_ecdsa_get_pubkey_init(x2, x3, x4, x5, x6, 1864 &mbox_error); 1865 SMC_RET1(handle, status); 1866 } 1867 1868 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1869 { 1870 status = intel_fcs_ecdsa_get_pubkey_finalize(smc_fid, x1, x2, x3, 1871 x4, (uint32_t *) &x5, &mbox_error); 1872 SMC_RET1(handle, status); 1873 } 1874 1875 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT: 1876 { 1877 status = intel_fcs_ecdh_request_init(x2, x3, x4, x5, x6, 1878 &mbox_error); 1879 SMC_RET1(handle, status); 1880 } 1881 1882 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE: 1883 { 1884 uint32_t dest_size = (uint32_t)x7; 1885 1886 NOTICE("MBOX: %s, %d: x7 0x%x, dest_size 0x%x\n", 1887 __func__, __LINE__, (uint32_t)x7, dest_size); 1888 1889 status = intel_fcs_ecdh_request_finalize(smc_fid, x1, x2, x3, 1890 x4, x5, x6, (uint32_t *) &dest_size, 1891 &mbox_error); 1892 SMC_RET1(handle, status); 1893 } 1894 1895 case ALTERA_SIP_SMC_ASYNC_MCTP_MSG: 1896 { 1897 uint32_t *src_addr = (uint32_t *)x2; 1898 uint32_t src_size = (uint32_t)x3; 1899 uint32_t *dst_addr = (uint32_t *)x4; 1900 1901 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1902 GET_JOB_ID(x1), 1903 MBOX_CMD_MCTP_MSG, 1904 src_addr, 1905 src_size / MBOX_WORD_BYTE, 1906 MBOX_CMD_FLAG_CASUAL, 1907 sip_smc_ret_nbytes_cb, 1908 dst_addr, 1909 2); 1910 1911 SMC_RET1(handle, status); 1912 } 1913 1914 case ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST: 1915 { 1916 status = intel_fcs_hkdf_request(smc_fid, x1, x2, x3, x4, x5, x6, 1917 x7); 1918 SMC_RET1(handle, status); 1919 } 1920 1921 default: 1922 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1923 cookie, handle, flags); 1924 } /* switch (smc_fid) */ 1925 } 1926 #endif 1927 1928 /* 1929 * This function is responsible for handling all SiP calls from the NS world 1930 */ 1931 1932 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 1933 u_register_t x1, 1934 u_register_t x2, 1935 u_register_t x3, 1936 u_register_t x4, 1937 void *cookie, 1938 void *handle, 1939 u_register_t flags) 1940 { 1941 uint32_t retval = 0, completed_addr[3]; 1942 uint32_t retval2 = 0; 1943 uint32_t mbox_error = 0; 1944 uint32_t err_states = 0; 1945 uint64_t retval64, rsu_respbuf[9]; 1946 uint32_t seu_respbuf[3]; 1947 int status = INTEL_SIP_SMC_STATUS_OK; 1948 int mbox_status; 1949 unsigned int len_in_resp = 0; 1950 u_register_t x5, x6, x7; 1951 1952 switch (smc_fid) { 1953 case SIP_SVC_UID: 1954 /* Return UID to the caller */ 1955 SMC_UUID_RET(handle, intl_svc_uid); 1956 1957 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 1958 status = intel_mailbox_fpga_config_isdone(&err_states); 1959 SMC_RET4(handle, status, err_states, 0, 0); 1960 1961 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 1962 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1963 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 1964 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 1965 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 1966 1967 case INTEL_SIP_SMC_FPGA_CONFIG_START: 1968 status = intel_fpga_config_start(x1); 1969 SMC_RET4(handle, status, 0, 0, 0); 1970 1971 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 1972 status = intel_fpga_config_write(x1, x2); 1973 SMC_RET4(handle, status, 0, 0, 0); 1974 1975 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 1976 status = intel_fpga_config_completed_write(completed_addr, 1977 &retval, &rcv_id); 1978 switch (retval) { 1979 case 1: 1980 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1981 completed_addr[0], 0, 0); 1982 1983 case 2: 1984 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1985 completed_addr[0], 1986 completed_addr[1], 0); 1987 1988 case 3: 1989 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1990 completed_addr[0], 1991 completed_addr[1], 1992 completed_addr[2]); 1993 1994 case 0: 1995 SMC_RET4(handle, status, 0, 0, 0); 1996 1997 default: 1998 mailbox_clear_response(); 1999 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 2000 } 2001 2002 case INTEL_SIP_SMC_REG_READ: 2003 status = intel_secure_reg_read(x1, &retval); 2004 SMC_RET3(handle, status, retval, x1); 2005 2006 case INTEL_SIP_SMC_REG_WRITE: 2007 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 2008 SMC_RET3(handle, status, retval, x1); 2009 2010 case INTEL_SIP_SMC_REG_UPDATE: 2011 status = intel_secure_reg_update(x1, (uint32_t)x2, 2012 (uint32_t)x3, &retval); 2013 SMC_RET3(handle, status, retval, x1); 2014 2015 case INTEL_SIP_SMC_RSU_STATUS: 2016 status = intel_rsu_status(rsu_respbuf, 2017 ARRAY_SIZE(rsu_respbuf)); 2018 if (status) { 2019 SMC_RET1(handle, status); 2020 } else { 2021 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 2022 rsu_respbuf[2], rsu_respbuf[3]); 2023 } 2024 2025 case INTEL_SIP_SMC_RSU_UPDATE: 2026 status = intel_rsu_update(x1); 2027 SMC_RET1(handle, status); 2028 2029 case INTEL_SIP_SMC_RSU_NOTIFY: 2030 status = intel_rsu_notify(x1); 2031 SMC_RET1(handle, status); 2032 2033 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 2034 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 2035 ARRAY_SIZE(rsu_respbuf), &retval); 2036 if (status) { 2037 SMC_RET1(handle, status); 2038 } else { 2039 SMC_RET2(handle, status, retval); 2040 } 2041 2042 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 2043 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 2044 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 2045 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 2046 2047 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 2048 status = intel_rsu_copy_dcmf_version(x1, x2); 2049 SMC_RET1(handle, status); 2050 2051 case INTEL_SIP_SMC_RSU_GET_DEVICE_INFO: 2052 status = intel_rsu_get_device_info((uint32_t *)rsu_respbuf, 2053 ARRAY_SIZE(rsu_respbuf)); 2054 if (status) { 2055 SMC_RET1(handle, status); 2056 } else { 2057 SMC_RET5(handle, status, rsu_respbuf[0], rsu_respbuf[1], 2058 rsu_respbuf[2], rsu_respbuf[3]); 2059 } 2060 2061 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 2062 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 2063 ((uint64_t)rsu_dcmf_stat[3] << 48) | 2064 ((uint64_t)rsu_dcmf_stat[2] << 32) | 2065 ((uint64_t)rsu_dcmf_stat[1] << 16) | 2066 rsu_dcmf_stat[0]); 2067 2068 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 2069 status = intel_rsu_copy_dcmf_status(x1); 2070 SMC_RET1(handle, status); 2071 2072 case INTEL_SIP_SMC_RSU_MAX_RETRY: 2073 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 2074 2075 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 2076 rsu_max_retry = x1; 2077 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 2078 2079 case INTEL_SIP_SMC_ECC_DBE: 2080 status = intel_ecc_dbe_notification(x1); 2081 SMC_RET1(handle, status); 2082 2083 case INTEL_SIP_SMC_SERVICE_COMPLETED: 2084 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 2085 &len_in_resp, &mbox_error); 2086 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 2087 2088 case INTEL_SIP_SMC_FIRMWARE_VERSION: 2089 status = intel_smc_fw_version(&retval); 2090 SMC_RET2(handle, status, retval); 2091 2092 case INTEL_SIP_SMC_MBOX_SEND_CMD: 2093 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2094 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2095 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 2096 &mbox_status, &len_in_resp); 2097 SMC_RET3(handle, status, mbox_status, len_in_resp); 2098 2099 case INTEL_SIP_SMC_GET_USERCODE: 2100 status = intel_smc_get_usercode(&retval); 2101 SMC_RET2(handle, status, retval); 2102 2103 case INTEL_SIP_SMC_FCS_CRYPTION: 2104 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2105 2106 if (x1 == FCS_MODE_DECRYPT) { 2107 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 2108 } else if (x1 == FCS_MODE_ENCRYPT) { 2109 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 2110 } else { 2111 status = INTEL_SIP_SMC_STATUS_REJECTED; 2112 } 2113 2114 SMC_RET3(handle, status, x4, x5); 2115 2116 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 2117 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2118 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2119 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2120 2121 if (x3 == FCS_MODE_DECRYPT) { 2122 status = intel_fcs_decryption_ext(smc_fid, 0, x1, x2, x4, x5, x6, 2123 (uint32_t *) &x7, &mbox_error, 0, 0, 0); 2124 } else if (x3 == FCS_MODE_ENCRYPT) { 2125 status = intel_fcs_encryption_ext(smc_fid, 0, x1, x2, x4, x5, x6, 2126 (uint32_t *) &x7, &mbox_error, 0, 0); 2127 } else { 2128 status = INTEL_SIP_SMC_STATUS_REJECTED; 2129 } 2130 2131 SMC_RET4(handle, status, mbox_error, x6, x7); 2132 2133 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 2134 status = intel_fcs_random_number_gen(x1, &retval64, 2135 &mbox_error); 2136 SMC_RET4(handle, status, mbox_error, x1, retval64); 2137 2138 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 2139 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 2140 &send_id); 2141 SMC_RET1(handle, status); 2142 2143 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 2144 status = intel_fcs_send_cert(smc_fid, 0, x1, x2, &send_id); 2145 SMC_RET1(handle, status); 2146 2147 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 2148 status = intel_fcs_get_provision_data(&send_id); 2149 SMC_RET1(handle, status); 2150 2151 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 2152 status = intel_fcs_cntr_set_preauth(smc_fid, 0, x1, x2, x3, 2153 &mbox_error); 2154 SMC_RET2(handle, status, mbox_error); 2155 2156 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 2157 status = intel_hps_set_bridges(x1, x2); 2158 SMC_RET1(handle, status); 2159 2160 case INTEL_SIP_SMC_HWMON_READTEMP: 2161 status = intel_hwmon_readtemp(x1, &retval); 2162 SMC_RET2(handle, status, retval); 2163 2164 case INTEL_SIP_SMC_HWMON_READVOLT: 2165 status = intel_hwmon_readvolt(x1, &retval); 2166 SMC_RET2(handle, status, retval); 2167 2168 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 2169 status = intel_fcs_sigma_teardown(x1, &mbox_error); 2170 SMC_RET2(handle, status, mbox_error); 2171 2172 case INTEL_SIP_SMC_FCS_CHIP_ID: 2173 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 2174 SMC_RET4(handle, status, mbox_error, retval, retval2); 2175 2176 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 2177 status = intel_fcs_attestation_subkey(x1, x2, x3, 2178 (uint32_t *) &x4, &mbox_error); 2179 SMC_RET4(handle, status, mbox_error, x3, x4); 2180 2181 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 2182 status = intel_fcs_get_measurement(x1, x2, x3, 2183 (uint32_t *) &x4, &mbox_error); 2184 SMC_RET4(handle, status, mbox_error, x3, x4); 2185 2186 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 2187 status = intel_fcs_get_attestation_cert(smc_fid, 0, x1, x2, 2188 (uint32_t *) &x3, &mbox_error); 2189 SMC_RET4(handle, status, mbox_error, x2, x3); 2190 2191 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 2192 status = intel_fcs_create_cert_on_reload(smc_fid, 0, x1, &mbox_error); 2193 SMC_RET2(handle, status, mbox_error); 2194 2195 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 2196 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 2197 SMC_RET3(handle, status, mbox_error, retval); 2198 2199 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 2200 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 2201 SMC_RET2(handle, status, mbox_error); 2202 2203 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 2204 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 2205 SMC_RET1(handle, status); 2206 2207 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 2208 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 2209 (uint32_t *) &x4, &mbox_error); 2210 SMC_RET4(handle, status, mbox_error, x3, x4); 2211 2212 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 2213 status = intel_fcs_remove_crypto_service_key(x1, x2, 2214 &mbox_error); 2215 SMC_RET2(handle, status, mbox_error); 2216 2217 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 2218 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 2219 (uint32_t *) &x4, &mbox_error); 2220 SMC_RET4(handle, status, mbox_error, x3, x4); 2221 2222 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 2223 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2224 status = intel_fcs_get_digest_init(x1, x2, x3, 2225 x4, x5, &mbox_error); 2226 SMC_RET2(handle, status, mbox_error); 2227 2228 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 2229 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2230 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2231 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2, 2232 x3, x4, x5, (uint32_t *) &x6, false, 2233 &mbox_error, 0); 2234 SMC_RET4(handle, status, mbox_error, x5, x6); 2235 2236 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 2237 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2238 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2239 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2, 2240 x3, x4, x5, (uint32_t *) &x6, true, 2241 &mbox_error, 0); 2242 SMC_RET4(handle, status, mbox_error, x5, x6); 2243 2244 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 2245 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2246 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2247 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 2248 x4, x5, (uint32_t *) &x6, false, 2249 &mbox_error, &send_id); 2250 SMC_RET4(handle, status, mbox_error, x5, x6); 2251 2252 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 2253 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2254 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2255 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 2256 x4, x5, (uint32_t *) &x6, true, 2257 &mbox_error, &send_id); 2258 SMC_RET4(handle, status, mbox_error, x5, x6); 2259 2260 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 2261 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2262 status = intel_fcs_mac_verify_init(x1, x2, x3, 2263 x4, x5, &mbox_error); 2264 SMC_RET2(handle, status, mbox_error); 2265 2266 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 2267 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2268 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2269 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2270 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2, 2271 x3, x4, x5, (uint32_t *) &x6, x7, false, 2272 &mbox_error, 0); 2273 SMC_RET4(handle, status, mbox_error, x5, x6); 2274 2275 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 2276 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2277 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2278 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2279 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2, 2280 x3, x4, x5, (uint32_t *) &x6, x7, true, 2281 &mbox_error, 0); 2282 SMC_RET4(handle, status, mbox_error, x5, x6); 2283 2284 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 2285 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2286 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2287 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2288 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 2289 x4, x5, (uint32_t *) &x6, x7, 2290 false, &mbox_error, &send_id); 2291 SMC_RET4(handle, status, mbox_error, x5, x6); 2292 2293 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 2294 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2295 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2296 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2297 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 2298 x4, x5, (uint32_t *) &x6, x7, 2299 true, &mbox_error, &send_id); 2300 SMC_RET4(handle, status, mbox_error, x5, x6); 2301 2302 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 2303 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2304 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 2305 x4, x5, &mbox_error); 2306 SMC_RET2(handle, status, mbox_error); 2307 2308 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 2309 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2310 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2311 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 2312 0, x1, x2, x3, x4, x5, (uint32_t *) &x6, 2313 false, &mbox_error, 0); 2314 SMC_RET4(handle, status, mbox_error, x5, x6); 2315 2316 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 2317 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2318 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2319 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 2320 0, x1, x2, x3, x4, x5, (uint32_t *) &x6, 2321 true, &mbox_error, 0); 2322 SMC_RET4(handle, status, mbox_error, x5, x6); 2323 2324 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 2325 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2326 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2327 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 2328 x2, x3, x4, x5, (uint32_t *) &x6, false, 2329 &mbox_error, &send_id); 2330 SMC_RET4(handle, status, mbox_error, x5, x6); 2331 2332 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 2333 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2334 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2335 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 2336 x2, x3, x4, x5, (uint32_t *) &x6, true, 2337 &mbox_error, &send_id); 2338 SMC_RET4(handle, status, mbox_error, x5, x6); 2339 2340 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 2341 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2342 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 2343 x4, x5, &mbox_error); 2344 SMC_RET2(handle, status, mbox_error); 2345 2346 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 2347 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2348 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2349 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, 0, x1, x2, 2350 x3, x4, x5, (uint32_t *) &x6, 2351 &mbox_error); 2352 SMC_RET4(handle, status, mbox_error, x5, x6); 2353 2354 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 2355 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2356 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 2357 x4, x5, &mbox_error); 2358 SMC_RET2(handle, status, mbox_error); 2359 2360 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 2361 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2362 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2363 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, 0, x1, 2364 x2, x3, x4, x5, (uint32_t *) &x6, 2365 &mbox_error); 2366 SMC_RET4(handle, status, mbox_error, x5, x6); 2367 2368 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 2369 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2370 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 2371 x4, x5, &mbox_error); 2372 SMC_RET2(handle, status, mbox_error); 2373 2374 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 2375 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2376 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2377 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2378 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 2379 smc_fid, 0, x1, x2, x3, x4, x5, 2380 (uint32_t *) &x6, x7, false, 2381 &mbox_error, 0); 2382 SMC_RET4(handle, status, mbox_error, x5, x6); 2383 2384 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 2385 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2386 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2387 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2388 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 2389 x1, x2, x3, x4, x5, (uint32_t *) &x6, 2390 x7, false, &mbox_error, &send_id); 2391 SMC_RET4(handle, status, mbox_error, x5, x6); 2392 2393 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 2394 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2395 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2396 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2397 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 2398 x1, x2, x3, x4, x5, (uint32_t *) &x6, 2399 x7, true, &mbox_error, &send_id); 2400 SMC_RET4(handle, status, mbox_error, x5, x6); 2401 2402 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 2403 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2404 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2405 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2406 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 2407 smc_fid, 0, x1, x2, x3, x4, x5, 2408 (uint32_t *) &x6, x7, true, 2409 &mbox_error, 0); 2410 SMC_RET4(handle, status, mbox_error, x5, x6); 2411 2412 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 2413 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2414 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 2415 x4, x5, &mbox_error); 2416 SMC_RET2(handle, status, mbox_error); 2417 2418 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 2419 status = intel_fcs_ecdsa_get_pubkey_finalize( 2420 INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE, 0, 2421 x1, x2, x3, (uint32_t *) &x4, &mbox_error); 2422 SMC_RET4(handle, status, mbox_error, x3, x4); 2423 2424 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 2425 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2426 status = intel_fcs_ecdh_request_init(x1, x2, x3, 2427 x4, x5, &mbox_error); 2428 SMC_RET2(handle, status, mbox_error); 2429 2430 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 2431 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2432 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2433 status = intel_fcs_ecdh_request_finalize(smc_fid, 0, x1, x2, x3, 2434 x4, x5, (uint32_t *) &x6, &mbox_error); 2435 SMC_RET4(handle, status, mbox_error, x5, x6); 2436 2437 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 2438 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2439 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 2440 &mbox_error); 2441 SMC_RET2(handle, status, mbox_error); 2442 2443 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 2444 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2445 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2446 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2, 2447 x3, x4, x5, x6, 0, false, &send_id, 0, 0); 2448 SMC_RET1(handle, status); 2449 2450 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 2451 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2452 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2453 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2, 2454 x3, x4, x5, x6, 0, true, &send_id, 0, 0); 2455 SMC_RET1(handle, status); 2456 2457 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 2458 case INTEL_SIP_SMC_FCS_SDM_REMAPPER_CONFIG: 2459 status = intel_smmu_hps_remapper_config(x1); 2460 SMC_RET1(handle, status); 2461 #endif 2462 2463 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 2464 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 2465 &mbox_error); 2466 SMC_RET4(handle, status, mbox_error, x1, retval64); 2467 2468 case INTEL_SIP_SMC_SVC_VERSION: 2469 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 2470 SIP_SVC_VERSION_MAJOR, 2471 SIP_SVC_VERSION_MINOR); 2472 2473 case INTEL_SIP_SMC_SEU_ERR_STATUS: 2474 status = intel_sdm_seu_err_read(seu_respbuf, 2475 ARRAY_SIZE(seu_respbuf)); 2476 if (status) { 2477 SMC_RET1(handle, status); 2478 } else { 2479 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); 2480 } 2481 2482 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR: 2483 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2); 2484 SMC_RET1(handle, status); 2485 2486 case INTEL_SIP_SMC_ATF_BUILD_VER: 2487 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, VERSION_MAJOR, 2488 VERSION_MINOR, VERSION_PATCH); 2489 2490 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 2491 case INTEL_SIP_SMC_INJECT_IO96B_ECC_ERR: 2492 intel_inject_io96b_ecc_err((uint32_t *)&x1, (uint32_t)x2); 2493 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 2494 #endif 2495 2496 default: 2497 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 2498 cookie, handle, flags); 2499 } 2500 } 2501 2502 uintptr_t sip_smc_handler(uint32_t smc_fid, 2503 u_register_t x1, 2504 u_register_t x2, 2505 u_register_t x3, 2506 u_register_t x4, 2507 void *cookie, 2508 void *handle, 2509 u_register_t flags) 2510 { 2511 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 2512 2513 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 2514 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 2515 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 2516 cookie, handle, flags); 2517 } 2518 #if SIP_SVC_V3 2519 else if ((cmd >= INTEL_SIP_SMC_CMD_V3_RANGE_BEGIN) && 2520 (cmd <= INTEL_SIP_SMC_CMD_V3_RANGE_END)) { 2521 uintptr_t ret = sip_smc_handler_v3(smc_fid, x1, x2, x3, x4, 2522 cookie, handle, flags); 2523 return ret; 2524 } 2525 #endif 2526 else { 2527 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 2528 cookie, handle, flags); 2529 } 2530 } 2531 2532 DECLARE_RT_SVC( 2533 socfpga_sip_svc, 2534 OEN_SIP_START, 2535 OEN_SIP_END, 2536 SMC_TYPE_FAST, 2537 NULL, 2538 sip_smc_handler 2539 ); 2540 2541 DECLARE_RT_SVC( 2542 socfpga_sip_svc_std, 2543 OEN_SIP_START, 2544 OEN_SIP_END, 2545 SMC_TYPE_YIELD, 2546 NULL, 2547 sip_smc_handler 2548 ); 2549