1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. External 27 memory-mapped debug accesses are unaffected by this control. 28 The default value is 1 for all platforms. 29 30- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 31 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 32 ``aarch64``. 33 34- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 35 one or more feature modifiers. This option has the form ``[no]feature+...`` 36 and defaults to ``none``. It translates into compiler option 37 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 38 list of supported feature modifiers. 39 40- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 41 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 42 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 43 :ref:`Firmware Design`. 44 45- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 46 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 47 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 48 49- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded 50 SP nodes in tb_fw_config. 51 52- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the 53 SPMC Core manifest. Valid when ``SPD=spmd`` is selected. 54 55- ``BL2``: This is an optional build option which specifies the path to BL2 56 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 57 built. 58 59- ``BL2U``: This is an optional build option which specifies the path to 60 BL2U image. In this case, the BL2U in TF-A will not be built. 61 62- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 63 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 64 entrypoint) or 1 (CPU reset to BL2 entrypoint). 65 The default value is 0. 66 67- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 68 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 69 true in a 4-world system where RESET_TO_BL2 is 0. 70 71- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 72 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 73 74- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 75 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 76 the RW sections in RAM, while leaving the RO sections in place. This option 77 enable this use-case. For now, this option is only supported 78 when RESET_TO_BL2 is set to '1'. 79 80- ``BL31``: This is an optional build option which specifies the path to 81 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 82 be built. 83 84- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 85 file that contains the BL31 private key in PEM format or a PKCS11 URI. If 86 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 87 88- ``BL32``: This is an optional build option which specifies the path to 89 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 90 be built. 91 92- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 93 Trusted OS Extra1 image for the ``fip`` target. 94 95- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 96 Trusted OS Extra2 image for the ``fip`` target. 97 98- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 99 file that contains the BL32 private key in PEM format or a PKCS11 URI. If 100 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 101 102- ``RMM``: This is an optional build option used when ``ENABLE_RME`` is set. 103 It specifies the path to RMM binary for the ``fip`` target. If the RMM option 104 is not specified, TF-A builds the TRP to load and run at R-EL2. 105 106- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 107 ``fip`` target in case TF-A BL2 is used. 108 109- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 110 file that contains the BL33 private key in PEM format or a PKCS11 URI. If 111 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 112 113- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 114 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 115 If enabled, it is needed to use a compiler that supports the option 116 ``-mbranch-protection``. The value of the ``-march`` (via ``ARM_ARCH_MINOR`` 117 and ``ARM_ARCH_MAJOR``) option will control which instructions will be 118 emitted (HINT space or not). Selects the branch protection features to use: 119- 0: Default value turns off all types of branch protection (FEAT_STATE_DISABLED) 120- 1: Enables all types of branch protection features 121- 2: Return address signing to its standard level 122- 3: Extend the signing to include leaf functions 123- 4: Turn on branch target identification mechanism 124- 5: Enables all types of branch protection features, only if present in 125 hardware (FEAT_STATE_CHECK). 126 127 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 128 and resulting PAuth/BTI features. 129 130 +-------+--------------+-------+-----+ 131 | Value | GCC option | PAuth | BTI | 132 +=======+==============+=======+=====+ 133 | 0 | none | N | N | 134 +-------+--------------+-------+-----+ 135 | 1 | standard | Y | Y | 136 +-------+--------------+-------+-----+ 137 | 2 | pac-ret | Y | N | 138 +-------+--------------+-------+-----+ 139 | 3 | pac-ret+leaf | Y | N | 140 +-------+--------------+-------+-----+ 141 | 4 | bti | N | Y | 142 +-------+--------------+-------+-----+ 143 | 5 | dynamic | Y | Y | 144 +-------+--------------+-------+-----+ 145 146 This option defaults to 0. 147 Note that Pointer Authentication is enabled for Non-secure world 148 irrespective of the value of this option if the CPU supports it. 149 150- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 151 compilation of each build. It must be set to a C string (including quotes 152 where applicable). Defaults to a string that contains the time and date of 153 the compilation. 154 155- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 156 build to be uniquely identified. Defaults to the current git commit id. 157 158- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 159 160- ``CFLAGS``: Extra user options appended on the compiler's command line in 161 addition to the options set by the build system. 162 163- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 164 release several CPUs out of reset. It can take either 0 (several CPUs may be 165 brought up) or 1 (only one CPU will ever be brought up during cold reset). 166 Default is 0. If the platform always brings up a single CPU, there is no 167 need to distinguish between primary and secondary CPUs and the boot path can 168 be optimised. The ``plat_is_my_cpu_primary()`` and 169 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 170 to be implemented in this case. 171 172- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 173 Defaults to ``tbbr``. 174 175- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 176 register state when an unexpected exception occurs during execution of 177 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 178 this is only enabled for a debug build of the firmware. 179 180- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 181 certificate generation tool to create new keys in case no valid keys are 182 present or specified. Allowed options are '0' or '1'. Default is '1'. 183 184- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 185 the AArch32 system registers to be included when saving and restoring the 186 CPU context. The option must be set to 0 for AArch64-only platforms (that 187 is on hardware that does not implement AArch32, or at least not at EL1 and 188 higher ELs). Default value is 1. 189 190- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 191 registers to be included when saving and restoring the CPU context. Default 192 is 0. 193 194- ``CTX_INCLUDE_MPAM_REGS``: Boolean option that, when set to 1, will cause the 195 Memory System Resource Partitioning and Monitoring (MPAM) 196 registers to be included when saving and restoring the CPU context. 197 Default is '0'. 198 199- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 200 registers to be saved/restored when entering/exiting an EL2 execution 201 context. This flag can take values 0 to 2, to align with the 202 ``ENABLE_FEAT`` mechanism. Default value is 0. 203 204- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 205 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 206 to be included when saving and restoring the CPU context as part of world 207 switch. Automatically enabled when ``BRANCH_PROTECTION`` is enabled. This flag 208 can take values 0 to 2, to align with ``ENABLE_FEAT`` mechanism. Default value 209 is 0. 210 211 Note that Pointer Authentication is enabled for Non-secure world irrespective 212 of the value of this flag if the CPU supports it. Alternatively, when 213 ``BRANCH_PROTECTION`` is enabled, this flag is superseded. 214 215- ``CTX_INCLUDE_SVE_REGS``: Boolean option that, when set to 1, will cause the 216 SVE registers to be included when saving and restoring the CPU context. Note 217 that this build option requires ``ENABLE_SVE_FOR_SWD`` to be enabled. In 218 general, it is recommended to perform SVE context management in lower ELs 219 and skip in EL3 due to the additional cost of maintaining large data 220 structures to track the SVE state. Hence, the default value is 0. 221 222- ``DEBUG``: Chooses between a debug and release build. It can take either 0 223 (release) or 1 (debug) as values. 0 is the default. 224 225- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 226 authenticated decryption algorithm to be used to decrypt firmware/s during 227 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 228 this flag is ``none`` to disable firmware decryption which is an optional 229 feature as per TBBR. 230 231- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 232 of the binary image. If set to 1, then only the ELF image is built. 233 0 is the default. 234 235- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded 236 PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards. 237 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 238 mechanism. Default is ``0``. 239 240- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 241 Board Boot authentication at runtime. This option is meant to be enabled only 242 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 243 flag has to be enabled. 0 is the default. 244 245- ``E``: Boolean option to make warnings into errors. Default is 1. 246 247 When specifying higher warnings levels (``W=1`` and higher), this option 248 defaults to 0. This is done to encourage contributors to use them, as they 249 are expected to produce warnings that would otherwise fail the build. New 250 contributions are still expected to build with ``W=0`` and ``E=1`` (the 251 default). 252 253- ``EARLY_CONSOLE``: This option is used to enable early traces before default 254 console is properly setup. It introduces EARLY_* traces macros, that will 255 use the non-EARLY traces macros if the flag is enabled, or do nothing 256 otherwise. To use this feature, platforms will have to create the function 257 plat_setup_early_console(). 258 Default is 0 (disabled) 259 260- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 261 the normal boot flow. It must specify the entry point address of the EL3 262 payload. Please refer to the "Booting an EL3 payload" section for more 263 details. 264 265- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 266 (also known as group 1 counters). These are implementation-defined counters, 267 and as such require additional platform configuration. Default is 0. 268 269- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 270 are compiled out. For debug builds, this option defaults to 1, and calls to 271 ``assert()`` are left in place. For release builds, this option defaults to 0 272 and calls to ``assert()`` function are compiled out. This option can be set 273 independently of ``DEBUG``. It can also be used to hide any auxiliary code 274 that is only required for the assertion and does not fit in the assertion 275 itself. 276 277- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 278 dumps or not. It is supported in both AArch64 and AArch32. However, in 279 AArch32 the format of the frame records are not defined in the AAPCS and they 280 are defined by the implementation. This implementation of backtrace only 281 supports the format used by GCC when T32 interworking is disabled. For this 282 reason enabling this option in AArch32 will force the compiler to only 283 generate A32 code. This option is enabled by default only in AArch64 debug 284 builds, but this behaviour can be overridden in each platform's Makefile or 285 in the build command line. 286 287- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 288 extensions. This flag can take the values 0 to 2, to align with the 289 ``ENABLE_FEAT`` mechanism. This is an optional architectural feature 290 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 291 and this option can be used to enable this feature on those systems as well. 292 This flag can take the values 0 to 2, the default is 0. 293 294- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 295 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 296 onwards. This flag can take the values 0 to 2, to align with the 297 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 298 299- ``ENABLE_FEAT_CLRBHB``: Numeric value to enable the CLRBHB instruction. 300 Clear Branch History clears the branch history for the current context to 301 the extent that branch history information created before the CLRBHB instruction 302 cannot be used by code. This is an optional architectural feature available on v8.0 303 onwards and is a mandatory feature from v8.9 onwards. 304 This flag can take the values of 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 305 Default value is ``0``. 306 307- ``ENABLE_FEAT_CPA2``: Numeric value to enable the ``FEAT_CPA2`` extension. 308 It enables checked pointer arithmetic in EL3, which will result in address 309 faults in the event that a pointer arithmetic overflow error occurs. This is 310 an optional feature starting from Arm v9.4 and This flag can take values 0 to 311 2, to align with the ``ENABLE_FEAT`` mechanism. Default value is ``0``. 312 313- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 314 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 315 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 316 optional feature available on Arm v8.0 onwards. This flag can take values 317 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 318 Default value is ``0``. 319 320- ``ENABLE_FEAT_CSV2_3``: Numeric value to enable support for ``FEAT_CSV2_3`` 321 extension. This feature is supported in AArch64 state only and is an optional 322 feature available in Arm v8.0 implementations. 323 ``FEAT_CSV2_3`` implies the implementation of ``FEAT_CSV2_2``. 324 The flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 325 mechanism. Default value is ``0``. 326 327- ``ENABLE_FEAT_DEBUGV8P9``: Numeric value to enable ``FEAT_DEBUGV8P9`` 328 extension which allows the ability to implement more than 16 breakpoints 329 and/or watchpoints. This feature is mandatory from v8.9 and is optional 330 from v8.8. This flag can take the values of 0 to 2, to align with the 331 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 332 333- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 334 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 335 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 336 and upwards. This flag can take the values 0 to 2, to align with the 337 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 338 339- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 340 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 341 Physical Offset register) during EL2 to EL3 context save/restore operations. 342 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 343 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 344 mechanism. Default value is ``0``. 345 346- ``ENABLE_FEAT_FPMR``: Numerical value to enable support for Floating Point 347 Mode Register feature, allowing access to the FPMR register. FPMR register 348 controls the behaviors of FP8 instructions. It is an optional architectural 349 feature from v9.2 and upwards. This flag can take value of 0 to 2, to align 350 with the ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 351 352- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 353 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 354 Read Trap Register) during EL2 to EL3 context save/restore operations. 355 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 356 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 357 mechanism. Default value is ``0``. 358 359- ``ENABLE_FEAT_FGT2``: Numeric value to enable support for FGT2 360 (Fine Grain Traps 2) feature allowing for access to Fine-grained trap 2 registers 361 during EL2 to EL3 context save/restore operations. 362 Its an optional architectural feature and is available from v8.8 and upwards. 363 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 364 mechanism. Default value is ``0``. 365 366- ``ENABLE_FEAT_FGWTE3``: Numeric value to enable support for 367 Fine Grained Write Trap EL3 (FEAT_FGWTE3), a feature that allows EL3 to 368 restrict overwriting certain EL3 registers after boot. 369 This lockdown is established by setting individual trap bits for 370 system registers that are not expected to be overwritten after boot. 371 This feature is an optional architectural feature and is available from 372 Armv9.4 onwards. This flag can take values from 0 to 2, aligning with 373 the ``ENABLE_FEAT`` mechanism. The default value is 0. 374 375 .. note:: 376 This feature currently traps access to all EL3 registers in 377 ``FGWTE3_EL3``, except for ``MDCR_EL3``, ``MPAM3_EL3``, 378 ``TPIDR_EL3``(when ``CRASH_REPORTING=1``), and 379 ``SCTLR_EL3``(when ``HW_ASSISTED_COHERENCY=0``). 380 If additional traps need to be disabled for specific platforms, 381 please contact the Arm team on `TF-A public mailing list`_. 382 383- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 384 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 385 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 386 mandatory architectural feature and is enabled from v8.7 and upwards. This 387 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 388 mechanism. Default value is ``0``. 389 390- ``ENABLE_FEAT_IDTE3``: Numeric value to set SCR_EL3.TID3/TID5 bits which 391 enables trapping of ID register reads by lower ELs to EL3. This allows EL3 392 to control the feature visibility to lower ELs by returning a sanitized value 393 based on current feature enablement status. Hypervisors are expected to 394 cache ID register during their boot stage. This flag can take the 395 values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 396 Default value is ``0``. This feature is EXPERIMENTAL. 397 398 .. note:: 399 This feature traps all lower EL accesses to Group 3 and Group 5 400 ID registers to EL3. This can incur a performance impact and platforms 401 should enable them only if they have a specific need. 402 403- ``ENABLE_FEAT_MOPS``: Numeric value to enable FEAT_MOPS (Standardization 404 of memory operations) when INIT_UNUSED_NS_EL2=1. 405 This feature is mandatory from v8.8 and enabling of FEAT_MOPS does not 406 require any settings from EL3 as the controls are present in EL2 registers 407 (HCRX_EL2.{MSCEn,MCE2} and SCTLR_EL2.MSCEn) and in most configurations 408 we expect EL2 to be present. But in case of INIT_UNUSED_NS_EL2=1 , 409 EL3 should configure the EL2 registers. This flag 410 can take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 411 Default value is ``0``. 412 413- ``ENABLE_FEAT_MTE2``: Numeric value to enable Memory Tagging Extension2 414 if the platform wants to use this feature and MTE2 is enabled at ELX. 415 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 416 mechanism. Default value is ``0``. 417 418- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 419 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 420 permission fault for any privileged data access from EL1/EL2 to virtual 421 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 422 mandatory architectural feature and is enabled from v8.1 and upwards. This 423 flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 424 mechanism. Default value is ``0``. 425 426- ``ENABLE_FEAT_PAUTH_LR``: Numeric value to enable the ``FEAT_PAUTH_LR`` 427 extension. ``FEAT_PAUTH_LR`` is an optional feature available from Arm v9.4 428 onwards. This feature requires PAUTH to be enabled via the 429 ``BRANCH_PROTECTION`` flag. This flag can take the values 0 to 2, to align 430 with the ``ENABLE_FEAT`` mechanism. Default value is ``0``. 431 432- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 433 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 434 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 435 mechanism. Default value is ``0``. 436 437- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 438 extension. This feature is only supported in AArch64 state. This flag can 439 take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 440 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 441 Armv8.5 onwards. 442 443- ``ENABLE_FEAT_SB``: Numeric option to let the TF-A code use the ``FEAT_SB`` 444 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 445 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 446 later CPUs. It is enabled from v8.5 and upwards and if needed can be 447 overidden from platforms explicitly. This flag can take values 0 to 2, to 448 align with the ``ENABLE_FEAT`` mechanism. Default value is ``0``. 449 450- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 451 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 452 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 453 mechanism. Default is ``0``. 454 455- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 456 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 457 available on Arm v8.6. This flag can take values 0 to 2, to align with the 458 ``ENABLE_FEAT`` mechanism. Default is ``0``. 459 460 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 461 delayed by the amount of value in ``TWED_DELAY``. 462 463- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 464 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 465 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 466 architectural feature and is enabled from v8.1 and upwards. It can take 467 values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 468 Default value is ``0``. 469 470- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 471 allow access to TCR2_EL2 (extended translation control) from EL2 as 472 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 473 mandatory architectural feature and is enabled from v8.9 and upwards. This 474 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 475 mechanism. Default value is ``0``. 476 477- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 478 at EL2 and below, and context switch relevant registers. This flag 479 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 480 mechanism. Default value is ``0``. 481 482- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 483 at EL2 and below, and context switch relevant registers. This flag 484 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 485 mechanism. Default value is ``0``. 486 487- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 488 at EL2 and below, and context switch relevant registers. This flag 489 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 490 mechanism. Default value is ``0``. 491 492- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 493 at EL2 and below, and context switch relevant registers. This flag 494 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 495 mechanism. Default value is ``0``. 496 497- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to 498 allow use of Guarded Control Stack from EL2 as well as adding the GCS 499 registers to the EL2 context save/restore operations. This flag can take 500 the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 501 Default value is ``0``. 502 503 - ``ENABLE_FEAT_GCIE``: Boolean value to enable support for the GICv5 CPU 504 interface (see ``USE_GIC_DRIVER`` for the IRI). GICv5 and GICv3 are mutually 505 exclusive, so the ``ENABLE_FEAT`` mechanism is currently not supported. 506 Default value is ``0``. 507 508- ``ENABLE_FEAT_THE``: Numeric value to enable support for FEAT_THE 509 (Translation Hardening Extension) at EL2 and below, setting the bit 510 SCR_EL3.RCWMASKEn in EL3 to allow access to RCWMASK_EL1 and RCWSMASK_EL1 511 registers and context switch them. 512 Its an optional architectural feature and is available from v8.8 and upwards. 513 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 514 mechanism. Default value is ``0``. 515 516- ``ENABLE_FEAT_SCTLR2``: Numeric value to enable support for FEAT_SCTLR2 517 (Extension to SCTLR_ELx) at EL2 and below, setting the bit 518 SCR_EL3.SCTLR2En in EL3 to allow access to SCTLR2_ELx registers and 519 context switch them. This feature is OPTIONAL from Armv8.0 implementations 520 and mandatory in Armv8.9 implementations. 521 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 522 mechanism. Default value is ``0``. 523 524- ``ENABLE_FEAT_D128``: Numeric value to enable support for FEAT_D128 525 at EL2 and below, setting the bit SCT_EL3.D128En in EL3 to allow access to 526 128 bit version of system registers like PAR_EL1, TTBR0_EL1, TTBR1_EL1, 527 TTBR0_EL2, TTBR1_EL2, TTBR0_EL12, TTBR1_EL12 , VTTBR_EL2, RCWMASK_EL1, and 528 RCWSMASK_EL1. Its an optional architectural feature and is available from 529 9.3 and upwards. 530 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 531 mechanism. Default value is ``0``. 532 533- ``ENABLE_FEAT_UINJ``: Numerical value to enable FEAT_UINJ support which 534 is hardware based injection of undefined instruction exceptions. 535 The objective of this feature is to provide higher privilege software with a 536 future proofed mechanism to inject an Undefined Instruction exception into 537 lower privilege software. It is an optional architectural feature from v9.0 538 and mandatory from v9.6. This flag can take value of 0 to 2, 539 to align with the ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 540 541- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 542 support. This option is currently only supported for AArch64. On GCC it only 543 applies to TF-A proper, and not its libraries. If LTO on libraries (except 544 the libc) is desired a platform can pass `-flto -ffat-lto-objects` as long as 545 GCC >= 14 is in use. ``ENABLE_LTO`` is enabled by default on release builds. 546 Default is 0. 547 548- ``ENABLE_FEAT_MPAM``: Numeric value to enable lower ELs to use MPAM 549 feature. MPAM is an optional Armv8.4 extension that enables various memory 550 system components and resources to define partitions; software running at 551 various ELs can assign themselves to desired partition to control their 552 performance aspects. 553 554 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 555 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 556 access their own MPAM registers without trapping into EL3. This option 557 doesn't make use of partitioning in EL3, however. Platform initialisation 558 code should configure and use partitions in EL3 as required. This option 559 defaults to ``2`` since MPAM is enabled by default for NS world only. 560 The flag is automatically disabled when the target 561 architecture is AArch32. 562 563- ``ENABLE_FEAT_MPAM_PE_BW_CTRL``: This option enables Armv9.3 MPAM 564 PE-side bandwidth controls and disables traps to EL3/EL2 (when 565 ``INIT_UNUSED_NS_EL2`` = 1). The flag accepts values from 0 to 2, in 566 line with the ``ENABLE_FEAT`` mechanism, and defaults to ``0``. 567 568- ``ENABLE_FEAT_LS64_ACCDATA``: Numeric value to enable access and save and 569 restore the ACCDATA_EL1 system register, at EL2 and below. This flag can 570 take the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 571 Default value is ``0``. 572 573- ``ENABLE_FEAT_AIE``: Numeric value to enable access to the (A)MAIR2 system 574 registers from non-secure world. This flag can take the values 0 to 2, to 575 align with the ``ENABLE_FEAT`` mechanism. 576 Default value is ``0``. 577 578- ``ENABLE_FEAT_PFAR``: Numeric value to enable access to the PFAR system 579 registers from non-secure world. This flag can take the values 0 to 2, to 580 align with the ``ENABLE_FEAT`` mechanism. 581 Default value is ``0``. 582 583- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 584 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 585 firmware to detect and limit high activity events to assist in SoC processor 586 power domain dynamic power budgeting and limit the triggering of whole-rail 587 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 588 589- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 590 support within generic code in TF-A. This option is currently only supported 591 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 592 in BL32 (SP_min) for AARCH32. Default is 0. 593 594- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 595 Measurement Framework(PMF). Default is 0. 596 597- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 598 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 599 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 600 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 601 software. 602 603- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 604 instrumentation which injects timestamp collection points into TF-A to 605 allow runtime performance to be measured. Currently, only PSCI is 606 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 607 as well. Default is 0. 608 609- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 610 extensions. This is an optional architectural feature for AArch64. 611 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 612 mechanism. The default is 2 but is automatically disabled when the target 613 architecture is AArch32. 614 615- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 616 (SVE) for the Non-secure world only. SVE is an optional architectural feature 617 for AArch64. This flag can take the values 0 to 2, to align with the 618 ``ENABLE_FEAT`` mechanism. At this time, this build option cannot be used on 619 systems that have SPM_MM enabled. The default value is 2. 620 621 Note that when SVE is enabled for the Non-secure world, access 622 to SVE, SIMD and floating-point functionality from the Secure world is 623 independently controlled by build option ``ENABLE_SVE_FOR_SWD``. When enabling 624 ``CTX_INCLUDE_FPREGS`` and ``ENABLE_SVE_FOR_NS`` together, it is mandatory to 625 enable ``CTX_INCLUDE_SVE_REGS``. This is to avoid corruption of the Non-secure 626 world data in the Z-registers which are aliased by the SIMD and FP registers. 627 628- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE and FPU/SIMD functionality 629 for the Secure world. SVE is an optional architectural feature for AArch64. 630 The default is 0 and it is automatically disabled when the target architecture 631 is AArch32. 632 633 .. note:: 634 This build flag requires ``ENABLE_SVE_FOR_NS`` to be enabled. When enabling 635 ``ENABLE_SVE_FOR_SWD``, a developer must carefully consider whether 636 ``CTX_INCLUDE_SVE_REGS`` is also needed. 637 638- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 639 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 640 default value is set to "none". "strong" is the recommended stack protection 641 level if this feature is desired. "none" disables the stack protection. For 642 all values other than "none", the ``plat_get_stack_protector_canary()`` 643 platform hook needs to be implemented. The value is passed as the last 644 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 645 646- ``ENABLE_ERRATA_ALL``: This option is used only for testing purposes, Boolean 647 option to enable the workarounds for all errata that TF-A implements. Normally 648 they should be explicitly enabled depending on each platform's needs. Not 649 recommended for release builds. This option is default set to 0. 650 651- ``ENABLE_FEAT_MORELLO`` : Numeric option to enable the Morello capability aware 652 firmware. This flag can take the values 0 to 2, to align with the 653 ``ENABLE_FEAT`` mechanism. This option is experimental and supported only with 654 LLVM CLANG toolchain and not with GCC toolchain. Capability awareness is 655 currently enabled only in BL31 firmware and not in other firmware types of 656 trusted firmware. Enabling this on regular AARCH64 system might not work. 657 658- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 659 flag depends on ``DECRYPTION_SUPPORT`` build flag. 660 661- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 662 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 663 664- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 665 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 666 on ``DECRYPTION_SUPPORT`` build flag. 667 668- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 669 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 670 build flag. 671 672- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 673 deprecated platform APIs, helper functions or drivers within Trusted 674 Firmware as error. It can take the value 1 (flag the use of deprecated 675 APIs as error) or 0. The default is 0. 676 677- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can 678 configure an Arm® Ethos™-N NPU. To use this service the target platform's 679 ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only 680 the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform 681 only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. 682 683- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the 684 Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and 685 ``TRUSTED_BOARD_BOOT`` to be enabled. 686 687- ``ETHOSN_NPU_FW``: location of the NPU firmware binary 688 (```ethosn.bin```). This firmware image will be included in the FIP and 689 loaded at runtime. 690 691- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 692 targeted at EL3. When set ``0`` (default), no exceptions are expected or 693 handled at EL3, and a panic will result. The exception to this rule is when 694 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 695 occuring during normal world execution, are trapped to EL3. Any exception 696 trapped during secure world execution are trapped to the SPMC. This is 697 supported only for AArch64 builds. 698 699- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 700 injection from lower ELs, and this build option enables lower ELs to use 701 Error Records accessed via System Registers to inject faults. This is 702 applicable only to AArch64 builds. 703 704 This feature is intended for testing purposes only, and is advisable to keep 705 disabled for production images. 706 707- ``FIP_NAME``: This is an optional build option which specifies the FIP 708 filename for the ``fip`` target. Default is ``fip.bin``. 709 710- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 711 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 712 713- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 714 715 :: 716 717 0: Encryption is done with Secret Symmetric Key (SSK) which is common 718 for a class of devices. 719 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 720 unique per device. 721 722 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 723 724- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 725 tool to create certificates as per the Chain of Trust described in 726 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 727 include the certificates in the FIP and FWU_FIP. Default value is '0'. 728 729 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 730 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 731 the corresponding certificates, and to include those certificates in the 732 FIP and FWU_FIP. 733 734 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 735 images will not include support for Trusted Board Boot. The FIP will still 736 include the corresponding certificates. This FIP can be used to verify the 737 Chain of Trust on the host machine through other mechanisms. 738 739 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 740 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 741 will not include the corresponding certificates, causing a boot failure. 742 743- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 744 inherent support for specific EL3 type interrupts. Setting this build option 745 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 746 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 747 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 748 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 749 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 750 the Secure Payload interrupts needs to be synchronously handed over to Secure 751 EL1 for handling. The default value of this option is ``0``, which means the 752 Group 0 interrupts are assumed to be handled by Secure EL1. 753 754- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 755 Interrupts, resulting from errors in NS world, will be always trapped in 756 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 757 will be trapped in the current exception level (or in EL1 if the current 758 exception level is EL0). 759 760- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 761 software operations are required for CPUs to enter and exit coherency. 762 However, newer systems exist where CPUs' entry to and exit from coherency 763 is managed in hardware. Such systems require software to only initiate these 764 operations, and the rest is managed in hardware, minimizing active software 765 management. In such systems, this boolean option enables TF-A to carry out 766 build and run-time optimizations during boot and power management operations. 767 This option defaults to 0 and if it is enabled, then it implies 768 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 769 770 If this flag is disabled while the platform which TF-A is compiled for 771 includes cores that manage coherency in hardware, then a compilation error is 772 generated. This is based on the fact that a system cannot have, at the same 773 time, cores that manage coherency in hardware and cores that don't. In other 774 words, a platform cannot have, at the same time, cores that require 775 ``HW_ASSISTED_COHERENCY=1`` and cores that require 776 ``HW_ASSISTED_COHERENCY=0``. 777 778 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 779 translation library (xlat tables v2) must be used; version 1 of translation 780 library is not supported. 781 782- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for 783 implementation defined system register accesses from lower ELs. Default 784 value is ``0``. 785 786- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 787 bottom, higher addresses at the top. This build flag can be set to '1' to 788 invert this behavior. Lower addresses will be printed at the top and higher 789 addresses at the bottom. 790 791- ``INIT_UNUSED_NS_EL2``: This build flag guards code that disables EL2 792 safely in scenario where NS-EL2 is present but unused. This flag is set to 0 793 by default. Platforms without NS-EL2 in use must enable this flag. 794 795- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 796 used for generating the PKCS keys and subsequent signing of the certificate. 797 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 798 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 799 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 800 compatibility. The default value of this flag is ``rsa`` which is the TBBR 801 compliant PKCS#1 RSA 2.1 scheme. 802 803- ``KEY_SIZE``: This build flag enables the user to select the key size for 804 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 805 depend on the chosen algorithm and the cryptographic module. 806 807 +---------------------------+------------------------------------+ 808 | KEY_ALG | Possible key sizes | 809 +===========================+====================================+ 810 | rsa | 1024 , 2048 (default), 3072, 4096 | 811 +---------------------------+------------------------------------+ 812 | ecdsa | 256 (default), 384 | 813 +---------------------------+------------------------------------+ 814 | ecdsa-brainpool-regular | 256 (default) | 815 +---------------------------+------------------------------------+ 816 | ecdsa-brainpool-twisted | 256 (default) | 817 +---------------------------+------------------------------------+ 818 819- ``HASH_ALG``: This build flag enables the user to select the secure hash 820 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 821 The default value of this flag is ``sha256``. 822 823- ``HW_CONFIG_BASE``: This option specifies the location in memory where the DTB 824 should either be loaded by BL2 or can be found by later stages. 825 826- ``LDFLAGS``: Extra user options appended to the linkers' command line in 827 addition to the one set by the build system. 828 829- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 830 output compiled into the build. This should be one of the following: 831 832 :: 833 834 0 (LOG_LEVEL_NONE) 835 10 (LOG_LEVEL_ERROR) 836 20 (LOG_LEVEL_NOTICE) 837 30 (LOG_LEVEL_WARNING) 838 40 (LOG_LEVEL_INFO) 839 50 (LOG_LEVEL_VERBOSE) 840 841 All log output up to and including the selected log level is compiled into 842 the build. The default value is 40 in debug builds and 20 in release builds. 843 844 ``LOG_DEBUG``: Boolean option to enable support for module level internal 845 logs. There can be situation where a module has detail internal debugging 846 logs, these debugging logs may not be required to print even when log level 847 is VERBOSE. Such logs can be put under this flag. This is a file 848 level build flag. By default this should be disabled (``0``) in each file. 849 850- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 851 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 852 provide trust that the code taking the measurements and recording them has 853 not been tampered with. 854 855 This option defaults to 0. 856 857- ``DISCRETE_TPM``: Boolean flag to include support for a Discrete TPM. 858 859 This option defaults to 0. 860 861- ``TPM_INTERFACE``: When ``DISCRETE_TPM=1``, this is a required flag to 862 select the TPM interface. Currently only one interface is supported: 863 864 :: 865 866 FIFO_SPI 867 868- ``MBOOT_TPM_HASH_ALG``: Build flag to select the TPM hash algorithm used during 869 Measured Boot. Currently only accepts ``sha256`` as a valid algorithm. 870 871- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build 872 options to the compiler. An example usage: 873 874 .. code:: make 875 876 MARCH_DIRECTIVE := -march=armv8.5-a 877 878- ``HARDEN_SLS``: used to pass -mharden-sls=all from the TF-A build 879 options to the compiler currently supporting only of the options. 880 GCC documentation: 881 https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mharden-sls 882 883 An example usage: 884 885 .. code:: make 886 887 HARDEN_SLS := 1 888 889 This option defaults to 0. 890 891- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 892 specifies a file that contains the Non-Trusted World private key in PEM 893 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and it 894 will be used to save the key. 895 896- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 897 optional. It is only needed if the platform makefile specifies that it 898 is required in order to build the ``fwu_fip`` target. 899 900- ``NS_TIMER_SWITCH``: (deprecated) Enable save and restore for non-secure 901 timer register contents upon world switch. It can take either 0 (don't save 902 and restore) or 1 (do save and restore). 0 is the default. An SPD may set 903 this to 1 if it wants the timer registers to be saved and restored. This 904 option has been deprecated since it breaks Linux preemption model. 905 906- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 907 for the BL image. It can be either 0 (include) or 1 (remove). The default 908 value is 0. 909 910- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 911 the underlying hardware is not a full PL011 UART but a minimally compliant 912 generic UART, which is a subset of the PL011. The driver will not access 913 any register that is not part of the SBSA generic UART specification. 914 Default value is 0 (a full PL011 compliant UART is present). 915 916- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 917 must be subdirectory of any depth under ``plat/``, and must contain a 918 platform makefile named ``platform.mk``. For example, to build TF-A for the 919 Arm Juno board, select PLAT=juno. 920 921- ``PLATFORM_REPORT_CTX_MEM_USE``: Reports the context memory allocated for 922 each core as well as the global context. The data includes the memory used 923 by each world and each privileged exception level. This build option is 924 applicable only for ``ARCH=aarch64`` builds. The default value is 0. 925 926- ``PLAT_EXTRA_LD_SCRIPT``: Allows the platform to include a custom LD script 927 snippet for any custom sections that cannot be expressed otherwise. Defaults 928 to 0. 929 930- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 931 instead of the normal boot flow. When defined, it must specify the entry 932 point address for the preloaded BL33 image. This option is incompatible with 933 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 934 over ``PRELOADED_BL33_BASE``. 935 936- ``PRESERVE_DSU_PMU_REGS``: This options when enabled allows the platform to 937 save/restore the DynamIQ Shared Unit's(DSU) Performance Monitoring Unit(PMU) 938 registers when the cluster goes through a power cycle. This is disabled by 939 default and platforms that require this feature have to enable them. 940 941- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 942 vector address can be programmed or is fixed on the platform. It can take 943 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 944 programmable reset address, it is expected that a CPU will start executing 945 code directly at the right address, both on a cold and warm reset. In this 946 case, there is no need to identify the entrypoint on boot and the boot path 947 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 948 does not need to be implemented in this case. 949 950- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 951 possible for the PSCI power-state parameter: original and extended State-ID 952 formats. This flag if set to 1, configures the generic PSCI layer to use the 953 extended format. The default value of this flag is 0, which means by default 954 the original power-state format is used by the PSCI implementation. This flag 955 should be specified by the platform makefile and it governs the return value 956 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 957 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 958 set to 1 as well. 959 960- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 961 OS-initiated mode. This option defaults to 0. 962 963- ``ARCH_FEATURE_AVAILABILITY``: Boolean flag to enable support for the 964 optional SMCCC_ARCH_FEATURE_AVAILABILITY call. This option implicitly 965 interacts with IMPDEF_SYSREG_TRAP and software emulation. This option 966 defaults to 0. 967 968- ``ENABLE_FEAT_RAS``: Numeric flag to enable Armv8.2 RAS features. RAS 969 features are an optional extension for pre-Armv8.2 CPUs, but are mandatory 970 for Armv8.2 or later CPUs. NOTE: This flag enables use of IESB capability to 971 reduce entry latency into EL3 even when RAS error handling is not performed 972 on the platform. Hence this flag is recommended to be turned on Armv8.2 and 973 later CPUs. This flag can take the values 0 to 2, to align with the 974 ``ENABLE_FEAT`` mechanism. The default is 0. 975 976- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 977 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 978 entrypoint) or 1 (CPU reset to BL31 entrypoint). 979 The default value is 0. 980 981- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 982 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 983 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 984 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 985 986- ``RME_GPT_BITLOCK_BLOCK``: This defines the block size (in number of 512MB 987- blocks) covered by a single bit of the bitlock structure during RME GPT 988- operations. The lower the block size, the better opportunity for 989- parallelising GPT operations but at the cost of more bits being needed 990- for the bitlock structure. This numeric parameter can take the values 991- from 0 to 512 and must be a power of 2. The value of 0 is special and 992- and it chooses a single spinlock for all GPT L1 table entries. Default 993- value is 1 which corresponds to block size of 512MB per bit of bitlock 994- structure. 995 996- ``RME_GPT_MAX_BLOCK``: Numeric value in MB to define the maximum size of 997 supported contiguous blocks in GPT Library. This parameter can take the 998 values 0, 2, 32 and 512. Setting this value to 0 disables use of Contigious 999 descriptors. Default value is 512. 1000 1001- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 1002 file that contains the ROT private key in PEM format or a PKCS11 URI and 1003 enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is 1004 accepted and it will be used to save the key. 1005 1006- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 1007 certificate generation tool to save the keys used to establish the Chain of 1008 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 1009 1010- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 1011 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 1012 target. 1013 1014- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 1015 file that contains the SCP_BL2 private key in PEM format or a PKCS11 URI. 1016 If ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 1017 1018- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 1019 optional. It is only needed if the platform makefile specifies that it 1020 is required in order to build the ``fwu_fip`` target. 1021 1022- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 1023 Delegated Exception Interface to BL31 image. This defaults to ``0``. 1024 1025 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 1026 set to ``1``. 1027 1028- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 1029 isolated on separate memory pages. This is a trade-off between security and 1030 memory usage. See "Isolating code and read-only data on separate memory 1031 pages" section in :ref:`Firmware Design`. This flag is disabled by default 1032 and affects all BL images. 1033 1034- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 1035 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 1036 allocated in RAM discontiguous from the loaded firmware image. When set, the 1037 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 1038 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 1039 sections are placed in RAM immediately following the loaded firmware image. 1040 1041- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 1042 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 1043 discontiguous from loaded firmware images. When set, the platform need to 1044 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 1045 flag is disabled by default and NOLOAD sections are placed in RAM immediately 1046 following the loaded firmware image. 1047 1048- ``SEPARATE_BL2_FIP``: This option enables the separation of the BL2 FIP image 1049 from the main FIP image. When this option is enabled, the BL2 FIP image is built 1050 as a separate FIP image. The default value is 0. 1051 1052- ``SEPARATE_SIMD_SECTION``: Setting this option to ``1`` allows the SIMD context 1053 data structures to be put in a dedicated memory region as decided by platform 1054 integrator. Default value is ``0`` which means the SIMD context is put in BSS 1055 section of EL3 firmware. 1056 1057- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 1058 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 1059 UEFI+ACPI this can provide a certain amount of OS forward compatibility 1060 with newer platforms that aren't ECAM compliant. 1061 1062- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 1063 This build option is only valid if ``ARCH=aarch64``. The value should be 1064 the path to the directory containing the SPD source, relative to 1065 ``services/spd/``; the directory is expected to contain a makefile called 1066 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 1067 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 1068 cannot be enabled when the ``SPM_MM`` option is enabled. 1069 1070- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 1071 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 1072 execution in BL1 just before handing over to BL31. At this point, all 1073 firmware images have been loaded in memory, and the MMU and caches are 1074 turned off. Refer to the "Debugging options" section for more details. 1075 1076- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 1077 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 1078 component runs at the EL3 exception level. The default value is ``0`` ( 1079 disabled). This configuration supports pre-Armv8.4 platforms (aka not 1080 implementing the ``FEAT_SEL2`` extension). 1081 1082- ``SPMC_AT_EL3_SEL0_SP`` : Boolean option to enable SEL0 SP load support when 1083 ``SPMC_AT_EL3`` is enabled. The default value if ``0`` (disabled). This 1084 option cannot be enabled (``1``) when (``SPMC_AT_EL3``) is disabled. 1085 1086- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 1087 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 1088 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 1089 mechanism should be used. 1090 1091- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 1092 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 1093 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 1094 extension. This is the default when enabling the SPM Dispatcher. When 1095 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 1096 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 1097 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 1098 extension). 1099 1100- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 1101 Partition Manager (SPM) implementation. The default value is ``0`` 1102 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 1103 enabled (``SPD=spmd``). 1104 1105- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 1106 description of secure partitions. The build system will parse this file and 1107 package all secure partition blobs into the FIP. This file is not 1108 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 1109 1110- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 1111 secure interrupts (caught through the FIQ line). Platforms can enable 1112 this directive if they need to handle such interruption. When enabled, 1113 the FIQ are handled in monitor mode and non secure world is not allowed 1114 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 1115 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 1116 1117- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 1118 Platforms can configure this if they need to lower the hardware 1119 limit, for example due to asymmetric configuration or limitations of 1120 software run at lower ELs. The default is the architectural maximum 1121 of 2048 which should be suitable for most configurations, the 1122 hardware will limit the effective VL to the maximum physically supported 1123 VL. 1124 1125- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 1126 Random Number Generator Interface to BL31 image. This defaults to ``0``. 1127 1128- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 1129 Boot feature. When set to '1', BL1 and BL2 images include support to load 1130 and verify the certificates and images in a FIP, and BL1 includes support 1131 for the Firmware Update. The default value is '0'. Generation and inclusion 1132 of certificates in the FIP and FWU_FIP depends upon the value of the 1133 ``GENERATE_COT`` option. 1134 1135 .. warning:: 1136 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 1137 already exist in disk, they will be overwritten without further notice. 1138 1139- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 1140 specifies a file that contains the Trusted World private key in PEM 1141 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and 1142 it will be used to save the key. 1143 1144- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 1145 synchronous, (see "Initializing a BL32 Image" section in 1146 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 1147 synchronous method) or 1 (BL32 is initialized using asynchronous method). 1148 Default is 0. 1149 1150- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 1151 routing model which routes non-secure interrupts asynchronously from TSP 1152 to EL3 causing immediate preemption of TSP. The EL3 is responsible 1153 for saving and restoring the TSP context in this routing model. The 1154 default routing model (when the value is 0) is to route non-secure 1155 interrupts to TSP allowing it to save its context and hand over 1156 synchronously to EL3 via an SMC. 1157 1158 .. note:: 1159 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 1160 must also be set to ``1``. 1161 1162- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and 1163 internal-trusted-storage) as SP in tb_fw_config device tree. 1164 1165- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 1166 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 1167 this delay. It can take values in the range (0-15). Default value is ``0`` 1168 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 1169 Platforms need to explicitly update this value based on their requirements. 1170 1171- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 1172 linker. When the ``LINKER`` build variable points to the armlink linker, 1173 this flag is enabled automatically. To enable support for armlink, platforms 1174 will have to provide a scatter file for the BL image. Currently, Tegra 1175 platforms use the armlink support to compile BL3-1 images. 1176 1177- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 1178 memory region in the BL memory map or not (see "Use of Coherent memory in 1179 TF-A" section in :ref:`Firmware Design`). It can take the value 1 1180 (Coherent memory region is included) or 0 (Coherent memory region is 1181 excluded). Default is 1. 1182 1183- ``USE_KERNEL_DT_CONVENTION``: When this option is enabled, the hardware 1184 device tree is passed to BL33 using register x0, aligning with the expectations 1185 of the Linux kernel on Arm platforms. If this option is disabled, a different 1186 register, typically x1, may be used instead. This build option is 1187 not necessary when firmware handoff is active (that is, when TRANSFER_LIST=1 1188 is set), and it will be removed once all platforms have transitioned to that 1189 convention. 1190 1191- ``USE_DSU_DRIVER``: This flag enables DSU (DynamIQ Shared Unit) driver. 1192 The DSU driver allows save/restore of DSU PMU registers through 1193 ``PRESERVE_DSU_PMU_REGS`` build option, provides access to PMU registers at 1194 EL1 and allows platforms to configure powerdown and power settings of DSU. 1195 1196- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 1197 firmware configuration framework. This will move the io_policies into a 1198 configuration device tree, instead of static structure in the code base. 1199 1200- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 1201 at runtime using fconf. If this flag is enabled, COT descriptors are 1202 statically captured in tb_fw_config file in the form of device tree nodes 1203 and properties. Currently, COT descriptors used by BL2 are moved to the 1204 device tree and COT descriptors used by BL1 are retained in the code 1205 base statically. 1206 1207- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 1208 runtime using firmware configuration framework. The platform specific SDEI 1209 shared and private events configuration is retrieved from device tree rather 1210 than static C structures at compile time. This is only supported if 1211 SDEI_SUPPORT build flag is enabled. 1212 1213- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 1214 and Group1 secure interrupts using the firmware configuration framework. The 1215 platform specific secure interrupt property descriptor is retrieved from 1216 device tree in runtime rather than depending on static C structure at compile 1217 time. 1218 1219- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 1220 This feature creates a library of functions to be placed in ROM and thus 1221 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 1222 is 0. 1223 1224- ``V``: Verbose build. If assigned anything other than 0, the build commands 1225 are printed. Default is 0. 1226 1227- ``VERSION_STRING``: String used in the log output for each TF-A image. 1228 Defaults to a string formed by concatenating the version number, build type 1229 and build string. 1230 1231- ``W``: Warning level. Some compiler warning options of interest have been 1232 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 1233 each level enabling more warning options. Default is 0. 1234 1235 This option is closely related to the ``E`` option, which enables 1236 ``-Werror``. 1237 1238 - ``W=0`` (default) 1239 1240 Enables a wide assortment of warnings, most notably ``-Wall`` and 1241 ``-Wextra``, as well as various bad practices and things that are likely to 1242 result in errors. Includes some compiler specific flags. No warnings are 1243 expected at this level for any build. 1244 1245 - ``W=1`` 1246 1247 Enables warnings we want the generic build to include but are too time 1248 consuming to fix at the moment. It re-enables warnings taken out for 1249 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1250 to eventually be merged into ``W=0``. Some warnings are expected on some 1251 builds, but new contributions should not introduce new ones. 1252 1253 - ``W=2`` (recommended) 1254 1255 Enables warnings we want the generic build to include but cannot be enabled 1256 due to external libraries. This level is expected to eventually be merged 1257 into ``W=0``. Lots of warnings are expected, primarily from external 1258 libraries like zlib and compiler-rt, but new controbutions should not 1259 introduce new ones. 1260 1261 - ``W=3`` 1262 1263 Enables warnings that are informative but not necessary and generally too 1264 verbose and frequently ignored. A very large number of warnings are 1265 expected. 1266 1267 The exact set of warning flags depends on the compiler and TF-A warning 1268 level, however they are all succinctly set in the top-level Makefile. Please 1269 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1270 individual flags. 1271 1272- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1273 the CPU after warm boot. This is applicable for platforms which do not 1274 require interconnect programming to enable cache coherency (eg: single 1275 cluster platforms). If this option is enabled, then warm boot path 1276 enables D-caches immediately after enabling MMU. This option defaults to 0. 1277 1278- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1279 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1280 The default value of this flag is ``0``. 1281 1282 ``AT`` speculative errata workaround disables stage1 page table walk for 1283 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1284 produces either the correct result or failure without TLB allocation. 1285 1286 This boolean option enables errata for all below CPUs. 1287 1288 +---------+--------------+-------------------------+ 1289 | Errata | CPU | Workaround Define | 1290 +=========+==============+=========================+ 1291 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1292 +---------+--------------+-------------------------+ 1293 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1294 +---------+--------------+-------------------------+ 1295 | 1541130 | Cortex-A65 | ``ERRATA_A65_1541130`` | 1296 +---------+--------------+-------------------------+ 1297 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1298 +---------+--------------+-------------------------+ 1299 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1300 +---------+--------------+-------------------------+ 1301 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1302 +---------+--------------+-------------------------+ 1303 1304 .. note:: 1305 This option is enabled by build only if platform sets any of above defines 1306 mentioned in ’Workaround Define' column in the table. 1307 If this option is enabled for the EL3 software then EL2 software also must 1308 implement this workaround due to the behaviour of the errata mentioned 1309 in new SDEN document which will get published soon. 1310 1311- ``ERRATA_SME_POWER_DOWN``: Boolean option to disconnect the SME unit (PSTATE.{ZA,SM}=0) 1312 before power down and downgrade a suspend to power down request to a normal 1313 suspend request. This is necessary when software running at lower ELs requests 1314 power down without first clearing these bits. On affected cores, the CME 1315 connected to it will reject its power down request. The default value is 0. 1316 1317- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1318 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1319 This flag is disabled by default. 1320 1321- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1322 host machine where a custom installation of OpenSSL is located, which is used 1323 to build the certificate generation, firmware encryption and FIP tools. If 1324 this option is not set, the default OS installation will be used. 1325 1326- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1327 functions that wait for an arbitrary time length (udelay and mdelay). The 1328 default value is 0. 1329 1330- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1331 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1332 optional architectural feature for AArch64. This flag can take the values 1333 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0 1334 and it is automatically disabled when the target architecture is AArch32. 1335 1336- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1337 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1338 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1339 feature for AArch64. This flag can take the values 0 to 2, to align with the 1340 ``ENABLE_FEAT`` mechanism. The default is 0 and it is automatically 1341 disabled when the target architecture is AArch32. 1342 1343- ``USE_SPINLOCK_CAS``: Numeric value to use FEAT_LSE atomics instead of 1344 load/store exclusive instructions with spinlocks. FEAT_LSE is a mandatory 1345 feature from v8.1, however it is only architecturally guaranteed to work on 1346 "conventional memory" which may not apply to tightly coupled memory (eg. SRAM, 1347 TF-A's usual place). Platforms must check if TF-A's memory can be targetted 1348 by atomics before enabling this feature. Expected to increase performance on 1349 systems with many cores. This flag can take the values 0 to 2, to align with 1350 the ``ENABLE_FEAT`` mechanism. The default is 0. 1351 1352- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1353 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1354 but unused). This feature is available if trace unit such as ETMv4.x, and 1355 ETE(extending ETM feature) is implemented. This flag can take the values 1356 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0. 1357 1358- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1359 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1360 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1361 with the ``ENABLE_FEAT`` mechanism. This flag is disabled by default. 1362 1363- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1364 ``plat_can_cmo`` which will return zero if cache management operations should 1365 be skipped and non-zero otherwise. By default, this option is disabled which 1366 means platform hook won't be checked and CMOs will always be performed when 1367 related functions are called. 1368 1369- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management 1370 firmware interface for the BL31 image. By default its disabled (``0``). 1371 1372- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the 1373 errata mitigation for platforms with a non-arm interconnect using the errata 1374 ABI. By default its disabled (``0``). 1375 1376- ``ENABLE_CONSOLE_GETC``: Boolean option to enable `getc()` feature in console 1377 driver(s). By default it is disabled (``0``) because it constitutes an attack 1378 vector into TF-A by potentially allowing an attacker to inject arbitrary data. 1379 This option should only be enabled on a need basis if there is a use case for 1380 reading characters from the console. 1381 1382GIC driver options 1383-------------------- 1384 1385The generic GIC driver can be included with the ``USE_GIC_DRIVER`` option. It is 1386a numeric option that can take the following values: 1387 1388 - ``0``: generic GIC driver not enabled. Any support is entirely in platform 1389 code. Strongly discouraged for GIC based interrupt controllers. 1390 1391 - ``1``: enable the use of the generic GIC driver but do not include any files 1392 or function definitions. It is then the platform's responsibility to provide 1393 these. This is useful if the platform either has a custom GIC implementation 1394 or an alternative interrupt controller design. Use of this option is strongly 1395 discouraged for standard GIC implementations. 1396 1397 - ``2``: use the GICv2 driver 1398 1399 - ``3``: use the GICv3 driver. See the next section on how to further configure 1400 it. Use this option for GICv4 implementations. Requires calling 1401 ``gic_set_gicr_frames()``. 1402 1403 - ``5``: use the EXPERIMENTAL GICv5 driver. Requires ``ENABLE_FEAT_GCIE=1``. 1404 1405 For GIC driver versions other than ``1``, deciding when to save and restore GIC 1406 context on a power domain state transition, as well as any GIC actions outside 1407 of the PSCI library's visibility are the platform's responsibility. The driver 1408 provides implementations of all necessary subroutines, they only need to be 1409 called as appropriate. 1410 1411GICv3 driver options 1412~~~~~~~~~~~~~~~~~~~~ 1413 1414``USE_GIC_DRIVER=3`` is the preferred way of including GICv3 driver files. The 1415old (deprecated) way of included them is using the directive: 1416``include drivers/arm/gic/v3/gicv3.mk`` 1417 1418The driver can be configured with the following options set in the platform 1419makefile: 1420 1421- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1422 Enabling this option will add runtime detection support for the 1423 GIC-600, so is safe to select even for a GIC500 implementation. 1424 This option defaults to 0. 1425 1426- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1427 for GIC-600 AE. Enabling this option will introduce support to initialize 1428 the FMU. Platforms should call the init function during boot to enable the 1429 FMU and its safety mechanisms. This option defaults to 0. 1430 1431- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1432 functionality. This option defaults to 0 1433 1434- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1435 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1436 functions. This is required for FVP platform which need to simulate GIC save 1437 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1438 1439- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1440 This option defaults to 0. 1441 1442- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1443 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1444 1445Debugging options 1446----------------- 1447 1448To compile a debug version and make the build more verbose use 1449 1450.. code:: shell 1451 1452 make PLAT=<platform> DEBUG=1 V=1 all 1453 1454AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1455(for example Arm-DS) might not support this and may need an older version of 1456DWARF symbols to be emitted by GCC. This can be achieved by using the 1457``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1458the version to 4 is recommended for Arm-DS. 1459 1460When debugging logic problems it might also be useful to disable all compiler 1461optimizations by using ``-O0``. 1462 1463.. warning:: 1464 Using ``-O0`` could cause output images to be larger and base addresses 1465 might need to be recalculated (see the **Memory layout on Arm development 1466 platforms** section in the :ref:`Firmware Design`). 1467 1468Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1469``LDFLAGS``: 1470 1471.. code:: shell 1472 1473 CFLAGS='-O0 -gdwarf-2' \ 1474 make PLAT=<platform> DEBUG=1 V=1 all 1475 1476Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1477ignored as the linker is called directly. 1478 1479It is also possible to introduce an infinite loop to help in debugging the 1480post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1481``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1482section. In this case, the developer may take control of the target using a 1483debugger when indicated by the console output. When using Arm-DS, the following 1484commands can be used: 1485 1486:: 1487 1488 # Stop target execution 1489 interrupt 1490 1491 # 1492 # Prepare your debugging environment, e.g. set breakpoints 1493 # 1494 1495 # Jump over the debug loop 1496 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1497 1498 # Resume execution 1499 continue 1500 1501.. _build_options_experimental: 1502 1503Experimental build options 1504--------------------------- 1505 1506Common build options 1507~~~~~~~~~~~~~~~~~~~~ 1508 1509- ``DICE_PROTECTION_ENVIRONMENT``: Boolean flag to specify the measured boot 1510 backend when ``MEASURED_BOOT`` is enabled. The default value is ``0``. When 1511 set to ``1`` then measurements and additional metadata collected during the 1512 measured boot process are sent to the DICE Protection Environment for storage 1513 and processing. A certificate chain, which represents the boot state of the 1514 device, can be queried from the DPE. 1515 1516- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 1517 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 1518 the measurements and recording them as per `PSA DRTM specification`_. For 1519 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 1520 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 1521 should have mechanism to authenticate BL31. This option defaults to 0. 1522 1523- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 1524 Management Extension. This flag can take the values 0 to 2, to align with 1525 the ``ENABLE_FEAT`` mechanism. Default value is 0. 1526 1527- ``ENABLE_FEAT_MEC``: Numeric value to enable support for the ARMv9.2 Memory 1528 Encryption Contexts (MEC). This flag can take the values 0 to 2, to align 1529 with the ``ENABLE_FEAT`` mechanism. MEC supports multiple encryption 1530 contexts for Realm security state and only one encryption context for the 1531 rest of the security states. Default value is 0. 1532 1533- ``RMMD_ENABLE_EL3_TOKEN_SIGN``: Numeric value to enable support for singing 1534 realm attestation token signing requests in EL3. This flag can take the 1535 values 0 and 1. The default value is ``0``. When set to ``1``, this option 1536 enables additional RMMD SMCs to push and pop requests for signing to 1537 EL3 along with platform hooks that must be implemented to service those 1538 requests and responses. 1539 1540- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1541 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 1542 registers so are enabled together. Using this option without 1543 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 1544 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a 1545 superset of SVE. SME is an optional architectural feature for AArch64. 1546 At this time, this build option cannot be used on systems that have 1547 SPD=spmd/SPM_MM and atempting to build with this option will fail. 1548 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 1549 mechanism. Default is 0. 1550 1551- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1552 version 2 (SME2) for the non-secure world only. SME2 is an optional 1553 architectural feature for AArch64. 1554 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME 1555 accesses will still be trapped. This flag can take the values 0 to 2, to 1556 align with the ``ENABLE_FEAT`` mechanism. Default is 0. 1557 1558- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 1559 Extension for secure world. Used along with SVE and FPU/SIMD. 1560 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. 1561 Default is 0. 1562 1563- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM 1564 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support 1565 for logical partitions in EL3, managed by the SPMD as defined in the 1566 FF-A v1.2 specification. This flag is disabled by default. This flag 1567 must not be used if ``SPMC_AT_EL3`` is enabled. 1568 1569- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 1570 verification mechanism. This is a debug feature that compares the 1571 architectural features enabled through the feature specific build flags 1572 (ENABLE_FEAT_xxx) with the features actually available on the CPU running, 1573 and reports any discrepancies. 1574 This flag will also enable errata ordering checking for ``DEBUG`` builds. 1575 1576 It is expected that this feature is only used for flexible platforms like 1577 software emulators, or for hardware platforms at bringup time, to verify 1578 that the configured feature set matches the CPU. 1579 The ``FEATURE_DETECTION`` macro is disabled by default. 1580 1581- ``PSA_CRYPTO``: Boolean option for enabling MbedTLS PSA crypto APIs support. 1582 The platform will use PSA compliant Crypto APIs during authentication and 1583 image measurement process by enabling this option. It uses APIs defined as 1584 per the `PSA Crypto API specification`_. This feature is only supported if 1585 using MbedTLS 3.x version. It is disabled (``0``) by default. 1586 1587- ``LFA_SUPPORT``: Boolean flag to enable support for Live Firmware 1588 activation as per the specification. This option defaults to 0. 1589 1590- ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware 1591 Handoff using Transfer List defined in `Firmware Handoff specification`_. 1592 This defaults to ``0``. Current implementation follows the Firmware Handoff 1593 specification v0.9. 1594 1595- ``USE_DEBUGFS``: When set to 1 this option exposes a virtual filesystem 1596 interface through BL31 as a SiP SMC function. 1597 Default is disabled (0). 1598 1599- ``HOB_LIST``: Setting this to ``1`` enables support for passing boot 1600 information using HOB defined in `Platform Initialization specification`_. 1601 This defaults to ``0``. 1602 1603- ``ENABLE_ACS_SMC``: When set to ``1``, this enables support for ACS SMC 1604 handler code to handle SMC calls from the Architecture Compliance Suite. The 1605 handler is intentionally empty to reserve the SMC section and allow 1606 project-specific implementations in future ACS use cases. 1607 1608Firmware update options 1609~~~~~~~~~~~~~~~~~~~~~~~ 1610 1611- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1612 `PSA FW update specification`_. The default value is 0. 1613 PSA firmware update implementation has few limitations, such as: 1614 1615 - BL2 is not part of the protocol-updatable images. If BL2 needs to 1616 be updated, then it should be done through another platform-defined 1617 mechanism. 1618 1619 - It assumes the platform's hardware supports CRC32 instructions. 1620 1621- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1622 in defining the firmware update metadata structure. This flag is by default 1623 set to '2'. 1624 1625- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1626 firmware bank. Each firmware bank must have the same number of images as per 1627 the `PSA FW update specification`_. 1628 This flag is used in defining the firmware update metadata structure. This 1629 flag is by default set to '1'. 1630 1631- ``PSA_FWU_METADATA_FW_STORE_DESC``: To be enabled when the FWU 1632 metadata contains image description. The default value is 1. 1633 1634 The version 2 of the FWU metadata allows for an opaque metadata 1635 structure where a platform can choose to not include the firmware 1636 store description in the metadata structure. This option indicates 1637 if the firmware store description, which provides information on 1638 the updatable images is part of the structure. 1639 1640-------------- 1641 1642*Copyright (c) 2019-2026, Arm Limited. All rights reserved.* 1643 1644.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1645.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/latest/ 1646.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1647.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1648.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1649.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9 1650.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/ 1651.. _Platform Initialization specification: https://uefi.org/specs/PI/1.8/index.html 1652.. _TF-A public mailing list: https://lists.trustedfirmware.org/mailman3/lists/tf-a.lists.trustedfirmware.org/ 1653