1 /* 2 * Copyright 2019-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <drivers/arm/tzc380.h> 15 #include <drivers/console.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 22 #include <dram.h> 23 #include <gpc.h> 24 #include <imx_aipstz.h> 25 #include <imx_uart.h> 26 #include <imx_rdc.h> 27 #include <imx8m_caam.h> 28 #include <imx8m_ccm.h> 29 #include <imx8m_csu.h> 30 #include <imx8m_snvs.h> 31 #include <platform_def.h> 32 #include <plat_common.h> 33 #include <plat_imx8.h> 34 35 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 36 37 static const mmap_region_t imx_mmap[] = { 38 GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP, 39 CAAM_RAM_MAP, NS_OCRAM_MAP, ROM_MAP, DRAM_MAP, 40 {0}, 41 }; 42 43 static const struct aipstz_cfg aipstz[] = { 44 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 45 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 46 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 47 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 48 {0}, 49 }; 50 51 static struct imx_rdc_cfg rdc[] = { 52 /* Master domain assignment */ 53 RDC_MDAn(RDC_MDA_M7, DID1), 54 55 /* peripherals domain permission */ 56 RDC_PDAPn(RDC_PDAP_UART1, D0R | D0W | D1R | D1W | D2R | D2W | D3R | D3W), 57 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 58 RDC_PDAPn(RDC_PDAP_UART3, D0R | D0W | D1R | D1W | D2R | D2W | D3R | D3W), 59 RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), 60 61 /* memory region */ 62 RDC_MEM_REGIONn(16, 0x0, 0x0, 0xff), 63 RDC_MEM_REGIONn(17, 0x0, 0x0, 0xff), 64 RDC_MEM_REGIONn(18, 0x0, 0x0, 0xff), 65 66 /* Sentinel */ 67 {0}, 68 }; 69 70 static const struct imx_csu_cfg csu_cfg[] = { 71 /* peripherals csl setting */ 72 CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, UNLOCKED), 73 CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, UNLOCKED), 74 75 /* master HP0~1 */ 76 77 /* SA setting */ 78 79 /* HP control setting */ 80 81 /* Sentinel */ 82 {0} 83 }; 84 85 86 static entry_point_info_t bl32_image_ep_info; 87 static entry_point_info_t bl33_image_ep_info; 88 89 /* get SPSR for BL33 entry */ 90 static uint32_t get_spsr_for_bl33_entry(void) 91 { 92 unsigned long el_status; 93 unsigned long mode; 94 uint32_t spsr; 95 96 /* figure out what mode we enter the non-secure world */ 97 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 98 el_status &= ID_AA64PFR0_ELX_MASK; 99 100 mode = (el_status) ? MODE_EL2 : MODE_EL1; 101 102 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 103 return spsr; 104 } 105 106 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 107 u_register_t arg2, u_register_t arg3) 108 { 109 unsigned int console_base = IMX_BOOT_UART_BASE; 110 static console_t console; 111 unsigned int val; 112 int i, ret; 113 114 /* Enable CSU NS access permission */ 115 for (i = 0; i < 64; i++) { 116 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 117 } 118 119 imx_aipstz_init(aipstz); 120 121 if (console_base == 0U) { 122 console_base = imx8m_uart_get_base(); 123 } 124 125 imx_rdc_init(rdc, console_base); 126 127 imx_csu_init(csu_cfg); 128 129 /* 130 * Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes 131 * partial write issue. The AXI2AHB bridge is used for masters that access the TCM 132 * through system bus. Please refer to errata ERR050362 for more information. 133 */ 134 mmio_setbits_32((GPV5_BASE_ADDR + FORCE_INCR_OFFSET), FORCE_INCR_BIT_MASK); 135 136 /* config the ocram memory range for secure access */ 137 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0x4c1); 138 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c); 139 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); 140 141 console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ, 142 IMX_CONSOLE_BAUDRATE, &console); 143 #if DEBUG 144 console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); 145 #else 146 /* This console is only used for boot stage */ 147 console_set_scope(&console, CONSOLE_FLAG_BOOT); 148 #endif 149 150 imx8m_caam_init(); 151 152 /* 153 * tell BL3-1 where the non-secure software image is located 154 * and the entry state information. 155 */ 156 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 157 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 158 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 159 160 #if defined(SPD_opteed) || defined(SPD_trusty) 161 /* Populate entry point information for BL32 */ 162 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 163 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 164 bl32_image_ep_info.pc = BL32_BASE; 165 bl32_image_ep_info.spsr = 0; 166 167 /* Pass TEE base and size to bl33 */ 168 bl33_image_ep_info.args.arg1 = BL32_BASE; 169 bl33_image_ep_info.args.arg2 = BL32_SIZE; 170 171 #ifdef SPD_trusty 172 bl32_image_ep_info.args.arg0 = BL32_SIZE; 173 bl32_image_ep_info.args.arg1 = BL32_BASE; 174 #else 175 /* Make sure memory is clean */ 176 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 177 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 178 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 179 #endif 180 #endif 181 182 ret = imx_bl31_params_parse(arg0, IMX_NS_OCRAM_SIZE, IMX_NS_OCRAM_BASE, 183 &bl32_image_ep_info, &bl33_image_ep_info); 184 if (ret != 0) { 185 imx_bl31_params_parse(arg0, IMX_TCM_BASE, IMX_TCM_SIZE, 186 &bl32_image_ep_info, &bl33_image_ep_info); 187 } 188 189 #if !defined(SPD_opteed) && !defined(SPD_trusty) 190 enable_snvs_privileged_access(); 191 #endif 192 } 193 194 #define MAP_BL31_TOTAL \ 195 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE) 196 #define MAP_BL31_RO \ 197 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) 198 #define MAP_COHERENT_MEM \ 199 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ 200 MT_DEVICE | MT_RW | MT_SECURE) 201 #define MAP_BL32_TOTAL \ 202 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW) 203 204 void bl31_plat_arch_setup(void) 205 { 206 const mmap_region_t bl_regions[] = { 207 MAP_BL31_TOTAL, 208 MAP_BL31_RO, 209 #if USE_COHERENT_MEM 210 MAP_COHERENT_MEM, 211 #endif 212 #if defined(SPD_opteed) || defined(SPD_trusty) 213 /* Map TEE memory */ 214 MAP_BL32_TOTAL, 215 #endif 216 {0} 217 }; 218 219 setup_page_tables(bl_regions, imx_mmap); 220 enable_mmu_el3(0); 221 } 222 223 void bl31_platform_setup(void) 224 { 225 generic_delay_timer_init(); 226 227 /* select the CKIL source to 32K OSC */ 228 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 229 230 /* Init the dram info */ 231 dram_info_init(SAVED_DRAM_TIMING_BASE); 232 233 plat_gic_driver_init(); 234 plat_gic_init(); 235 236 imx_gpc_init(); 237 } 238 239 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 240 { 241 if (type == NON_SECURE) 242 return &bl33_image_ep_info; 243 if (type == SECURE) 244 return &bl32_image_ep_info; 245 246 return NULL; 247 } 248 249 unsigned int plat_get_syscnt_freq2(void) 250 { 251 return COUNTER_FREQUENCY; 252 } 253 254 #ifdef SPD_trusty 255 void plat_trusty_set_boot_args(aapcs64_params_t *args) 256 { 257 args->arg0 = BL32_SIZE; 258 args->arg1 = BL32_BASE; 259 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 260 } 261 #endif 262