1/* 2 * Copyright (c) 2022-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x4.h> 11#include <cpu_macros.S> 12#include "wa_cve_2022_23960_bhb_vector.S" 13 14#include <dsu_macros.S> 15#include <wa_cve_2025_0647_cpprctx.h> 16 17#include <plat_macros.S> 18 19/* Hardware handled coherency */ 20#if HW_ASSISTED_COHERENCY == 0 21#error "Cortex X4 must be compiled with HW_ASSISTED_COHERENCY enabled" 22#endif 23 24/* 64-bit only core */ 25#if CTX_INCLUDE_AARCH32_REGS == 1 26#error "Cortex X4 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 27#endif 28 29cpu_reset_prologue cortex_x4 30 31.global check_erratum_cortex_x4_2726228 32.global check_erratum_cortex_x4_3701758 33 34add_erratum_entry cortex_x4, ERRATUM(2726228), ERRATA_X4_2726228 35 36check_erratum_ls cortex_x4, ERRATUM(2726228), CPU_REV(0, 1) 37 38workaround_runtime_start cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089 39 /* dsb before isb of power down sequence */ 40 dsb sy 41workaround_runtime_end cortex_x4, ERRATUM(2740089) 42 43check_erratum_ls cortex_x4, ERRATUM(2740089), CPU_REV(0, 1) 44 45workaround_reset_start cortex_x4, ERRATUM(2763018), ERRATA_X4_2763018 46 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(47) 47workaround_reset_end cortex_x4, ERRATUM(2763018) 48 49check_erratum_ls cortex_x4, ERRATUM(2763018), CPU_REV(0, 1) 50 51workaround_reset_start cortex_x4, ERRATUM(2816013), ERRATA_X4_2816013 52 mrs x1, id_aa64pfr1_el1 53 ubfx x2, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4 54 cbz x2, #1f 55 sysreg_bit_set CORTEX_X4_CPUACTLR5_EL1, BIT(14) 561: 57workaround_reset_end cortex_x4, ERRATUM(2816013) 58 59check_erratum_ls cortex_x4, ERRATUM(2816013), CPU_REV(0, 1) 60 61workaround_reset_start cortex_x4, ERRATUM(2897503), ERRATA_X4_2897503 62 sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, BIT(8) 63workaround_reset_end cortex_x4, ERRATUM(2897503) 64 65check_erratum_ls cortex_x4, ERRATUM(2897503), CPU_REV(0, 1) 66 67workaround_reset_start cortex_x4, ERRATUM(2900952), ERRATA_DSU_2900952 68 errata_dsu_2900952_wa_apply 69workaround_reset_end cortex_x4, ERRATUM(2900952) 70 71check_erratum_custom_start cortex_x4, ERRATUM(2900952) 72 check_errata_dsu_2900952_applies 73 ret 74check_erratum_custom_end cortex_x4, ERRATUM(2900952) 75 76workaround_reset_start cortex_x4, ERRATUM(2923985), ERRATA_X4_2923985 77 sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, (BIT(11) | BIT(10)) 78workaround_reset_end cortex_x4, ERRATUM(2923985) 79 80check_erratum_ls cortex_x4, ERRATUM(2923985), CPU_REV(0, 1) 81 82workaround_reset_start cortex_x4, ERRATUM(2957258), ERRATA_X4_2957258 83 /* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */ 84 ldr x0, =0x1 85 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */ 86 ldr x0, =0xd5380000 87 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */ 88 ldr x0, =0xFFFFFF40 89 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */ 90 ldr x0, =0x000080010033f 91 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */ 92 isb 93workaround_reset_end cortex_x4, ERRATUM(2957258) 94 95check_erratum_ls cortex_x4, ERRATUM(2957258), CPU_REV(0, 1) 96 97workaround_reset_start cortex_x4, ERRATUM(3076789), ERRATA_X4_3076789 98 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(14) 99 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(13) 100 sysreg_bit_set CORTEX_X4_CPUACTLR_EL1, BIT(52) 101workaround_reset_end cortex_x4, ERRATUM(3076789) 102 103check_erratum_ls cortex_x4, ERRATUM(3076789), CPU_REV(0, 1) 104 105workaround_reset_start cortex_x4, ERRATUM(3133195), ERRATA_X4_3133195 106 ldr x0,=0x2 107 msr s3_6_c15_c8_0,x0 /* msr cpupselr_el3, x0 */ 108 ldr x0,=0xd503225f 109 msr s3_6_c15_c8_2,x0 /* msr cpupor_el3, x0 */ 110 ldr x0,=0xffffffff 111 msr s3_6_c15_c8_3,x0 /* msr cpupmr_el3, x0 */ 112 ldr x0,=0x00000000404003fd 113 msr s3_6_c15_c8_1,x0 /* msr cpupcr_el3, x0 */ 114workaround_reset_end cortex_x4, ERRATUM(3133195) 115 116check_erratum_range cortex_x4, ERRATUM(3133195), CPU_REV(0, 2), CPU_REV(0, 2) 117 118add_erratum_entry cortex_x4, ERRATUM(3701758), ERRATA_X4_3701758 119 120check_erratum_ls cortex_x4, ERRATUM(3701758), CPU_REV(0, 3) 121 122workaround_reset_start cortex_x4, ERRATUM(3887999), ERRATA_X4_3887999 123 sysreg_bit_set CORTEX_X4_CPUACTLR2_EL1, BIT(22) 124workaround_reset_end cortex_x4, ERRATUM(3887999) 125 126check_erratum_ls cortex_x4, ERRATUM(3887999), CPU_REV(0, 3) 127 128/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 129workaround_reset_start cortex_x4, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 130 sysreg_bit_set CORTEX_X4_CPUECTLR_EL1, BIT(46) 131workaround_reset_end cortex_x4, CVE(2024, 5660) 132 133check_erratum_ls cortex_x4, CVE(2024, 5660), CPU_REV(0, 2) 134 135 /* -------------------------------------------------------------- 136 * CVE-2024-7881 is mitigated for Cortex-X4 using erratum 3692983 137 * workaround by disabling the affected prefetcher setting 138 * CPUACTLR6_EL1[41]. 139 * -------------------------------------------------------------- 140 */ 141workaround_reset_start cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 142 sysreg_bit_set CORTEX_X4_CPUACTLR6_EL1, BIT(41) 143workaround_reset_end cortex_x4, CVE(2024, 7881) 144 145check_erratum_ls cortex_x4, CVE(2024, 7881), CPU_REV(0, 2) 146 147 /* 148 * Instruction patch sequence to trap 'cpp rctx' instructions to EL3. 149 * Enables mitigation for CVE-2025-0647. 150 */ 151workaround_reset_start cortex_x4, CVE(2025, 647), WORKAROUND_CVE_2025_0647 152 mov x0, #WA_PATCH_SLOT(3) 153 bl wa_cve_2025_0647_instruction_patch 154workaround_reset_end cortex_x4, CVE(2025, 647) 155 156check_erratum_chosen cortex_x4, CVE(2025, 647), WORKAROUND_CVE_2025_0647 157 158#if WORKAROUND_CVE_2025_0647 159func cortex_x4_impl_defined_el3_handler 160 mov x0, #0 161 162 /* See if this call came from trap handler. */ 163 cmp x1, #EC_IMP_DEF_EL3 164 bne wa_cve_2025_0647_do_cpp_wa 165 orr x0, x0, #WA_IS_TRAP_HANDLER 166 b wa_cve_2025_0647_do_cpp_wa 167endfunc cortex_x4_impl_defined_el3_handler 168#endif 169 170cpu_reset_func_start cortex_x4 171 /* Disable speculative loads */ 172 msr SSBS, xzr 173 enable_mpmm 174cpu_reset_func_end cortex_x4 175 176 /* ---------------------------------------------------- 177 * HW will do the cache maintenance while powering down 178 * ---------------------------------------------------- 179 */ 180func cortex_x4_core_pwr_dwn 181 /* --------------------------------------------------- 182 * Enable CPU power down bit in power control register 183 * --------------------------------------------------- 184 */ 185 sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 186 187 apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089 188 189 isb 190 ret 191endfunc cortex_x4_core_pwr_dwn 192 193 /* --------------------------------------------- 194 * This function provides Cortex X4-specific 195 * register information for crash reporting. 196 * It needs to return with x6 pointing to 197 * a list of register names in ascii and 198 * x8 - x15 having values of registers to be 199 * reported. 200 * --------------------------------------------- 201 */ 202.section .rodata.cortex_x4_regs, "aS" 203cortex_x4_regs: /* The ascii list of register names to be reported */ 204 .asciz "cpuectlr_el1", "" 205 206func cortex_x4_cpu_reg_dump 207 adr x6, cortex_x4_regs 208 mrs x8, CORTEX_X4_CPUECTLR_EL1 209 ret 210endfunc cortex_x4_cpu_reg_dump 211 212#if WORKAROUND_CVE_2025_0647 213declare_cpu_ops_eh cortex_x4, CORTEX_X4_MIDR, \ 214 cortex_x4_reset_func, \ 215 cortex_x4_impl_defined_el3_handler, \ 216 cortex_x4_core_pwr_dwn 217#else 218declare_cpu_ops cortex_x4, CORTEX_X4_MIDR, \ 219 cortex_x4_reset_func, \ 220 cortex_x4_core_pwr_dwn 221#endif 222 223