1/* 2 * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <common/bl_common.ld.h> 8#include <lib/xlat_tables/xlat_tables_defs.h> 9 10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 11OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 12ENTRY(bl2_entrypoint) 13 14MEMORY { 15#if BL2_IN_XIP_MEM 16 ROM (rx): ORIGIN = BL2_RO_BASE, LENGTH = BL2_RO_LIMIT - BL2_RO_BASE 17 RAM (rwx): ORIGIN = BL2_RW_BASE, LENGTH = BL2_RW_LIMIT - BL2_RW_BASE 18#else /* BL2_IN_XIP_MEM */ 19 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE 20#endif /* BL2_IN_XIP_MEM */ 21 22#if SEPARATE_BL2_NOLOAD_REGION 23 RAM_NOLOAD (rw!a): ORIGIN = BL2_NOLOAD_START, LENGTH = BL2_NOLOAD_LIMIT - BL2_NOLOAD_START 24#else /* SEPARATE_BL2_NOLOAD_REGION */ 25# define RAM_NOLOAD RAM 26#endif /* SEPARATE_BL2_NOLOAD_REGION */ 27} 28 29#if !BL2_IN_XIP_MEM 30# define ROM RAM 31#endif /* !BL2_IN_XIP_MEM */ 32 33SECTIONS { 34 RAM_REGION_START = ORIGIN(RAM); 35 RAM_REGION_LENGTH = LENGTH(RAM); 36#if BL2_IN_XIP_MEM 37 ROM_REGION_START = ORIGIN(ROM); 38 ROM_REGION_LENGTH = LENGTH(ROM); 39 40 . = BL2_RO_BASE; 41 42 ASSERT(. == ALIGN(PAGE_SIZE), 43 "BL2_RO_BASE address is not aligned on a page boundary.") 44#else /* BL2_IN_XIP_MEM */ 45 . = BL2_BASE; 46 47 ASSERT(. == ALIGN(PAGE_SIZE), 48 "BL2_BASE address is not aligned on a page boundary.") 49#endif /* BL2_IN_XIP_MEM */ 50 51#if SEPARATE_BL2_NOLOAD_REGION 52 RAM_NOLOAD_REGION_START = ORIGIN(RAM_NOLOAD); 53 RAM_NOLOAD_REGION_LENGTH = LENGTH(RAM_NOLOAD); 54#endif 55 56#if SEPARATE_CODE_AND_RODATA 57 58/* If platform didn't override BL2_TEXT_RESIDENT_LIMIT then set to 4K */ 59#ifndef BL2_TEXT_RESIDENT_LIMIT 60#define BL2_TEXT_RESIDENT_LIMIT U(0x1000) 61#endif 62 63 .text . : { 64 ASSERT(. == ALIGN(PAGE_SIZE), 65 ".text address is not aligned on a page boundary."); 66 67 __TEXT_START__ = .; 68 __TEXT_RESIDENT_START__ = .; 69 70 *bl2_el3_entrypoint.o(.text*) 71 *(.text.asm.*) 72 73 __TEXT_RESIDENT_END__ = .; 74 75 *(SORT_BY_ALIGNMENT(.text*)) 76 *(.vectors) 77 __TEXT_END_UNALIGNED__ = .; 78 79 . = ALIGN(PAGE_SIZE); 80 81 __TEXT_END__ = .; 82 } >ROM 83 84 .rodata . : { 85 __RODATA_START__ = .; 86 87 *(SORT_BY_ALIGNMENT(.rodata*)) 88 89 RODATA_COMMON 90 91 __RODATA_END_UNALIGNED__ = .; 92 . = ALIGN(PAGE_SIZE); 93 94 __RODATA_END__ = .; 95 } >ROM 96 97 ASSERT(__TEXT_RESIDENT_END__ - __TEXT_RESIDENT_START__ <= 98 BL2_TEXT_RESIDENT_LIMIT, 99 "Resident part of BL2 has exceeded its limit.") 100#else /* SEPARATE_CODE_AND_RODATA */ 101 .ro . : { 102 ASSERT(. == ALIGN(PAGE_SIZE), 103 ".ro address is not aligned on a page boundary."); 104 105 __RO_START__ = .; 106 __TEXT_RESIDENT_START__ = .; 107 108 *bl2_el3_entrypoint.o(.text*) 109 *(.text.asm.*) 110 111 __TEXT_RESIDENT_END__ = .; 112 113 *(SORT_BY_ALIGNMENT(.text*)) 114 *(SORT_BY_ALIGNMENT(.rodata*)) 115 116 RODATA_COMMON 117 118 *(.vectors) 119 120 __RO_END_UNALIGNED__ = .; 121 122 /* 123 * Memory page(s) mapped to this section will be marked as read-only, 124 * executable. No RW data from the next section must creep in. Ensure 125 * that the rest of the current memory page is unused. 126 */ 127 . = ALIGN(PAGE_SIZE); 128 129 __RO_END__ = .; 130 } >ROM 131#endif /* SEPARATE_CODE_AND_RODATA */ 132 133/* BL1 will have done this if it's built */ 134#if RESET_TO_BL2 135 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 136 "cpu_ops not defined for this platform.") 137#endif 138 139#if BL2_IN_XIP_MEM 140 ROM_REGION_END = .; 141 . = BL2_RW_BASE; 142 143 ASSERT(BL2_RW_BASE == ALIGN(PAGE_SIZE), 144 "BL2_RW_BASE address is not aligned on a page boundary.") 145#endif /* BL2_IN_XIP_MEM */ 146 147 __RW_START__ = .; 148 149 DATA_SECTION >RAM AT>ROM 150 151 __DATA_RAM_START__ = __DATA_START__; 152 __DATA_RAM_END__ = __DATA_END__; 153 154 RELA_SECTION >RAM 155 156#if SEPARATE_BL2_NOLOAD_REGION 157 SAVED_ADDR = .; 158 159 . = BL2_NOLOAD_START; 160 161 __BL2_NOLOAD_START__ = .; 162#endif /* SEPARATE_BL2_NOLOAD_REGION */ 163 164 STACK_SECTION >RAM_NOLOAD 165 BSS_SECTION >RAM_NOLOAD 166 XLAT_TABLE_SECTION >RAM_NOLOAD 167 168#if SEPARATE_BL2_NOLOAD_REGION 169 __BL2_NOLOAD_END__ = .; 170 RAM_NOLOAD_REGION_END = .; 171 172 . = SAVED_ADDR; 173#endif /* SEPARATE_BL2_NOLOAD_REGION */ 174 175#if USE_COHERENT_MEM 176 /* 177 * The base address of the coherent memory section must be page-aligned to 178 * guarantee that the coherent data are stored on their own pages and are 179 * not mixed with normal data. This is required to set up the correct 180 * memory attributes for the coherent data page tables. 181 */ 182 .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 183 __COHERENT_RAM_START__ = .; 184 185 *(.tzfw_coherent_mem) 186 187 __COHERENT_RAM_END_UNALIGNED__ = .; 188 189 /* 190 * Memory page(s) mapped to this section will be marked as device 191 * memory. No other unexpected data must creep in. Ensure the rest of 192 * the current memory page is unused. 193 */ 194 . = ALIGN(PAGE_SIZE); 195 196 __COHERENT_RAM_END__ = .; 197 } >RAM 198#endif /* USE_COHERENT_MEM */ 199 200 __RW_END__ = .; 201 __BL2_END__ = .; 202 203 /DISCARD/ : { 204 *(.dynsym .dynstr .hash .gnu.hash) 205 } 206 207#if BL2_IN_XIP_MEM 208 __BL2_RAM_START__ = ADDR(.data); 209 __BL2_RAM_END__ = .; 210 211 __DATA_ROM_START__ = LOADADDR(.data); 212 __DATA_SIZE__ = SIZEOF(.data); 213 214 /* 215 * The .data section is the last PROGBITS section so its end marks the end 216 * of BL2's RO content in XIP memory. 217 */ 218 __BL2_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__; 219 220 ASSERT(__BL2_ROM_END__ <= BL2_RO_LIMIT, 221 "BL2's RO content has exceeded its limit.") 222#endif /* BL2_IN_XIP_MEM */ 223 224 __BSS_SIZE__ = SIZEOF(.bss); 225 226#if USE_COHERENT_MEM 227 __COHERENT_RAM_UNALIGNED_SIZE__ = 228 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 229#endif /* USE_COHERENT_MEM */ 230 231 RAM_REGION_END = .; 232#if BL2_IN_XIP_MEM 233 ASSERT(. <= BL2_RW_LIMIT, "BL2's RW content has exceeded its limit.") 234#else /* BL2_IN_XIP_MEM */ 235 ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.") 236#endif /* BL2_IN_XIP_MEM */ 237} 238