1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/bl_common.h> 10 #include <common/debug.h> 11 #include <drivers/arm/smmu_v3.h> 12 #include <fconf_hw_config_getter.h> 13 #include <lib/fconf/fconf.h> 14 #include <lib/fconf/fconf_dyn_cfg_getter.h> 15 #include <lib/mmio.h> 16 17 #include <plat/arm/common/arm_config.h> 18 #include <plat/arm/common/plat_arm.h> 19 #include <plat/common/platform.h> 20 21 #include "fvp_private.h" 22 23 static const struct dyn_cfg_dtb_info_t *hw_config_info __unused; 24 25 void __init bl31_early_platform_setup2(u_register_t arg0, 26 u_register_t arg1, u_register_t arg2, u_register_t arg3) 27 { 28 /* Initialize the console to provide early debug support */ 29 arm_console_boot_init(); 30 31 #if (!TRANSFER_LIST && !RESET_TO_BL31 && (!RESET_TO_BL2 || \ 32 ARM_FW_CONFIG_LOAD_ENABLE)) 33 const struct dyn_cfg_dtb_info_t *soc_fw_config_info; 34 35 INFO("BL31 FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1); 36 /* Fill the properties struct with the info from the config dtb */ 37 fconf_populate("FW_CONFIG", arg1); 38 39 soc_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, SOC_FW_CONFIG_ID); 40 if (soc_fw_config_info != NULL) { 41 arg1 = soc_fw_config_info->config_addr; 42 } 43 44 /* 45 * arg2 is currently holding the 'secure' address of HW_CONFIG. 46 * But arm_bl31_early_platform_setup() below expects the 'non-secure' 47 * address of HW_CONFIG (which it will pass to BL33). 48 * This why we need to override arg2 here. 49 */ 50 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 51 assert(hw_config_info != NULL); 52 assert(hw_config_info->secondary_config_addr != 0UL); 53 arg2 = hw_config_info->secondary_config_addr; 54 #endif 55 56 arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3); 57 58 /* Initialize the platform config for future decision making */ 59 fvp_config_setup(); 60 61 /* 62 * Initialize the correct interconnect for this cluster during cold 63 * boot. No need for locks as no other CPU is active. 64 */ 65 fvp_interconnect_init(); 66 67 /* 68 * Enable coherency in interconnect for the primary CPU's cluster. 69 * Earlier bootloader stages might already do this (e.g. Trusted 70 * Firmware's BL1 does it) but we can't assume so. There is no harm in 71 * executing this code twice anyway. 72 * FVP PSCI code will enable coherency for other clusters. 73 */ 74 fvp_interconnect_enable(); 75 76 /* Initialize System level generic or SP804 timer */ 77 fvp_timer_init(); 78 79 /* On FVP RevC, initialize SMMUv3 */ 80 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U) { 81 if (smmuv3_security_init(PLAT_FVP_SMMUV3_BASE) != 0) { 82 /* 83 * Don't proceed for smmuv3 initialization if the 84 * security init failed. 85 */ 86 return; 87 } 88 /* SMMUv3 initialization failure is not fatal */ 89 if (smmuv3_init(PLAT_FVP_SMMUV3_BASE) != 0) { 90 WARN("Failed initializing SMMU.\n"); 91 } 92 } 93 } 94 95 void __init bl31_platform_setup(void) 96 { 97 arm_bl31_platform_setup(); 98 99 #if USE_GIC_DRIVER == 3 100 fvp_pcpu_init(); 101 fvp_gic_driver_pre_init(); 102 #endif 103 } 104 105 #if !TRANSFER_LIST 106 void __init bl31_plat_arch_setup(void) 107 { 108 int rc __unused; 109 uintptr_t hw_config_base_align __unused; 110 size_t mapped_size_align __unused; 111 112 arm_bl31_plat_arch_setup(); 113 114 /* 115 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run. 116 * So there is no BL2 to load the HW_CONFIG dtb into memory before 117 * control is passed to BL31. The code below relies on dynamic mapping 118 * capability, which is not supported by xlat tables lib V1. 119 * TODO: remove the ARM_XLAT_TABLES_LIB_V1 check when its support 120 * gets deprecated. 121 */ 122 #if (!RESET_TO_BL31 && (!RESET_TO_BL2 || ARM_FW_CONFIG_LOAD_ENABLE) && \ 123 !ARM_XLAT_TABLES_LIB_V1) 124 assert(hw_config_info != NULL); 125 assert(hw_config_info->config_addr != 0UL); 126 127 /* Page aligned address and size if necessary */ 128 hw_config_base_align = page_align(hw_config_info->config_addr, DOWN); 129 mapped_size_align = page_align(hw_config_info->config_max_size, UP); 130 131 if ((hw_config_info->config_addr != hw_config_base_align) && 132 (hw_config_info->config_max_size == mapped_size_align)) { 133 mapped_size_align += PAGE_SIZE; 134 } 135 136 /* 137 * map dynamically HW config region with its aligned base address and 138 * size 139 */ 140 rc = mmap_add_dynamic_region((unsigned long long)hw_config_base_align, 141 hw_config_base_align, 142 mapped_size_align, 143 MT_RO_DATA); 144 if (rc != 0) { 145 ERROR("Error while mapping HW_CONFIG device tree (%d).\n", rc); 146 panic(); 147 } 148 149 /* Populate HW_CONFIG device tree with the mapped address */ 150 fconf_populate("HW_CONFIG", hw_config_info->config_addr); 151 152 /* unmap the HW_CONFIG memory region */ 153 rc = mmap_remove_dynamic_region(hw_config_base_align, mapped_size_align); 154 if (rc != 0) { 155 ERROR("Error while unmapping HW_CONFIG device tree (%d).\n", 156 rc); 157 panic(); 158 } 159 #endif /* !RESET_TO_BL31 && !RESET_TO_BL2 && !ARM_XLAT_TABLES_LIB_V1 */ 160 } 161 #endif /* TRANSFER_LIST */ 162 163 unsigned int plat_get_syscnt_freq2(void) 164 { 165 unsigned int counter_base_frequency; 166 167 #if !RESET_TO_BL31 && (!RESET_TO_BL2 || ARM_FW_CONFIG_LOAD_ENABLE) 168 /* Get the frequency through FCONF API for HW_CONFIG */ 169 counter_base_frequency = FCONF_GET_PROPERTY(hw_config, cpu_timer, clock_freq); 170 if (counter_base_frequency > 0U) { 171 return counter_base_frequency; 172 } 173 #endif 174 175 /* Read the frequency from Frequency modes table */ 176 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 177 178 /* The first entry of the frequency modes table must not be 0 */ 179 if (counter_base_frequency == 0U) { 180 panic(); 181 } 182 183 return counter_base_frequency; 184 } 185