Merge changes from topic "qtiseclib_devel" into integration

* changes:
feat(kodiak): build XPU bypass only when bypass is enabled
docs(maintainers): update QTI maintainers
feat(qti): integrate

Merge changes from topic "qtiseclib_devel" into integration

* changes:
feat(kodiak): build XPU bypass only when bypass is enabled
docs(maintainers): update QTI maintainers
feat(qti): integrate access control stub
feat(kodiak): add access control driver
feat(qti): integrate watchdog stub
feat(kodiak): add watchdog driver
feat(qti): extend interrupt dispatcher
feat(qti): integrate qtimer stub
feat(kodiak): add qtimer driver
feat(qti): integrate sec_core stub
feat(kodiak): add sec_core driver

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feat(stm32mp1): make stpmic2 usable for STM32MP1

Update STPMIC2 driver to use it on STM32MP1 especially
STM32MP_STPMIC1L.

Change-Id: I0db727a093a6a85dca7a74be280c0d1af0e54417
Signed-off-by: Pascal

feat(stm32mp1): make stpmic2 usable for STM32MP1

Update STPMIC2 driver to use it on STM32MP1 especially
STM32MP_STPMIC1L.

Change-Id: I0db727a093a6a85dca7a74be280c0d1af0e54417
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>

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docs(maintainers): update QTI maintainers

Add myself to the list of QTI platform maintainers to include the
platform drivers.

Change-Id: I2746d74b182039a2db955e17313f8b439cfe6954
Signed-off-by: Jor

docs(maintainers): update QTI maintainers

Add myself to the list of QTI platform maintainers to include the
platform drivers.

Change-Id: I2746d74b182039a2db955e17313f8b439cfe6954
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

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feat(cpufeat): add support for FEAT_HACDBS

The Hardware accelerator for cleaning Dirty state feature also has two
register just like FEAT_HDBSS. They are guarded by a SCR_EL3 bit which
set for NS wo

feat(cpufeat): add support for FEAT_HACDBS

The Hardware accelerator for cleaning Dirty state feature also has two
register just like FEAT_HDBSS. They are guarded by a SCR_EL3 bit which
set for NS world only and are not context switched as a result. There is
no use for this feature at EL3.

Change-Id: Ica7a312d891a1671df8e9f2adbfe464d96bbcd4d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): add support for FEAT_HDBSS

The Hardware Dirty state tracking structure feature has two registers to
enable tracking at lower ELs which are guarded by an SCR_EL3 bit. Set
that bit for

feat(cpufeat): add support for FEAT_HDBSS

The Hardware Dirty state tracking structure feature has two registers to
enable tracking at lower ELs which are guarded by an SCR_EL3 bit. Set
that bit for NS only and do not context switch the registers. There is
no use of the feature at EL3.

Change-Id: I174a256d70a99abfafc65eed3a2fbdaea5ea946d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): add support for FEAT_STEP2

This feature only needs MDCR_EL3.EnSTEPOP to be written and mdstepop_el1
to be context switched when the next EL is EL1.

Change-Id: I70e2a488f4e50da4b181a0

feat(cpufeat): add support for FEAT_STEP2

This feature only needs MDCR_EL3.EnSTEPOP to be written and mdstepop_el1
to be context switched when the next EL is EL1.

Change-Id: I70e2a488f4e50da4b181a00648c4f608e1da451c
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(docs): update the feature guide to mention FEAT_IDTE3

It is a vital step of adding a feature. Also leave a note to update the
list of features.

Change-Id: I541328356939787e52e45da7ac528cd5e65c

feat(docs): update the feature guide to mention FEAT_IDTE3

It is a vital step of adding a feature. Also leave a note to update the
list of features.

Change-Id: I541328356939787e52e45da7ac528cd5e65c72dd
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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docs(cpufeat): add analysis of 2022 features

Having gone through the list, write down the features that require no
EL3 enablement and leave out the ones that do.

Change-Id: Ifb559006bf4dc57732a267b

docs(cpufeat): add analysis of 2022 features

Having gone through the list, write down the features that require no
EL3 enablement and leave out the ones that do.

Change-Id: Ifb559006bf4dc57732a267bce609250181f6105a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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docs(cpufeat): update 2025 arch feature list

This patch updates Architectural feature list with NA for
features that don't require EL3 enablement after analysis.

Signed-off-by: Arvind Ram Prakash <

docs(cpufeat): update 2025 arch feature list

This patch updates Architectural feature list with NA for
features that don't require EL3 enablement after analysis.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Iaf53c73ec248bf17cc97ba8218275778ce72dae5

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Merge changes from topic "xl/a76-errata" into integration

* changes:
fix(cpus): reorder docs for Cortex-A76 erratum 1165522
fix(cpus): update revisions for Cortex-A76 erratum 1946160

Merge "docs: add services section to FF-A manifest binding" into integration

refactor(platforms): remove A5DS platform (EOL)

The A5DS platform has reached end-of-life.
Keeping it in TF-A may give the impression that it is
still supported. This change removes A5DS support and

refactor(platforms): remove A5DS platform (EOL)

The A5DS platform has reached end-of-life.
Keeping it in TF-A may give the impression that it is
still supported. This change removes A5DS support and
public references to it, while retaining historical
release notes.

Removed:
- plat/arm/board/a5ds/ (entire directory)
- fdts/a5ds.dts

Updated:
- docs/about/maintainers.rst: drop the A5DS board row
- changelog.yaml: remove the "A5DS" taxonomy entry (title/scope)

Notes:
- Historical entries in docs/change-log.md are intentionally untouched.

Change-Id: I3a3f75857adb690c835f40d28ae29a826d28333f
Signed-off-by: Michael Safwat <michael.safwat@arm.com>

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fix(cpus): reorder docs for Cortex-A76 erratum 1165522

The documentation for Cortex-A76 erratum 1165522 is not in
ascending order. Reorder it to comply with the convention.

SDEN documentation:
http

fix(cpus): reorder docs for Cortex-A76 erratum 1165522

The documentation for Cortex-A76 erratum 1165522 is not in
ascending order. Reorder it to comply with the convention.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-885749/latest

Change-Id: I2e7c05d6355dfbaa69170fc098adc1f12edc6658
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): update revisions for Cortex-A76 erratum 1946160

Cortex-A76 erratum 1946160 is a Cat B erratum that applies
to revisions r0p0, r1p0, r2p0, r3p0, r3p1, r4p0, and r4p1.
It is still open.

Ne

fix(cpus): update revisions for Cortex-A76 erratum 1946160

Cortex-A76 erratum 1946160 is a Cat B erratum that applies
to revisions r0p0, r1p0, r2p0, r3p0, r3p1, r4p0, and r4p1.
It is still open.

New revisions are found being affected by erratum 1946160.
Update accordingly.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-885749/latest

Change-Id: I532ce10c3037dd77e31d7df849beb578f8b5e7b4
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76 erratum 1207823

Cortex-A76 erratum 1207823 is a Cat B erratum that applies
to revisions r0p0, r1p0, and r2p0, and is fixed in r3p0.

The exclusive monitor might

fix(cpus): workaround for Cortex-A76 erratum 1207823

Cortex-A76 erratum 1207823 is a Cat B erratum that applies
to revisions r0p0, r1p0, and r2p0, and is fixed in r3p0.

The exclusive monitor might end up tracking an incorrect cache
line in the presence of a VA-alias, causing a false pass on
the exclusive access sequence. This erratum can be avoided by
setting CPUACTLR2_EL1[11] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-885749/latest

Change-Id: Ife06401f3946884872b733f98c08e61f586d8353
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76 erratum 1165347

Cortex-A76 erratum 1165347 is a Cat B erratum that applies
to revisions r0p0, r1p0, and r2p0, and is fixed in r3p0.

This erratum can lead to liv

fix(cpus): workaround for Cortex-A76 erratum 1165347

Cortex-A76 erratum 1165347 is a Cat B erratum that applies
to revisions r0p0, r1p0, and r2p0, and is fixed in r3p0.

This erratum can lead to livelock under certain condition, which
can be avoided by by setting CPUACTLR2_EL1[0] to 1 and CPUACTLR2_EL1[15]
to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-885749/latest

Change-Id: If9817dc26d0df835d749f506de63a4f613735723
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge changes from topics "qemu-sve", "xl/simd-hash" into integration

* changes:
feat(qemu): disable fpregs traps for QEMU in BL31
feat(crypto): enable the runtime instrumentation for crypto ext

Merge changes from topics "qemu-sve", "xl/simd-hash" into integration

* changes:
feat(qemu): disable fpregs traps for QEMU in BL31
feat(crypto): enable the runtime instrumentation for crypto extension
feat(crypto): enable access to SIMD crypto in BL1 and BL2
feat(crypto): enable floating point register traps in EL3
feat(crypto): build flag for SIMD crypto extensions for v8+ platform
refactor(build): add a default filter list for lib cflags

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Merge "fix(cpus): workaround for Cortex-A65AE erratum 1638571" into integration

fix(cpus): workaround for Cortex-A65AE erratum 1638571

Cortex-A65AE erratum 1638571 is a Cat B erratum that applies
to revisions r0p0, r1p0, r1p1, and is still open.

This erratum can be avoided by

fix(cpus): workaround for Cortex-A65AE erratum 1638571

Cortex-A65AE erratum 1638571 is a Cat B erratum that applies
to revisions r0p0, r1p0, r1p1, and is still open.

This erratum can be avoided by disable stage1 page table walk for
lower Els (EL1 and EL0) in EL3, so 'AT' speculative fetch at any
point produces either the correct result or failure without TLB
allocation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1344564/latest

Change-Id: I861230de94a105fd52f9c8ef7e7551a2633c065b
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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feat(crypto): build flag for SIMD crypto extensions for v8+ platform

Add new build flags ENABLE_FEAT_CRYPTO to enable SIMD crypto extension
for hash256 in bootflow authentication process and ENABLE_

feat(crypto): build flag for SIMD crypto extensions for v8+ platform

Add new build flags ENABLE_FEAT_CRYPTO to enable SIMD crypto extension
for hash256 in bootflow authentication process and ENABLE_FEAT_CRYPTO_SHA3
to enable SIMD crypto extension for sha384 and sha512 in bootflow authentication
process for Arm platform greater than v8.0.

Change-Id: I6e52feb318136910d34cafd89319bf94f90e16fc
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): remove C1-Premium erratum 3651221

This erratum workaround is already implemented as part
of CVE-2024-7881 [1] and is redundant. This patch removes
C1-Premium erratum 3651221 [2] support.

fix(cpus): remove C1-Premium erratum 3651221

This erratum workaround is already implemented as part
of CVE-2024-7881 [1] and is redundant. This patch removes
C1-Premium erratum 3651221 [2] support.

[1] : https://developer.arm.com/documentation/110326/latest/
[2] : https://developer.arm.com/documentation/111078/latest/
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I40b37ec62788884ae5c0a0bb3eb4b924622ffe55

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fix(cpus): remove C1-Ultra erratum 3651221

This erratum workaround is already implemented as part
of CVE-2024-7881 [1] and is redundant. This patch removes
C1-Ultra erratum 3651221 [2] support.

[1]

fix(cpus): remove C1-Ultra erratum 3651221

This erratum workaround is already implemented as part
of CVE-2024-7881 [1] and is redundant. This patch removes
C1-Ultra erratum 3651221 [2] support.

[1] : https://developer.arm.com/documentation/110326/latest/
[2] : https://developer.arm.com/documentation/111077/latest/
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: If7ea433e4614f92333e788e3f6b366db22c92f0d

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fix(cpus): correct CVE-2024-7881 workaround and drop duplicate erratum

Fix the CVE-2024-7881 [1] workaround for C1-Pro. The previously
implemented erratum 3684268 [2] programmed the same control bit

fix(cpus): correct CVE-2024-7881 workaround and drop duplicate erratum

Fix the CVE-2024-7881 [1] workaround for C1-Pro. The previously
implemented erratum 3684268 [2] programmed the same control bit and
overlapped functionally with the CVE workaround, so the duplicate
erratum is removed.

Reference:
[1] https://developer.arm.com/documentation/110326/latest/
[2] https://developer.arm.com/documentation/SDEN-3273080/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I6207c49486e4020f34c862ad40ec3137bd3684cc

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Merge changes I8d332dbe,I9d30b6f9,I2fd7eece,Ibcd65f39,I86cc5e97 into integration

* changes:
feat(bl2): support RESET_TO_BL2 and ENABLE_RME
fix(build): fix BL2_CPPFLAGS when ENABLE_RME is set
f

Merge changes I8d332dbe,I9d30b6f9,I2fd7eece,Ibcd65f39,I86cc5e97 into integration

* changes:
feat(bl2): support RESET_TO_BL2 and ENABLE_RME
fix(build): fix BL2_CPPFLAGS when ENABLE_RME is set
fix(fvp): increase resident text size of BL2
fix(arm): support FCONF when TRANSFER_LIST and RESET_BL2 is set
fix(arm): update next image's ep info with the FW config address

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feat(bl2): support RESET_TO_BL2 and ENABLE_RME

When RSE is used as the root of trust along with CPU that supports RME
there is a need to enable both RESET_TO_BL2 and ENABLE_RME.

In current bl2_main

feat(bl2): support RESET_TO_BL2 and ENABLE_RME

When RSE is used as the root of trust along with CPU that supports RME
there is a need to enable both RESET_TO_BL2 and ENABLE_RME.

In current bl2_main there are two different code paths for RESET_BL2,
one handles BL2 running in EL1 and other for BL2 running in EL3.

When RME is enabled, BL2 always runs at EL3 but the current flow calls
bl2_early_platform_setup2, bl2_plat_arch_setup instead of
bl2_el3_early_platform_setup, bl2_el3_plat_arch_setup. Adding RME,
TRANSFER_LIST, ROMLIB support in bl2_el3_* helpers makes
arm_bl2_el3_setup.c almost identical to arm_bl2_setup.c.

This patch removes bl2_el3_plat helpers and related files. Now different
combinations of RESET_TO_BL2, ENABLE_RME are handled in common bl2_setup
routines in arm_bl2_setup.c. This helps to have common place to support
new features and build flags for BL2 irrespective of which EL the BL2
runs.

BREAKING-CHANGE: This patch also changes all existing platform files and
functions that use format bl2_el3_* to bl2_plat helpers. If any platform
or out-of-tree platforms that need to support running BL2 in EL1 or EL3
must now handle it in bl2_early_platform_setup2 and bl2_plat_arch_setup.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I8d332dbe2de1db3b69319496c8d04626cdcf4140

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