fix(cpus): workaround for Cortex-A715 erratum 3711916

Cortex-A715 erratum 3711916 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, r1p2 and r1p3, and is still open.

SDEN documentation

fix(cpus): workaround for Cortex-A715 erratum 3711916

Cortex-A715 erratum 3711916 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, r1p2 and r1p3, and is still open.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2148827

Change-Id: Iad149a2c02a804b3f4f0f2f5b89e866675cb4093
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-A715 erratum 2376701

Cortex-A715 erratum 2376701 is a Cat B erratum that applies to
revisions r0p0 and r1p0, and is fixed in r1p1.

This workaround is not expected t

fix(cpus): workaround for Cortex-A715 erratum 2376701

Cortex-A715 erratum 2376701 is a Cat B erratum that applies to
revisions r0p0 and r1p0, and is fixed in r1p1.

This workaround is not expected to have a significant performance
impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2148827

Change-Id: Idcd2a07d269d55534dc5faa59c454d37426f2cfa
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-A715 erratum 2409570

Cortex-A715 erratum 2409570 is a Cat B erratum that applies to
revisions r0p0 and r1p0, and is fixed in r1p1.

This workaround could have a sign

fix(cpus): workaround for Cortex-A715 erratum 2409570

Cortex-A715 erratum 2409570 is a Cat B erratum that applies to
revisions r0p0 and r1p0, and is fixed in r1p1.

This workaround could have a significant performance impact for
software that relies heavily on using store-release instructions.

This workaround only applies to r1p0, r0p0 has a different
workaround but is not used in production hardware so has not been
implemented.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2148827

Change-Id: Id9429831525b842779d7b7e60f103c93be4acd67
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2

Currently, the FEAT_EBEP feature presence check is only used for UNDEF
injection into lower ELs. However, this feature also aff

fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2

Currently, the FEAT_EBEP feature presence check is only used for UNDEF
injection into lower ELs. However, this feature also affects the access
behavior of MDCR_EL2. Specifically, if the PMEE bits in MDCR_EL3 are not
set to 0b01, then the MDCR_EL2.PMEE bits cannot be configured by EL2.

This patch extends the use of FEAT_EBEP to delegate PMU IRQ and
profiling exception control to EL2 by setting MDCR_EL3.PMEE = 0b01.This
ensures that lower ELs can manage PMU configuration.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib7e1d5c72f017b8ffc2131fc57309dd9d811c973

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feat(cpus): add support for Neoverse-N2 prefetcher

To get accurate and repeatable L2 cache performance metrics,
the L2 region prefetcher must be disabled. This prevents
speculative fetches from inte

feat(cpus): add support for Neoverse-N2 prefetcher

To get accurate and repeatable L2 cache performance metrics,
the L2 region prefetcher must be disabled. This prevents
speculative fetches from interfering with the measurements.

This patch adds a build-time option, NEOVERSE_N2_PREFETCHER_DISABLE,
to set the PF_DIS bit (bit 15) in the CPUECTLR_EL1 register for this
purpose.

Change-Id: Ie7ab9e84bb29d042d0bb2ec697e0c1e39ad5032e
Signed-off-by: Rohit Ner <rohitner@google.com>

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Merge "docs: deprecate Arm RD1AE platform" into integration

Merge changes Ie8453359,Icd58a49c into integration

* changes:
docs: deprecate SPM_MM build option
docs: deprecate NS_TIMER_SWITCH build option

docs: deprecate SPM_MM build option

Following the ML post [1] deprecating the SPM-MM build option.

[1] https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.org/thread/Z6GAD7OG

docs: deprecate SPM_MM build option

Following the ML post [1] deprecating the SPM-MM build option.

[1] https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.org/thread/Z6GAD7OGKNDPNKECJ63HQZ4XEYUJXTNM/

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ie845335989a6b11382ebe2f32962f534ad1bf8c6

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docs: deprecate NS_TIMER_SWITCH build option

Patch [1] deprecated NS_TIMER_SWITCH build option.
Mark it as such in documentation.

Fix build options deprecation/removal section indentation.

[1] htt

docs: deprecate NS_TIMER_SWITCH build option

Patch [1] deprecated NS_TIMER_SWITCH build option.
Mark it as such in documentation.

Fix build options deprecation/removal section indentation.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/42085

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Icd58a49cfe8cc1cfd08bd1fb87d605c614b2fcc3

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docs: deprecate Arm RD1AE platform

RD1AE (Kronos) is now deprecated in TF-A v2.14. Emit a build-time
warning in platform.mk of that platform to make the status explicit.
Update docs/plat/index.rst t

docs: deprecate Arm RD1AE platform

RD1AE (Kronos) is now deprecated in TF-A v2.14. Emit a build-time
warning in platform.mk of that platform to make the status explicit.
Update docs/plat/index.rst to list RD1AE with deleted version set to
TBD.
Drop from the deprecated table platforms that were already deleted in
v2.13 (TC2, fvp_r, SGI-575, RD-N1-Edge, RD-V1, RD-V1-MC).

Change-Id: Ia334a1901fbf303e876e85c8075e2ac7e3fa0d67
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "feat(docs): update context management's threat model" into integration

Merge "docs: add Architectural Feature Support reference" into integration

Merge "fix(security): add clrbhb support" into integration

docs: add Architectural Feature Support reference

Introduce a central document to track the status of Arm architectural
features in TF-A.

This aims to provide a single reference point to check whet

docs: add Architectural Feature Support reference

Introduce a central document to track the status of Arm architectural
features in TF-A.

This aims to provide a single reference point to check whether a given
feature is:
- explicitly supported in TF-A (OK)
- transparent from EL3 (no changes required) (NA)
- Analyzed but decided not to implemened (NO)
- Implementation in progress (WIP)
- not yet analyzed.

This reduces the current reliance on grepping the code, browsing JIRA,
or cross-referencing the Arm ARM to answer feature status queries.

The content is aligned with Arm’s yearly architectural feature updates
(see [Architecture Feature Descriptions](https://developer.arm.com/documentation/109697/latest/)).

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I32cc07268fc641180837a42a973308dab0824236

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Merge "docs: add dependabot patches for LTS" into integration

Merge changes from topic "ahmed-azeem/rdaspen-enhancements" into integration

* changes:
fix(dsu): dsu config for all cores in hot reset
docs(rdaspen): bl32 and GPT support
feat(rdaspen): suppo

Merge changes from topic "ahmed-azeem/rdaspen-enhancements" into integration

* changes:
fix(dsu): dsu config for all cores in hot reset
docs(rdaspen): bl32 and GPT support
feat(rdaspen): support BL32 (OP-TEE)

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Merge changes from topic "gr/spectre_bhb_updates" into integration

* changes:
fix(security): remove CVE_2022_23960 Cortex-X4
fix(security): remove CVE_2022_23960 Neoverse V3
fix(security): rem

Merge changes from topic "gr/spectre_bhb_updates" into integration

* changes:
fix(security): remove CVE_2022_23960 Cortex-X4
fix(security): remove CVE_2022_23960 Neoverse V3
fix(security): remove CVE_2022_23960 Cortex-A720

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Merge "refactor(docs): deduplicate PSCI documentation" into integration

fix(security): add clrbhb support

TF-A mitigates spectre-bhb(CVE-2022-23960) issue with loop
workaround based on - https://developer.arm.com/documentation/110280/latest/

On platforms that support `

fix(security): add clrbhb support

TF-A mitigates spectre-bhb(CVE-2022-23960) issue with loop
workaround based on - https://developer.arm.com/documentation/110280/latest/

On platforms that support `clrbhb` instruction it is recommended to
use `clrbhb` instruction instead of the loop workaround.

Ref- https://developer.arm.com/documentation/102898/0108/

Change-Id: Ie6e56e96378503456a1617d5e5d51bc64c2e0f0b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(security): remove CVE_2022_23960 Neoverse V3

Neoverse V3 has ECBHB implemented and is protected against X-Context
attacks.

Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https

fix(security): remove CVE_2022_23960 Neoverse V3

Neoverse V3 has ECBHB implemented and is protected against X-Context
attacks.

Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https://developer.arm.com/documentation/107734/0002/The-Neoverse--V3--core/Supported-standards-and-specifications?lang=en

Remove WORKAROUND_CVE_2022_23960 to avoid accidental enabling of this
workaround and using loop workaround.

This was accidentally added with
commit@c2a15217c3053117f4d39233002cb1830fa96670

Change-Id: I13b27c04c3da5ec80fa79422b4ef4fee64738caa
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(security): remove CVE_2022_23960 Cortex-A720

Cortex-A720 has ECBHB implemented and is protected against X-Context
attacks.

Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https

fix(security): remove CVE_2022_23960 Cortex-A720

Cortex-A720 has ECBHB implemented and is protected against X-Context
attacks.

Ref: https://developer.arm.com/documentation/110280/latest/
TRM: https://developer.arm.com/documentation/102530/0002/The-Cortex-A720--core/Supported-standards-and-specifications?lang=en

Remove WORKAROUND_CVE_2022_23960 for Cortex-A720 to avoid accidental
enabling of this workaround and using loop workaround.

This was accidentally added with
commit@c2a15217c3053117f4d39233002cb1830fa96670

Change-Id: I3c68b5f5d85ede37a6a039369de8ed2aa9205395
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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refactor(docs): deduplicate PSCI documentation

It is already described in the porting guide and context management
sections so it's largely redundant. It also hasn't been updated for a
while despite

refactor(docs): deduplicate PSCI documentation

It is already described in the porting guide and context management
sections so it's largely redundant. It also hasn't been updated for a
while despite lots going on around PSCI so it's clearly not read often.
The only part that isn't is that for describing a new secure dispatcher,
which belongs in the porting guide.

Change-Id: Icdc53e19565f0785bc8a112e5eb49df1b365c66c
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "docs(build): update GCC toolchain requirement to 14.3.Rel1" into integration

docs(rdaspen): bl32 and GPT support

Added optional BL32 support for the RDaspen platform to enable
Trusted OS integration when required.

Updated documentation to clarify that if BL32 is not set, BL

docs(rdaspen): bl32 and GPT support

Added optional BL32 support for the RDaspen platform to enable
Trusted OS integration when required.

Updated documentation to clarify that if BL32 is not set, BL33 will
load directly after BL31.

Revised the ARM_GPT_SUPPORT description to note that it must be
enabled when the FIP image resides in a GPT partition on Secure Flash.

Change-Id: I79905efd026994290d0bc6c07cdf1f5a903c9194
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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Merge changes from topic "xl/fwu-trial-run" into integration

* changes:
fix(fwu): fwu NV ctr upgraded on trial run
feat(docs): platform hook for whether NV ctr is shared
feat(fwu): add platfor

Merge changes from topic "xl/fwu-trial-run" into integration

* changes:
fix(fwu): fwu NV ctr upgraded on trial run
feat(docs): platform hook for whether NV ctr is shared
feat(fwu): add platform hook for shared NV ctr

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