1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_n3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse-N3 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-N3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24cpu_reset_prologue neoverse_n3 25 26.global check_erratum_neoverse_n3_3699563 27 28workaround_runtime_start neoverse_n3, ERRATUM(3456111), ERRATA_N3_3456111 29 speculation_barrier 30workaround_runtime_end neoverse_n3, ERRATUM(3456111) 31 32check_erratum_ls neoverse_n3, ERRATUM(3456111), CPU_REV(0, 1) 33 34add_erratum_entry neoverse_n3, ERRATUM(3699563), ERRATA_N3_3699563 35 36check_erratum_ls neoverse_n3, ERRATUM(3699563), CPU_REV(0, 0) 37 38cpu_reset_func_start neoverse_n3 39 /* Disable speculative loads */ 40 msr SSBS, xzr 41 apply_erratum neoverse_n3, ERRATUM(3456111), ERRATA_N3_3456111 42 43#if !NEOVERSE_Nx_EXTERNAL_LLC 44 /* ------------------------------------------------------------- 45 * Neoverse n3 has that last level cache is external by default. 46 * Clear the bit when NEOVERSE_Nx_EXTERNAL_LLC is not enabled. 47 * ------------------------------------------------------------- 48 */ 49 sysreg_bit_clear NEOVERSE_N3_CPUECTLR2_EL1, NEOVERSE_N3_CPUECTLR2_EL1_SW_EXT_LLC_BIT 50#endif 51cpu_reset_func_end neoverse_n3 52 53 /* ---------------------------------------------------- 54 * HW will do the cache maintenance while powering down 55 * ---------------------------------------------------- 56 */ 57func neoverse_n3_core_pwr_dwn 58 /* --------------------------------------------------- 59 * Enable CPU power down bit in power control register 60 * --------------------------------------------------- 61 */ 62 sysreg_bit_set NEOVERSE_N3_CPUPWRCTLR_EL1, NEOVERSE_N3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 63 isb 64 ret 65endfunc neoverse_n3_core_pwr_dwn 66 67 /* --------------------------------------------- 68 * This function provides Neoverse-N3 specific 69 * register information for crash reporting. 70 * It needs to return with x6 pointing to 71 * a list of register names in ascii and 72 * x8 - x15 having values of registers to be 73 * reported. 74 * --------------------------------------------- 75 */ 76.section .rodata.neoverse_n3_regs, "aS" 77neoverse_n3_regs: /* The ascii list of register names to be reported */ 78 .asciz "cpuectlr_el1", "" 79 80func neoverse_n3_cpu_reg_dump 81 adr x6, neoverse_n3_regs 82 mrs x8, NEOVERSE_N3_CPUECTLR_EL1 83 ret 84endfunc neoverse_n3_cpu_reg_dump 85 86declare_cpu_ops neoverse_n3, NEOVERSE_N3_MIDR, \ 87 neoverse_n3_reset_func, \ 88 neoverse_n3_core_pwr_dwn 89