1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x925.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-X925 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-X925 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue cortex_x925 26 27workaround_reset_start cortex_x925, ERRATUM(2900952), ERRATA_DSU_2900952 28 errata_dsu_2900952_wa_apply 29workaround_reset_end cortex_x925, ERRATUM(2900952) 30 31check_erratum_custom_start cortex_x925, ERRATUM(2900952) 32 check_errata_dsu_2900952_applies 33 ret 34check_erratum_custom_end cortex_x925, ERRATUM(2900952) 35 36add_erratum_entry cortex_x925, ERRATUM(3701747), ERRATA_X925_3701747 37 38.global check_erratum_cortex_x925_3701747 39check_erratum_ls cortex_x925, ERRATUM(3701747), CPU_REV(0, 1) 40 41workaround_reset_start cortex_x925, ERRATUM(2921199), ERRATA_X925_2921199 42 sysreg_bit_set CORTEX_X925_CPUACTLR5_EL1, BIT(14) 43workaround_reset_end cortex_x925, ERRATUM(2921199) 44 45check_erratum_ls cortex_x925, ERRATUM(2921199), CPU_REV(0, 0) 46 47workaround_reset_start cortex_x925, ERRATUM(2922378), ERRATA_X925_2922378 48 sysreg_bitfield_insert CORTEX_X925_CPUACTLR4_EL1, CORTEX_X925_CPUACTLR4_EL1_BHB_BIT, \ 49 CORTEX_X925_CPUACTLR4_EL1_BHB_SHIFT, CORTEX_X925_CPUACTLR4_EL1_BHB_WIDTH 50workaround_reset_end cortex_x925, ERRATUM(2922378) 51 52check_erratum_ls cortex_x925, ERRATUM(2922378), CPU_REV(0, 0) 53 54workaround_reset_start cortex_x925, ERRATUM(2933290), ERRATA_X925_2933290 55 sysreg_bit_set CORTEX_X925_CPUACTLR5_EL1, BIT(42) 56workaround_reset_end cortex_x925, ERRATUM(2933290) 57 58check_erratum_ls cortex_x925, ERRATUM(2933290), CPU_REV(0, 0) 59 60workaround_reset_start cortex_x925, ERRATUM(2963999), ERRATA_X925_2963999 61 /* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */ 62 ldr x0, =0x0 63 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */ 64 ldr x0, =0xd5380000 65 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */ 66 ldr x0, =0xFFFFFF40 67 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */ 68 ldr x0, =0x000080010033f 69 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */ 70 isb 71workaround_reset_end cortex_x925, ERRATUM(2963999) 72 73check_erratum_ls cortex_x925, ERRATUM(2963999), CPU_REV(0, 0) 74 75workaround_runtime_start cortex_x925, ERRATUM(3324334), ERRATA_X925_3324334 76 speculation_barrier 77workaround_runtime_end cortex_x925, ERRATUM(3324334) 78 79check_erratum_ls cortex_x925, ERRATUM(3324334), CPU_REV(0, 1) 80 81workaround_reset_start cortex_x925, ERRATUM(3692980), ERRATA_X925_3692980 82 sysreg_bit_set CORTEX_X925_CPUACTLR6_EL1, BIT(41) 83workaround_reset_end cortex_x925, ERRATUM(3692980) 84 85check_erratum_ls cortex_x925, ERRATUM(3692980), CPU_REV(0, 1) 86 87/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 88workaround_reset_start cortex_x925, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 89 sysreg_bit_set CORTEX_X925_CPUECTLR_EL1, BIT(46) 90workaround_reset_end cortex_x925, CVE(2024, 5660) 91 92check_erratum_ls cortex_x925, CVE(2024, 5660), CPU_REV(0, 1) 93 94 /* ---------------------------------------------------------------- 95 * CVE-2024-7881 is mitigated for Cortex-X925 using erratum 3692980 96 * workaround by disabling the affected prefetcher setting 97 * CPUACTLR6_EL1[41]. 98 * ---------------------------------------------------------------- 99 */ 100workaround_reset_start cortex_x925, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 101 sysreg_bit_set CORTEX_X925_CPUACTLR6_EL1, BIT(41) 102workaround_reset_end cortex_x925, CVE(2024, 7881) 103 104check_erratum_ls cortex_x925, CVE(2024, 7881), CPU_REV(0, 1) 105 106cpu_reset_func_start cortex_x925 107 /* Disable speculative loads */ 108 msr SSBS, xzr 109 apply_erratum cortex_x925, ERRATUM(3324334), ERRATA_X925_3324334 110 enable_mpmm 111cpu_reset_func_end cortex_x925 112 113 /* ---------------------------------------------------- 114 * HW will do the cache maintenance while powering down 115 * ---------------------------------------------------- 116 */ 117func cortex_x925_core_pwr_dwn 118 /* --------------------------------------------------- 119 * Enable CPU power down bit in power control register 120 * --------------------------------------------------- 121 */ 122 sysreg_bit_set CORTEX_X925_CPUPWRCTLR_EL1, CORTEX_X925_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 123 isb 124 ret 125endfunc cortex_x925_core_pwr_dwn 126 127 /* --------------------------------------------- 128 * This function provides Cortex-X925 specific 129 * register information for crash reporting. 130 * It needs to return with x6 pointing to 131 * a list of register names in ascii and 132 * x8 - x15 having values of registers to be 133 * reported. 134 * --------------------------------------------- 135 */ 136.section .rodata.cortex_x925_regs, "aS" 137cortex_x925_regs: /* The ascii list of register names to be reported */ 138 .asciz "cpuectlr_el1", "" 139 140func cortex_x925_cpu_reg_dump 141 adr x6, cortex_x925_regs 142 mrs x8, CORTEX_X925_CPUECTLR_EL1 143 ret 144endfunc cortex_x925_cpu_reg_dump 145 146declare_cpu_ops cortex_x925, CORTEX_X925_MIDR, \ 147 cortex_x925_reset_func, \ 148 cortex_x925_core_pwr_dwn 149