1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_nano.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Arm C1-Nano must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Arm C1-Nano supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if ERRATA_SME_POWER_DOWN == 0 26#error "Arm C1-Nano needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27#endif 28 29cpu_reset_prologue c1_nano 30 31workaround_reset_start c1_nano, ERRATUM(3392149), ERRATA_C1NANO_3392149 32 sysreg_bit_set C1_NANO_IMP_CPUACTLR3_EL1, BIT(39) 33workaround_reset_end c1_nano, ERRATUM(3392149) 34 35check_erratum_ls c1_nano, ERRATUM(3392149), CPU_REV(0, 0) 36 37workaround_reset_start c1_nano, ERRATUM(3437202), ERRATA_C1NANO_3437202 38 sysreg_bit_set C1_NANO_IMP_CPUACTLR_EL1, BIT(26) 39workaround_reset_end c1_nano, ERRATUM(3437202) 40 41check_erratum_ls c1_nano, ERRATUM(3437202), CPU_REV(0, 0) 42 43workaround_reset_start c1_nano, ERRATUM(3516455), ERRATA_C1NANO_3516455 44#if ENABLE_SME_FOR_NS 45#if ENABLE_SME_FOR_NS == 2 46 is_feat_sme_present_asm x1 47 beq 1f 48#endif 49 50 mov x0, #0 51 msr C1_NANO_IMP_CPUPSELR_EL3, x0 52 isb 53 ldr x0, =0xA0008000 54 msr C1_NANO_IMP_CPUPOR_EL3, x0 55 ldr x0, =0xFE808000 56 msr C1_NANO_IMP_CPUPMR_EL3, x0 57 ldr x0, =0x7F9 58 movk x0, #0x20, LSL #32 59 msr C1_NANO_IMP_CPUPCR_EL3, x0 60 isb 61 mov x0, #1 62 msr C1_NANO_IMP_CPUPSELR_EL3, x0 63 isb 64 ldr x0, =0xA4604000 65 msr C1_NANO_IMP_CPUPOR_EL3, x0 66 ldr x0, =0xBE604000 67 msr C1_NANO_IMP_CPUPMR_EL3, x0 68 ldr x0, =0x7F9 69 movk x0, #0x20, LSL #32 70 msr C1_NANO_IMP_CPUPCR_EL3, x0 71 72 1: 73#endif 74workaround_reset_end c1_nano, ERRATUM(3516455) 75 76check_erratum_ls c1_nano, ERRATUM(3516455), CPU_REV(0, 0) 77 78workaround_reset_start c1_nano, ERRATUM(3616450), ERRATA_C1NANO_3616450 79#if ENABLE_SME_FOR_NS 80#if ENABLE_SME_FOR_NS == 2 81 is_feat_sme_present_asm x1 82 beq 1f 83#endif 84 85 sysreg_bit_set C1_NANO_IMP_CPUACTLR_EL1, BIT(29) 86 87 1: 88#endif 89workaround_reset_end c1_nano, ERRATUM(3616450) 90 91check_erratum_ls c1_nano, ERRATUM(3616450), CPU_REV(0, 0) 92 93cpu_reset_func_start c1_nano 94 /* ---------------------------------------------------- 95 * Disable speculative loads 96 * ---------------------------------------------------- 97 */ 98 msr SSBS, xzr 99 /* model bug: not cleared on reset */ 100 sysreg_bit_clear C1_NANO_IMP_CPUPWRCTLR_EL1, \ 101 C1_NANO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 102 enable_mpmm 103cpu_reset_func_end c1_nano 104 105func c1_nano_core_pwr_dwn 106 /* --------------------------------------------------- 107 * Enable CPU power down bit in power control register 108 * --------------------------------------------------- 109 */ 110 sysreg_bit_toggle C1_NANO_IMP_CPUPWRCTLR_EL1, \ 111 C1_NANO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 112 isb 113 signal_pabandon_handled 114 ret 115endfunc c1_nano_core_pwr_dwn 116 117.section .rodata.c1_nano_regs, "aS" 118c1_nano_regs: /* The ASCII list of register names to be reported */ 119 .asciz "cpuectlr_el1", "" 120 121func c1_nano_cpu_reg_dump 122 adr x6, c1_nano_regs 123 mrs x8, C1_NANO_IMP_CPUECTLR_EL1 124 ret 125endfunc c1_nano_cpu_reg_dump 126 127declare_cpu_ops c1_nano, C1_NANO_MIDR, \ 128 c1_nano_reset_func, \ 129 c1_nano_core_pwr_dwn 130