1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_pro.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Arm C1-Pro must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Arm C1-Pro supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if ERRATA_SME_POWER_DOWN == 0 26#error "Arm C1-Pro needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27#endif 28 29cpu_reset_prologue c1_pro 30 31 /* ----------------------------------------------------------- 32 * CVE-2024-7881 is mitigated for C1-Pro using erratum 3684268 33 * workaround by disabling the affected prefetcher 34 * via IMP_CPUECTLR_EL1[49]. 35 * ----------------------------------------------------------- 36 */ 37workaround_reset_start c1_pro, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 38 sysreg_bit_set C1_PRO_IMP_CPUECTLR_EL1, BIT(49) 39 dsb sy 40workaround_reset_end c1_pro, CVE(2024, 7881) 41 42check_erratum_ls c1_pro, CVE(2024, 7881), CPU_REV(1, 0) 43 44workaround_runtime_start c1_pro, ERRATUM(3338470), ERRATA_C1PRO_3338470 45 speculation_barrier 46workaround_runtime_end c1_pro, ERRATUM(3338470) 47 48check_erratum_ls c1_pro, ERRATUM(3338470), CPU_REV(0, 0) 49 50workaround_reset_start c1_pro, ERRATUM(3362007), ERRATA_C1PRO_3362007 51 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(27) 52workaround_reset_end c1_pro, ERRATUM(3362007) 53 54check_erratum_ls c1_pro, ERRATUM(3362007), CPU_REV(0, 0) 55 56workaround_reset_start c1_pro, ERRATUM(3684268), ERRATA_C1PRO_3684268 57 sysreg_bit_set C1_PRO_IMP_CPUECTLR2_EL1, BIT(49) 58 dsb sy 59workaround_reset_end c1_pro, ERRATUM(3684268) 60 61check_erratum_ls c1_pro, ERRATUM(3684268), CPU_REV(1, 0) 62 63workaround_runtime_start c1_pro, ERRATUM(3686597), ERRATA_C1PRO_3686597 64 /* check if sme feature supported */ 65 is_feat_sme_present_asm x1 66 beq 1f 67 68 sysreg_bit_set C1_PRO_IMP_CPUECTLR_EL1, BIT(57) 69 dsb sy 70 711: 72workaround_runtime_end c1_pro, ERRATUM(3686597) 73 74check_erratum_ls c1_pro, ERRATUM(3686597), CPU_REV(1, 0) 75 76workaround_reset_start c1_pro, ERRATUM(3694158), ERRATA_C1PRO_3694158 77 mov x0, #5 78 msr C1_PRO_IMP_CPUPSELR_EL3, x0 79 isb 80 ldr x0, =0xd503329f 81 msr C1_PRO_IMP_CPUPOR_EL3, x0 82 ldr x0, =0xfffff3ff 83 msr C1_PRO_IMP_CPUPMR_EL3, x0 84 mov x1, #0 85 orr x1, x1, #1<<0 86 orr x1, x1, #3<<4 87 orr x1, x1, #0xf<<6 88 orr x1, x1, #1<<22 89 orr x1, x1, #1<<32 90 msr C1_PRO_IMP_CPUPCR_EL3, x1 91workaround_reset_end c1_pro, ERRATUM(3694158) 92 93check_erratum_ls c1_pro, ERRATUM(3694158), CPU_REV(1, 1) 94 95workaround_reset_start c1_pro, ERRATUM(3706576), ERRATA_C1PRO_3706576 96 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(37) 97workaround_reset_end c1_pro, ERRATUM(3706576) 98 99check_erratum_ls c1_pro, ERRATUM(3706576), CPU_REV(1, 0) 100 101add_erratum_entry c1_pro, ERRATUM(3300099), ERRATA_C1PRO_3300099 102.global check_erratum_c1_pro_3300099 103check_erratum_ls c1_pro, ERRATUM(3300099), CPU_REV(1, 0) 104 105cpu_reset_func_start c1_pro 106 /* ---------------------------------------------------- 107 * Disable speculative loads 108 * ---------------------------------------------------- 109 */ 110 msr SSBS, xzr 111 apply_erratum c1_pro, ERRATUM(3338470), ERRATA_C1PRO_3338470 112 /* model bug: not cleared on reset */ 113 sysreg_bit_clear C1_PRO_IMP_CPUPWRCTLR_EL1, \ 114 C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 115 enable_mpmm 116cpu_reset_func_end c1_pro 117 118 /* ---------------------------------------------------- 119 * HW will do the cache maintenance while powering down 120 * ---------------------------------------------------- 121 */ 122func c1_pro_core_pwr_dwn 123 /* --------------------------------------------------- 124 * Flip CPU power down bit in power control register. 125 * It will be set on powerdown and cleared on wakeup 126 * --------------------------------------------------- 127 */ 128 apply_erratum c1_pro, ERRATUM(3686597), ERRATA_C1PRO_3686597 129 sysreg_bit_toggle C1_PRO_IMP_CPUPWRCTLR_EL1, \ 130 C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 131 isb 132 signal_pabandon_handled 133 ret 134endfunc c1_pro_core_pwr_dwn 135 136 /* --------------------------------------------- 137 * This function provides Arm C1-Pro specific 138 * register information for crash reporting. 139 * It needs to return with x6 pointing to 140 * a list of register names in ascii and 141 * x8 - x15 having values of registers to be 142 * reported. 143 * --------------------------------------------- 144 */ 145.section .rodata.c1_pro_regs, "aS" 146c1_pro_regs: /* The ASCII list of register names to be reported */ 147 .asciz "imp_cpuectlr_el1", "" 148 149func c1_pro_cpu_reg_dump 150 adr x6, c1_pro_regs 151 mrs x8, C1_PRO_IMP_CPUECTLR_EL1 152 ret 153endfunc c1_pro_cpu_reg_dump 154 155declare_cpu_ops c1_pro, C1_PRO_MIDR, \ 156 c1_pro_reset_func, \ 157 c1_pro_core_pwr_dwn 158